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fourkbombfourkbomb
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HACK: i9300: lowlevel init from u-boot 2010.12
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‎board/samsung/i9300/Makefile‎

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# SPDX-License-Identifier: GPL-2.0+
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#
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7-
obj-y += i9300.o
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obj-y += i9300.o lowlevel_init.o mem_init.o clk_init.o

‎board/samsung/i9300/clk_init.S‎

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/*
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* (C) Copyright 2011 Samsung Electronics Co. Ltd
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <config.h>
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#include <asm/arch/cpu.h>
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#define ELFIN_CLOCK_BASE 0x10030000
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#define CLK_SRC_LEFTBUS_OFFSET 0x04200
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#define CLK_DIV_LEFTBUS_OFFSET 0x04500
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#define CLK_SRC_RIGHTBUS_OFFSET 0x08200
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#define CLK_DIV_RIGHTBUS_OFFSET 0x08500
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#define EPLL_LOCK_OFFSET 0x0C010
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#define VPLL_LOCK_OFFSET 0x0C020
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#define EPLL_CON0_OFFSET 0x0C110
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#define EPLL_CON1_OFFSET 0x0C114
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#define EPLL_CON2_OFFSET 0x0C118
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#define VPLL_CON0_OFFSET 0x0C120
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#define VPLL_CON1_OFFSET 0x0C124
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#define VPLL_CON2_OFFSET 0x0C128
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#define CLK_SRC_TOP0_OFFSET 0x0C210
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#define CLK_SRC_TOP1_OFFSET 0x0C214
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#define CLK_SRC_FSYS_OFFSET 0x0C240
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#define CLK_SRC_PERIL0_OFFSET 0x0C250
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#define CLK_DIV_TOP_OFFSET 0x0C510
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#define CLK_DIV_FSYS1_OFFSET 0x0C544
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#define CLK_DIV_FSYS2_OFFSET 0x0C548
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#define CLK_DIV_FSYS3_OFFSET 0x0C54C
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#define CLK_DIV_PERIL0_OFFSET 0x0C550
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#define CLK_SRC_DMC_OFFSET 0x10200
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#define CLK_DIV_DMC0_OFFSET 0x10500
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#define CLK_DIV_DMC1_OFFSET 0x10504
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#define APLL_LOCK_OFFSET 0x14000
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#define MPLL_LOCK_OFFSET 0x14008
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#define APLL_CON0_OFFSET 0x14100
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#define APLL_CON1_OFFSET 0x14104
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#define MPLL_CON0_OFFSET 0x10108
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#define MPLL_CON1_OFFSET 0x1010C
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#define CLK_SRC_CPU_OFFSET 0x14200
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#define CLK_DIV_CPU0_OFFSET 0x14500
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#define CLK_DIV_CPU1_OFFSET 0x14504
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#define S5PV310_POWER_BASE 0x10020000
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#define C2C_CTRL_OFFSET 0x24
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#define APB_DMC_0_BASE 0x10600000
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#define APB_DMC_1_BASE 0x10610000
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#define DMC_CONCONTROL 0x00
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#define DMC_MEMCONTROL 0x04
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#define DMC_PHYCONTROL0 0x18
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#define DMC_PHYCONTROL1 0x1C
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#define DMC_PHYCONTROL2 0x20
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#include "i9300_val.h"
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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#define MEM_DLLl_ON
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.globl system_clock_init_asm
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system_clock_init_asm:
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push {lr}
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ldr r0, =ELFIN_CLOCK_BASE @0x1003_0000
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@ CMU_CPU MUX / DIV
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ldr r1, =0x0
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ldr r2, =CLK_SRC_CPU_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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1: subs r1, r1, #1
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bne 1b
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ldr r1, =CLK_DIV_DMC0_VAL
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ldr r2, =CLK_DIV_DMC0_OFFSET
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str r1, [r0, r2]
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ldr r1, =CLK_DIV_DMC1_VAL
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ldr r2, =CLK_DIV_DMC1_OFFSET
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str r1, [r0, r2]
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@ CMU_TOP MUX / DIV
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ldr r1, =CLK_SRC_TOP0_VAL
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ldr r2, =CLK_SRC_TOP0_OFFSET
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str r1, [r0, r2]
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ldr r1, =CLK_SRC_TOP1_VAL
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ldr r2, =CLK_SRC_TOP1_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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3: subs r1, r1, #1
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bne 3b
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ldr r1, =CLK_DIV_TOP_VAL
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ldr r2, =CLK_DIV_TOP_OFFSET
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str r1, [r0, r2]
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@ CMU_LEFTBUS MUX / DIV
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ldr r1, =CLK_SRC_LEFTBUS_VAL
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ldr r2, =CLK_SRC_LEFTBUS_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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4: subs r1, r1, #1
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bne 4b
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ldr r1, =CLK_DIV_LEFRBUS_VAL
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ldr r2, =CLK_DIV_LEFTBUS_OFFSET
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str r1, [r0, r2]
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@ CMU_RIGHTBUS MUX / DIV
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ldr r1, =CLK_SRC_RIGHTBUS_VAL
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ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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5: subs r1, r1, #1
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bne 5b
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ldr r1, =CLK_DIV_RIGHTBUS_VAL
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ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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@ Set PLL locktime
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ldr r1, =APLL_LOCK_VAL
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ldr r2, =APLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =MPLL_LOCK_VAL
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ldr r2, =MPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =EPLL_LOCK_VAL
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ldr r2, =EPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =VPLL_LOCK_VAL
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ldr r2, =VPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =CLK_DIV_CPU0_VAL
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ldr r2, =CLK_DIV_CPU0_OFFSET
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str r1, [r0, r2]
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ldr r1, =CLK_DIV_CPU1_VAL
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ldr r2, =CLK_DIV_CPU1_OFFSET
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str r1, [r0, r2]
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@ Set APLL
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ldr r1, =APLL_CON1_VAL
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ldr r2, =APLL_CON1_OFFSET
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str r1, [r0, r2]
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ldr r1, =APLL_CON0_VAL
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ldr r2, =APLL_CON0_OFFSET
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str r1, [r0, r2]
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/* check MPLL and if MPLL is not 400 Mhz skip MPLL resetting for C2C operation */
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ldr r2, =MPLL_CON0_OFFSET
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ldr r1, [r0, r2]
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ldr r3, =0xA0640301
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cmp r1, r3
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bne skip_mpll
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@ Set MPLL
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ldr r1, =MPLL_CON1_VAL
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ldr r2, =MPLL_CON1_OFFSET
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str r1, [r0, r2]
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ldr r1, =MPLL_CON0_VAL
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ldr r2, =MPLL_CON0_OFFSET
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str r1, [r0, r2]
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skip_mpll:
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@ Set EPLL
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ldr r1, =EPLL_CON2_VAL
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ldr r2, =EPLL_CON2_OFFSET
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str r1, [r0, r2]
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ldr r1, =EPLL_CON1_VAL
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ldr r2, =EPLL_CON1_OFFSET
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str r1, [r0, r2]
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ldr r1, =EPLL_CON0_VAL
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ldr r2, =EPLL_CON0_OFFSET
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str r1, [r0, r2]
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@ Set VPLL
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ldr r1, =VPLL_CON2_VAL
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ldr r2, =VPLL_CON2_OFFSET
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str r1, [r0, r2]
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ldr r1, =VPLL_CON1_VAL
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ldr r2, =VPLL_CON1_OFFSET
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str r1, [r0, r2]
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ldr r1, =VPLL_CON0_VAL
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ldr r2, =VPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x40000
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6: subs r1, r1, #1
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bne 6b
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ldr r1, =0x01000001
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ldr r2, =CLK_SRC_CPU_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x00011000
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ldr r2, =CLK_SRC_DMC_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x00000110
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ldr r2, =CLK_SRC_TOP0_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x01111000
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ldr r2, =CLK_SRC_TOP1_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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7: subs r1, r1, #1
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bne 7b
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/* check C2C_CTRL enable bit */
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ldr r3, =S5PV310_POWER_BASE
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ldr r4, =C2C_CTRL_OFFSET
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ldr r1, [r3, r4]
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and r1, r1, #1
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cmp r1, #0
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bne v310_2
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@ ConControl
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#ifdef MEM_DLLl_ON
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ldr r0, =APB_DMC_0_BASE
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ldr r1, =0x7F10100A
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ldr r2, =DMC_PHYCONTROL0
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str r1, [r0, r2]
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ldr r1, =0xE0000084
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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ldr r1, =0x7F10100B
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ldr r2, =DMC_PHYCONTROL0
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x20000
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8: subs r1, r1, #1
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bne 8b
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ldr r1, =0x0000008C
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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ldr r1, =0x00000084
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x20000
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9: subs r1, r1, #1
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bne 9b
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ldr r0, =APB_DMC_1_BASE
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ldr r1, =0x7F10100A
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ldr r2, =DMC_PHYCONTROL0
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str r1, [r0, r2]
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ldr r1, =0xE0000084
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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ldr r1, =0x7F10100B
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ldr r2, =DMC_PHYCONTROL0
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x20000
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10: subs r1, r1, #1
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bne 10b
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ldr r1, =0x0000008C
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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ldr r1, =0x00000084
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ldr r2, =DMC_PHYCONTROL1
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x20000
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11: subs r1, r1, #1
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bne 11b
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#endif
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ldr r0, =APB_DMC_0_BASE
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ldr r1, =0x0FFF30FA
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ldr r2, =DMC_CONCONTROL
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str r1, [r0, r2]
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ldr r0, =APB_DMC_1_BASE
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ldr r1, =0x0FFF30FA
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ldr r2, =DMC_CONCONTROL
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str r1, [r0, r2]
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ldr r0, =APB_DMC_0_BASE
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ldr r1, =0x00202533
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ldr r2, =DMC_MEMCONTROL
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str r1, [r0, r2]
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ldr r0, =APB_DMC_1_BASE
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ldr r1, =0x00202533
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ldr r2, =DMC_MEMCONTROL
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str r1, [r0, r2]
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v310_2:
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pop {pc}
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