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HACK: i9300: lowlevel init from u-boot 2010.12

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fourkbomb committed Apr 25, 2018
1 parent e71dd9f commit 2a0f5defffbb53eb4aa4eb0fd2879306b98ef012
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#

obj-y += i9300.o
obj-y += i9300.o lowlevel_init.o mem_init.o clk_init.o
@@ -0,0 +1,333 @@
/*
* (C) Copyright 2011 Samsung Electronics Co. Ltd
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/

#include <config.h>
#include <asm/arch/cpu.h>

#define ELFIN_CLOCK_BASE 0x10030000

#define CLK_SRC_LEFTBUS_OFFSET 0x04200
#define CLK_DIV_LEFTBUS_OFFSET 0x04500

#define CLK_SRC_RIGHTBUS_OFFSET 0x08200
#define CLK_DIV_RIGHTBUS_OFFSET 0x08500

#define EPLL_LOCK_OFFSET 0x0C010
#define VPLL_LOCK_OFFSET 0x0C020
#define EPLL_CON0_OFFSET 0x0C110
#define EPLL_CON1_OFFSET 0x0C114
#define EPLL_CON2_OFFSET 0x0C118
#define VPLL_CON0_OFFSET 0x0C120
#define VPLL_CON1_OFFSET 0x0C124
#define VPLL_CON2_OFFSET 0x0C128

#define CLK_SRC_TOP0_OFFSET 0x0C210
#define CLK_SRC_TOP1_OFFSET 0x0C214
#define CLK_SRC_FSYS_OFFSET 0x0C240
#define CLK_SRC_PERIL0_OFFSET 0x0C250
#define CLK_DIV_TOP_OFFSET 0x0C510
#define CLK_DIV_FSYS1_OFFSET 0x0C544
#define CLK_DIV_FSYS2_OFFSET 0x0C548
#define CLK_DIV_FSYS3_OFFSET 0x0C54C
#define CLK_DIV_PERIL0_OFFSET 0x0C550

#define CLK_SRC_DMC_OFFSET 0x10200
#define CLK_DIV_DMC0_OFFSET 0x10500
#define CLK_DIV_DMC1_OFFSET 0x10504

#define APLL_LOCK_OFFSET 0x14000
#define MPLL_LOCK_OFFSET 0x14008
#define APLL_CON0_OFFSET 0x14100
#define APLL_CON1_OFFSET 0x14104
#define MPLL_CON0_OFFSET 0x10108
#define MPLL_CON1_OFFSET 0x1010C

#define CLK_SRC_CPU_OFFSET 0x14200
#define CLK_DIV_CPU0_OFFSET 0x14500
#define CLK_DIV_CPU1_OFFSET 0x14504


#define S5PV310_POWER_BASE 0x10020000
#define C2C_CTRL_OFFSET 0x24
#define APB_DMC_0_BASE 0x10600000
#define APB_DMC_1_BASE 0x10610000
#define DMC_CONCONTROL 0x00
#define DMC_MEMCONTROL 0x04
#define DMC_PHYCONTROL0 0x18
#define DMC_PHYCONTROL1 0x1C
#define DMC_PHYCONTROL2 0x20

#include "i9300_val.h"

/*
* system_clock_init: Initialize core clock and bus clock.
* void system_clock_init(void)
*/
#define MEM_DLLl_ON

.globl system_clock_init_asm
system_clock_init_asm:
push {lr}

ldr r0, =ELFIN_CLOCK_BASE @0x1003_0000

@ CMU_CPU MUX / DIV
ldr r1, =0x0
ldr r2, =CLK_SRC_CPU_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x10000
1: subs r1, r1, #1
bne 1b

ldr r1, =CLK_DIV_DMC0_VAL
ldr r2, =CLK_DIV_DMC0_OFFSET
str r1, [r0, r2]
ldr r1, =CLK_DIV_DMC1_VAL
ldr r2, =CLK_DIV_DMC1_OFFSET
str r1, [r0, r2]

@ CMU_TOP MUX / DIV
ldr r1, =CLK_SRC_TOP0_VAL
ldr r2, =CLK_SRC_TOP0_OFFSET
str r1, [r0, r2]
ldr r1, =CLK_SRC_TOP1_VAL
ldr r2, =CLK_SRC_TOP1_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x10000
3: subs r1, r1, #1
bne 3b

ldr r1, =CLK_DIV_TOP_VAL
ldr r2, =CLK_DIV_TOP_OFFSET
str r1, [r0, r2]

@ CMU_LEFTBUS MUX / DIV
ldr r1, =CLK_SRC_LEFTBUS_VAL
ldr r2, =CLK_SRC_LEFTBUS_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x10000
4: subs r1, r1, #1
bne 4b

ldr r1, =CLK_DIV_LEFRBUS_VAL
ldr r2, =CLK_DIV_LEFTBUS_OFFSET
str r1, [r0, r2]

@ CMU_RIGHTBUS MUX / DIV
ldr r1, =CLK_SRC_RIGHTBUS_VAL
ldr r2, =CLK_SRC_RIGHTBUS_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x10000
5: subs r1, r1, #1
bne 5b

ldr r1, =CLK_DIV_RIGHTBUS_VAL
ldr r2, =CLK_DIV_RIGHTBUS_OFFSET
str r1, [r0, r2]

@ Set PLL locktime
ldr r1, =APLL_LOCK_VAL
ldr r2, =APLL_LOCK_OFFSET
str r1, [r0, r2]

ldr r1, =MPLL_LOCK_VAL
ldr r2, =MPLL_LOCK_OFFSET
str r1, [r0, r2]

ldr r1, =EPLL_LOCK_VAL
ldr r2, =EPLL_LOCK_OFFSET
str r1, [r0, r2]

ldr r1, =VPLL_LOCK_VAL
ldr r2, =VPLL_LOCK_OFFSET
str r1, [r0, r2]

ldr r1, =CLK_DIV_CPU0_VAL
ldr r2, =CLK_DIV_CPU0_OFFSET
str r1, [r0, r2]
ldr r1, =CLK_DIV_CPU1_VAL
ldr r2, =CLK_DIV_CPU1_OFFSET
str r1, [r0, r2]

@ Set APLL
ldr r1, =APLL_CON1_VAL
ldr r2, =APLL_CON1_OFFSET
str r1, [r0, r2]
ldr r1, =APLL_CON0_VAL
ldr r2, =APLL_CON0_OFFSET
str r1, [r0, r2]

/* check MPLL and if MPLL is not 400 Mhz skip MPLL resetting for C2C operation */
ldr r2, =MPLL_CON0_OFFSET
ldr r1, [r0, r2]
ldr r3, =0xA0640301
cmp r1, r3
bne skip_mpll

@ Set MPLL
ldr r1, =MPLL_CON1_VAL
ldr r2, =MPLL_CON1_OFFSET
str r1, [r0, r2]
ldr r1, =MPLL_CON0_VAL
ldr r2, =MPLL_CON0_OFFSET
str r1, [r0, r2]
skip_mpll:

@ Set EPLL
ldr r1, =EPLL_CON2_VAL
ldr r2, =EPLL_CON2_OFFSET
str r1, [r0, r2]
ldr r1, =EPLL_CON1_VAL
ldr r2, =EPLL_CON1_OFFSET
str r1, [r0, r2]
ldr r1, =EPLL_CON0_VAL
ldr r2, =EPLL_CON0_OFFSET
str r1, [r0, r2]

@ Set VPLL
ldr r1, =VPLL_CON2_VAL
ldr r2, =VPLL_CON2_OFFSET
str r1, [r0, r2]
ldr r1, =VPLL_CON1_VAL
ldr r2, =VPLL_CON1_OFFSET
str r1, [r0, r2]
ldr r1, =VPLL_CON0_VAL
ldr r2, =VPLL_CON0_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x40000
6: subs r1, r1, #1
bne 6b

ldr r1, =0x01000001
ldr r2, =CLK_SRC_CPU_OFFSET
str r1, [r0, r2]
ldr r1, =0x00011000
ldr r2, =CLK_SRC_DMC_OFFSET
str r1, [r0, r2]
ldr r1, =0x00000110
ldr r2, =CLK_SRC_TOP0_OFFSET
str r1, [r0, r2]
ldr r1, =0x01111000
ldr r2, =CLK_SRC_TOP1_OFFSET
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x10000
7: subs r1, r1, #1
bne 7b

/* check C2C_CTRL enable bit */
ldr r3, =S5PV310_POWER_BASE
ldr r4, =C2C_CTRL_OFFSET
ldr r1, [r3, r4]
and r1, r1, #1
cmp r1, #0
bne v310_2

@ ConControl
#ifdef MEM_DLLl_ON
ldr r0, =APB_DMC_0_BASE

ldr r1, =0x7F10100A
ldr r2, =DMC_PHYCONTROL0
str r1, [r0, r2]

ldr r1, =0xE0000084
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]

ldr r1, =0x7F10100B
ldr r2, =DMC_PHYCONTROL0
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x20000
8: subs r1, r1, #1
bne 8b

ldr r1, =0x0000008C
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]
ldr r1, =0x00000084
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x20000
9: subs r1, r1, #1
bne 9b

ldr r0, =APB_DMC_1_BASE

ldr r1, =0x7F10100A
ldr r2, =DMC_PHYCONTROL0
str r1, [r0, r2]

ldr r1, =0xE0000084
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]

ldr r1, =0x7F10100B
ldr r2, =DMC_PHYCONTROL0
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x20000
10: subs r1, r1, #1
bne 10b

ldr r1, =0x0000008C
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]
ldr r1, =0x00000084
ldr r2, =DMC_PHYCONTROL1
str r1, [r0, r2]

/* wait ?us */
mov r1, #0x20000
11: subs r1, r1, #1
bne 11b
#endif

ldr r0, =APB_DMC_0_BASE
ldr r1, =0x0FFF30FA
ldr r2, =DMC_CONCONTROL
str r1, [r0, r2]

ldr r0, =APB_DMC_1_BASE
ldr r1, =0x0FFF30FA
ldr r2, =DMC_CONCONTROL
str r1, [r0, r2]

ldr r0, =APB_DMC_0_BASE
ldr r1, =0x00202533
ldr r2, =DMC_MEMCONTROL
str r1, [r0, r2]

ldr r0, =APB_DMC_1_BASE
ldr r1, =0x00202533
ldr r2, =DMC_MEMCONTROL
str r1, [r0, r2]

v310_2:
pop {pc}

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