diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 08daf6fa86..7ebb9f456b 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -15,7 +15,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o obj-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4210.o clock_init_exynos4210.o -obj-$(CONFIG_EXYNOS4) += dmc_init_exynos4412.o +obj-$(CONFIG_EXYNOS4412)+= dmc_init_exynos4412.o clock_init_exynos4412.o obj-y += spl_boot.o tzpc.o obj-y += lowlevel_init.o endif diff --git a/arch/arm/mach-exynos/clock_init_exynos4412.c b/arch/arm/mach-exynos/clock_init_exynos4412.c new file mode 100644 index 0000000000..1f7365b41a --- /dev/null +++ b/arch/arm/mach-exynos/clock_init_exynos4412.c @@ -0,0 +1,150 @@ +/* + * Clock initialisation for Exynos4412 based boards + * + * Copyright (C) 2018 Simon Shields + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "common_setup.h" +#include "exynos4412_setup.h" + +/* + * TODO: change all clock sources, then change clock dividers. + */ +void system_clock_init(void) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + struct exynos4412_power *power = + (struct exynos4412_power *)samsung_get_base_power(); +#if 0 + struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() + DMC_OFFSET); +#endif + + /* Set up UART */ + + writel(0, &clk->src_cpu); + writel(CLK_SRC_TOP0_VAL, &clk->src_top0); + writel(CLK_SRC_TOP1_VAL, &clk->src_top1); + writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); + writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); + writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0); + + sdelay(0x10000); + + writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); + writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); + writel(CLK_DIV_TOP_VAL, &clk->div_top); + writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); + writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); + writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0); + + /* PLLs */ + writel(APLL_LOCK_VAL, &clk->apll_lock); + writel(MPLL_LOCK_VAL, &clk->mpll_lock); + writel(EPLL_LOCK_VAL, &clk->epll_lock); + writel(VPLL_LOCK_VAL, &clk->vpll_lock); + + writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); + writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); + + /* APLL: 800MHz */ + writel(APLL_CON1_VAL, &clk->apll_con1); + writel(APLL_CON0_VAL, &clk->apll_con0); + + /* The iROM sets MPLL at 400MHz. + * Skip increasing MPLL if it's not at 400MHz */ + if (readl(&clk->mpll_con0) == 0xa0640301) { + /* MPLL: 800MHz */ + writel(MPLL_CON1_VAL, &clk->mpll_con1); + writel(MPLL_CON0_VAL, &clk->mpll_con0); + } + + /* EPLL: 96MHz */ + /* (64) * (24000000) / (2 * (1 << 3)) */ + writel(EPLL_CON2_VAL, &clk->epll_con2); + writel(EPLL_CON1_VAL, &clk->epll_con1); + writel(EPLL_CON0_VAL, &clk->epll_con0); + + /* VPLL: 108MHz */ + /* (72) * (24000000) / (2 * (1 << 3)) */ + writel(VPLL_CON2_VAL, &clk->vpll_con2); + writel(VPLL_CON1_VAL, &clk->vpll_con1); + writel(VPLL_CON0_VAL, &clk->vpll_con0); + + /* Stabilise */ + sdelay(0x40000); + + /* Now that PLLs are set up, we can set the other clocks to use them... */ + writel((1 << 24) | (1 << 0), &clk->src_cpu); + writel((1 << 16) | (1 << 12), &clk->src_dmc); + writel((1 << 8) | (1 << 4), &clk->src_top0); + writel((1 << 24) | (1 << 20) | (1 << 16) | (1 << 12), &clk->src_top1); + + sdelay(0x10000); + + /* + * In the SDMMC booting case, we need to reconfigure MMC clock + * to make the iROM happy. + */ + u32 fsys2_div = readl(&clk->div_fsys2); + /* new MMC2 div is 16 */ + fsys2_div |= 0xf; + writel(fsys2_div, &clk->div_fsys2); + + /*check C2C_CTRL enable bit */ + if ((readl(&power->c2c_ctrl) & 1) != 0) + return; +#if 0 + writel(PHYCONTROL0_VAL, &dmc->phycontrol0); + writel(MEM_TERM_EN | PHY_READ_EN | CTRL_SHGATE | CTRL_REF(8) | CTRL_SHIFTC(4), &dmc->phycontrol1); + writel(PHYCONTROL0_VAL | CTRL_DLL_START, &dmc->phycontrol0); + sdelay(0x20000); + + writel(CTRL_REF(8) | CTRL_SHIFTC(4), &dmc->phycontrol1); + writel(CTRL_REF(8) | FP_RESYNC | CTRL_SHIFTC(4), &dmc->phycontrol1); + + sdelay(0x20000); + + writel(PHYCONTROL0_VAL, &dmc1->phycontrol0); + writel(MEM_TERM_EN | PHY_READ_EN | CTRL_SHGATE | CTRL_REF(8) | CTRL_SHIFTC(4), &dmc1->phycontrol1); + writel(PHYCONTROL0_VAL | CTRL_DLL_START, &dmc1->phycontrol0); + sdelay(0x20000); + + writel(CTRL_REF(8) | CTRL_SHIFTC(4), &dmc1->phycontrol1); + writel(CTRL_REF(8) | FP_RESYNC | CTRL_SHIFTC(4), &dmc1->phycontrol1); + + sdelay(0x20000); + + writel(DMC_CONCONTROL, &dmc->concontrol); + writel(DMC_CONCONTROL, &dmc1->concontrol); + + writel(DMC_MEMCONTROL, &dmc->memcontrol); + writel(DMC_MEMCONTROL, &dmc1->memcontrol); +#endif +} diff --git a/arch/arm/mach-exynos/dmc_init_exynos4412.c b/arch/arm/mach-exynos/dmc_init_exynos4412.c index 0b87ddf200..3224c5a7fb 100644 --- a/arch/arm/mach-exynos/dmc_init_exynos4412.c +++ b/arch/arm/mach-exynos/dmc_init_exynos4412.c @@ -9,103 +9,12 @@ #include "common_setup.h" #include "exynos4412_setup.h" -// TODO: 4412 and 4210 should be commonised using something like is_soc_4210 -void system_clock_init(void) -{ - struct exynos4x12_clock *clk = - (struct exynos4x12_clock *)samsung_get_base_clock(); - struct exynos4412_power *power = (struct exynos4412_power *)samsung_get_base_power(); - struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); - struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() + DMC_OFFSET); - - // disable WDT - writel(0, (unsigned int *)0x10060000); - - writel(0, &clk->src_cpu); - - sdelay(0x10000); - - writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0); - writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1); - - writel(CLK_SRC_TOP0_VAL, &clk->src_top0); - writel(CLK_SRC_TOP1_VAL, &clk->src_top1); - sdelay(0x10000); - writel(CLK_DIV_TOP_VAL, &clk->div_top); - - writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus); - sdelay(0x10000); - writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); - - writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus); - sdelay(0x10000); - writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus); - - // setup PLLs - writel(0x3e8, &clk->apll_lock); - writel(0x2f1, &clk->mpll_lock); - writel(0x2321, &clk->epll_lock); - writel(0x2321, &clk->vpll_lock); - - writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0); - writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1); - - writel(APLL_CON1_VAL, &clk->apll_con1); - writel(APLL_CON0_VAL, &clk->apll_con0); - - /* don't reset MPLL in C2C case */ - if (readl(&clk->mpll_con1) == 0xa0640301) { - writel(MPLL_CON1_VAL, &clk->mpll_con1); - writel(MPLL_CON0_VAL, &clk->mpll_con0); - } - - writel(EPLL_CON2_VAL, &clk->epll_con2); - writel(EPLL_CON1_VAL, &clk->epll_con1); - writel(EPLL_CON0_VAL, &clk->epll_con0); - - writel(VPLL_CON2_VAL, &clk->vpll_con2); - writel(VPLL_CON1_VAL, &clk->vpll_con1); - writel(VPLL_CON0_VAL, &clk->vpll_con0); - - sdelay(0x10000); - - /* wtf */ - writel(0x01000001, &clk->src_cpu); - writel(0x00011000, &clk->src_dmc); - writel(0x00000110, &clk->src_top0); - writel(0x01111000, &clk->src_top1); - - sdelay(0x10000); - - if ((readl(&power->c2c_ctrl) & 1) != 0) { - return; - } - - /* todo: split this out, clean it up. Or drop it entirely? */ - // DRAM clocks - writel(0x7f10100a, &dmc->phycontrol0); - writel(0xe0000084, &dmc->phycontrol1); - writel(0x7f10100b, &dmc->phycontrol0); - - sdelay(0x20000); - - writel(0x0000008c, &dmc->phycontrol1); // force DLL resync - writel(0x00000084, &dmc->phycontrol1); - - sdelay(0x20000); - - writel(0x0fff30fa, &dmc->concontrol); - writel(0x0fff30fa, &dmc1->concontrol); - - writel(0x00202533, &dmc->memcontrol); - writel(0x00202533, &dmc1->memcontrol); -} - void mem_ctrl_init(int reset) { struct exynos4x12_clock *clk = (struct exynos4x12_clock *)samsung_get_base_clock(); struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); + struct exynos4_dmc *dmc1 = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() + DMC_OFFSET); writel(0x00117713, &clk->div_dmc0); @@ -151,49 +60,74 @@ void mem_ctrl_init(int reset) writel(0x810, &dmc->directcmd); writel(0xc08, &dmc->directcmd); - dmc = (struct exynos4_dmc *)(samsung_get_base_dmc_ctrl() + DMC_OFFSET); + writel(0xe3855403, &dmc1->phyzqcontrol); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x7110100a, &dmc1->phycontrol0); - writel(0xe3855403, &dmc->phyzqcontrol); - writel(0x71101008, &dmc->phycontrol0); - writel(0x7110100a, &dmc->phycontrol0); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x71101008, &dmc1->phycontrol0); + writel(0x0000008c, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); + writel(0x0000008c, &dmc1->phycontrol1); + writel(0x00000084, &dmc1->phycontrol1); - writel(0x00000084, &dmc->phycontrol1); - writel(0x71101008, &dmc->phycontrol0); - writel(0x0000008c, &dmc->phycontrol1); - writel(0x00000084, &dmc->phycontrol1); - writel(0x0000008c, &dmc->phycontrol1); - writel(0x00000084, &dmc->phycontrol1); - - writel(0x0fff30ca, &dmc->concontrol); - writel(0x00202500, &dmc->memcontrol); - writel(0x40c01323, &dmc->memconfig0); - writel(0x80000000 | 0x7, &dmc->ivcontrol); - writel(0x64000000, &dmc->prechconfig); - writel(0x9c4000ff, &dmc->phycontrol0); + writel(0x0fff30ca, &dmc1->concontrol); + writel(0x00202500, &dmc1->memcontrol); + writel(0x40c01323, &dmc1->memconfig0); + writel(0x80000000 | 0x7, &dmc1->ivcontrol); + writel(0x64000000, &dmc1->prechconfig); + writel(0x9c4000ff, &dmc1->phycontrol0); - writel(0x5d, &dmc->timingref); + writel(0x5d, &dmc1->timingref); - writel(0x34498691, &dmc->timingrow); - writel(0x36330306, &dmc->timingdata); - writel(0x50380365, &dmc->timingpower); + writel(0x34498691, &dmc1->timingrow); + writel(0x36330306, &dmc1->timingdata); + writel(0x50380365, &dmc1->timingpower); sdelay(0x100000); - writel(0x07000000, &dmc->directcmd); + writel(0x07000000, &dmc1->directcmd); sdelay(0x100000); - writel(0x00071c00, &dmc->directcmd); + writel(0x00071c00, &dmc1->directcmd); sdelay(0x100000); - writel(0x00010bfc, &dmc->directcmd); + writel(0x00010bfc, &dmc1->directcmd); sdelay(0x100000); - writel(0x608, &dmc->directcmd); - writel(0x810, &dmc->directcmd); - writel(0xc08, &dmc->directcmd); + writel(0x608, &dmc1->directcmd); + writel(0x810, &dmc1->directcmd); + writel(0xc08, &dmc1->directcmd); + + writel(PHYCONTROL0_VAL, &dmc->phycontrol0); + writel(MEM_TERM_EN | PHY_READ_EN | CTRL_SHGATE | CTRL_REF(8) | CTRL_SHIFTC(4), &dmc->phycontrol1); + writel(PHYCONTROL0_VAL | CTRL_DLL_START, &dmc->phycontrol0); + sdelay(0x20000); + + writel(CTRL_REF(8) | CTRL_SHIFTC(4), &dmc->phycontrol1); + writel(CTRL_REF(8) | FP_RESYNC | CTRL_SHIFTC(4), &dmc->phycontrol1); + + sdelay(0x20000); + + writel(PHYCONTROL0_VAL, &dmc1->phycontrol0); + writel(MEM_TERM_EN | PHY_READ_EN | CTRL_SHGATE | CTRL_REF(8) | CTRL_SHIFTC(4), &dmc1->phycontrol1); + writel(PHYCONTROL0_VAL | CTRL_DLL_START, &dmc1->phycontrol0); + sdelay(0x20000); + + writel(CTRL_REF(8) | CTRL_SHIFTC(4), &dmc1->phycontrol1); + writel(CTRL_REF(8) | FP_RESYNC | CTRL_SHIFTC(4), &dmc1->phycontrol1); + + sdelay(0x20000); + + writel(DMC_CONCONTROL, &dmc->concontrol); + writel(DMC_CONCONTROL, &dmc1->concontrol); + + writel(DMC_MEMCONTROL, &dmc->memcontrol); + writel(DMC_MEMCONTROL, &dmc1->memcontrol); + } diff --git a/arch/arm/mach-exynos/exynos4412_setup.h b/arch/arm/mach-exynos/exynos4412_setup.h index 6eb4290240..cff30fb691 100644 --- a/arch/arm/mach-exynos/exynos4412_setup.h +++ b/arch/arm/mach-exynos/exynos4412_setup.h @@ -1,161 +1,483 @@ -/* DMC */ -#define CORE_TIMERS_RATIO 0x0 -#define COPY2_RATIO 0x0 -#define DMCP_RATIO 0x1 -#define DMCD_RATIO 0x1 -#define DMC_RATIO 0x3 -#define DPHY_RATIO 0x1 -#define ACP_PCLK_RATIO 0x1 -#define ACP_RATIO 0x3 +/* + * (C) Copyright 2011 Samsung Electronics Co. Ltd + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef _VAL_SMDKC220_H +#define _VAL_SMDKC220_H + +#include +#include + +#include + +/* ARM_CLOCK_800Mhz */ +#if 1//defined(CONFIG_CLK_ARM_800_APLL_800 +#define APLL_MDIV 0x64 +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x1 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define PERIPH_RATIO 0x7 +#define COREM1_RATIO 0x5 +#define COREM0_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x3 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x3 + +/* ARM_CLOCK_1Ghz */ +#elif defined(CONFIG_CLK_ARM_1000_APLL_1000) +#define APLL_MDIV 0x7D +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x1 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x2 +#define COREM1_RATIO 0x5 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x4 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x3 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x4 + +/* ARM_CLOCK_1.2Ghz */ +#elif defined(CONFIG_CLK_ARM_1200_APLL_1100) +#define APLL_MDIV 0x113 +#define APLL_PDIV 0x6 +#define APLL_SDIV 0x0 + +#define APLL_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x3 +#define COREM1_RATIO 0x6 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x4 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x4 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x4 + +/* ARM_CLOCK_1.2Ghz */ +#elif defined(CONFIG_CLK_ARM_1200_APLL_1200) +#define APLL_MDIV 0x96 +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#define APLL_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x5 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x4 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x5 + +/* ARM_CLOCK_1.2Ghz */ +#elif defined(CONFIG_CLK_ARM_1200_APLL_1300) +#define APLL_MDIV 0x145 +#define APLL_PDIV 0x6 +#define APLL_SDIV 0x0 + +#define APLL_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x5 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x5 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x5 + +/* ARM_CLOCK_1.2Ghz */ +#elif defined(CONFIG_CLK_ARM_1200_APLL_1400) +#define APLL_MDIV 0xAF +#define APLL_PDIV 0x3 +#define APLL_SDIV 0x0 + +#define APLL_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x6 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x5 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x6 + +/* ARM_CLOCK_1.5Ghz */ +#elif defined(CONFIG_CLK_ARM_1500_APLL_1500) +#define APLL_MDIV 0xFA +#define APLL_PDIV 0x4 +#define APLL_SDIV 0x0 + +#define APLL_RATIO 0x2 +#define CORE_RATIO 0x0 +#define CORE2_RATIO 0x0 +#define COREM0_RATIO 0x4 +#define COREM1_RATIO 0x7 +#define PERIPH_RATIO 0x7 +#define ATB_RATIO 0x6 +#define PCLK_DBG_RATIO 0x1 + +/* CLK_DIV_CPU1 */ +#define CORES_RATIO 0x5 +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x6 + +#endif + +#define CLK_DIV_CPU0_VAL ((CORE2_RATIO << 28) \ + | (APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20)\ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO <<12) \ + | (COREM1_RATIO << 8) \ + | (COREM0_RATIO << 4) \ + | (CORE_RATIO)) + +#define CLK_DIV_CPU1_VAL ((CORES_RATIO << 8) \ + | (HPM_RATIO << 4) \ + | (COPY_RATIO)) + +#if 0 //defined(CONFIG_CLK_BUS_DMC_165_330) +#define MPLL_MDIV 0x116 +#define MPLL_PDIV 0x5 +#define MPLL_SDIV 0x1 +#else //defined(CONFIG_CLK_BUS_DMC_200_400) +#define MPLL_MDIV 0x64 +#define MPLL_PDIV 0x3 +#define MPLL_SDIV 0x0 +#endif +#if 0 //defined(CONFIG_CLK_BUS_DMC_100_200) +#define MPLL_MDIV 0x64 +#define MPLL_PDIV 0x3 +#define MPLL_SDIV 0x0 +#endif + +/* APLL_CON1 */ +#define APLL_CON1_VAL (0x00803800) + +/* MPLL_CON1 */ +#define MPLL_CON1_VAL (0x00803800) + +#define EPLL_MDIV 0x40 +#define EPLL_PDIV 0x2 +#define EPLL_SDIV 0x3 + +#define EPLL_CON1_VAL 0x66010000 +#define EPLL_CON2_VAL 0x00000080 + +#define VPLL_MDIV 0x48 +#define VPLL_PDIV 0x2 +#define VPLL_SDIV 0x3 + +#define VPLL_CON1_VAL 0x66010000 +#define VPLL_CON2_VAL 0x00000080 + +/* Set PLL */ +#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) + +#define APLL_CON0_VAL set_pll(APLL_MDIV,APLL_PDIV,APLL_SDIV) +#define MPLL_CON0_VAL set_pll(MPLL_MDIV,MPLL_PDIV,MPLL_SDIV) +#define EPLL_CON0_VAL set_pll(EPLL_MDIV,EPLL_PDIV,EPLL_SDIV) +#define VPLL_CON0_VAL set_pll(VPLL_MDIV,VPLL_PDIV,VPLL_SDIV) + + +/* CLK_SRC_CPU */ +/* 0 = MOUTAPLL, 1 = SCLKMPLL */ +#define MUX_HPM_SEL_MOUTAPLL 0 +#define MUX_HPM_SEL_SCLKMPLL 1 +#define MUX_CORE_SEL_MOUTAPLL 0 +#define MUX_CORE_SEL_SCLKMPLL 1 + +/* 0 = FILPLL, 1 = MOUT */ +#define MUX_MPLL_SEL_FILPLL 0 +#define MUX_MPLL_SEL_MOUTMPLLFOUT 1 + +#define MUX_APLL_SEL_FILPLL 0 +#define MUX_APLL_SEL_MOUTMPLLFOUT 1 + +#define CLK_SRC_CPU_VAL_FINPLL ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL <<16) \ + | (MUX_MPLL_SEL_FILPLL << 8) \ + | (MUX_APLL_SEL_FILPLL <<0)) + +#define CLK_SRC_CPU_VAL_MOUTMPLLFOUT ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL <<16) \ + | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8) \ + | (MUX_APLL_SEL_MOUTMPLLFOUT <<0)) + + + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL 0x0 +#define MUX_CORE_TIMERS_SEL 0x0 +#define MUX_DPHY_SEL 0x0 +#define MUX_DMC_BUS_SEL 0x0 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL << 16) \ + | (MUX_CORE_TIMERS_SEL << 12) \ + | (MUX_DPHY_SEL << 8) \ + | (MUX_DMC_BUS_SEL << 4)) + + + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x0 +#define COPY2_RATIO 0x0 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#if 0 //defined(CONFIG_CLK_BUS_DMC_100_200) +#define DMC_RATIO 0x3 +#else +#define DMC_RATIO 0x1 +#endif +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 #define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ | (COPY2_RATIO << 24) \ - | (DMCP_RATIO << 20) \ - | (DMC_RATIO << 12) \ - | (DPHY_RATIO << 8) \ - | (ACP_PCLK_RATIO << 4) \ + | (DMCP_RATIO << 20) \ + | (DMCD_RATIO << 16) \ + | (DMC_RATIO << 12) \ + | (DPHY_RATIO << 8) \ + | (ACP_PCLK_RATIO << 4) \ | (ACP_RATIO)) -#define DPM_RATIO (0x7) -#define DVSEM_RATIO (0x7) -#define C2C_ACLK_RATIO (0x1) -#define PWI_RATIO (0x7) -#define C2C_RATIO (0x1) -#define G2D_ACP_RATIO (0x3) +/* CLK_DIV_DMC1 */ +#define DPM_RATIO 0x7 +#define DVSEM_RATIO 0x7 +#define C2C_ACLK_RATIO 0x1 +#define PWI_RATIO 0x7 +#define C2C_RATIO 0x1 +#define G2D_ACP_RATIO 0x3 #define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ | (DVSEM_RATIO << 16) \ | (C2C_ACLK_RATIO << 12) \ | (PWI_RATIO << 8) \ | (C2C_RATIO << 4) \ - | G2D_ACP_RATIO) - -/* TOP */ -#define MUX_ONENAND_SEL_ACLK133 0x0 -#define MUX_ACLK_133_SEL_MPLL 0x0 -#define MUX_ACLK_160_SEL_MPLL 0x0 -#define MUX_ACLK_100_SEL_MPLL 0x0 -#define MUX_ACLK_200_SEL_MPLL 0x0 -#define MUX_VPLL_SEL_FOUTVPLL 0x1 -#define MUX_EPLL_SEL_FOUTEPLL 0x1 - -#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK133 << 28) \ - | (MUX_ACLK_133_SEL_MPLL << 24) \ - | (MUX_ACLK_160_SEL_MPLL << 20) \ - | (MUX_ACLK_100_SEL_MPLL << 16) \ - | (MUX_ACLK_200_SEL_MPLL << 12) \ - | (MUX_VPLL_SEL_FOUTVPLL << 8) \ - | (MUX_EPLL_SEL_FOUTEPLL << 4)) - -#define MUX_MCUISP_ACLK400_SEL 0x1 -#define MUX_ACLK200_SEL 0x1 -#define MUX_ACLK266_GPS_SEL 0x1 -#define MUX_MPLL_USER_SEL 0x1 - -#define CLK_SRC_TOP1_VAL ((MUX_MCUISP_ACLK400_SEL << 24) \ - | (MUX_ACLK200_SEL << 20) \ - | (MUX_ACLK266_GPS_SEL << 16) \ - | (MUX_MPLL_USER_SEL << 12)) - -#define ACLK400_MCUISP_RATIO 0x1 -#define ACLK266_GPS_RATIO 0x2 -#define ONENAND_RATIO 0x1 -#define ACLK133_RATIO 0x5 -#define ACLK160_RATIO 0x4 -#define ACLK100_RATIO 0x7 -#define ACLK200_RATIO 0x4 - -#define CLK_DIV_TOP_VAL ((ACLK400_MCUISP_RATIO << 24) \ - | (ACLK266_GPS_RATIO << 20) \ - | (ONENAND_RATIO << 16) \ - | (ACLK133_RATIO << 12) \ - | (ACLK160_RATIO << 8) \ - | (ACLK100_RATIO << 4) \ - | (ACLK200_RATIO)) - -/* LEFTBUS */ -#define MUX_MPLL_USER_SEL_L 0x1 - -#define CLK_SRC_LEFTBUS_VAL (MUX_MPLL_USER_SEL_L << 4) - -#define GPL_RATIO 0x1 -#define GDL_RATIO 0x3 - -#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | GDL_RATIO) - -/* RIGHTBUS */ -#define MUX_MPLL_USER_SEL_R 0x1 -#define CLK_SRC_RIGHTBUS_VAL (MUX_MPLL_USER_SEL_R << 4) - -#define GPR_RATIO 0x1 -#define GDR_RATIO 0x3 - -#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | GDR_RATIO) - -/* CPU */ -// TODO: these values are for 800MHz ARMCLK, 800MHz APLL. - -#define CORE2_RATIO 0x0 -#define APLL_RATIO 0x1 -#define PCLK_DBG_RATIO 0x1 -#define ATB_RATIO 0x3 -#define PERIPH_RATIO 0x7 -#define COREM1_RATIO 0x5 -#define COREM0_RATIO 0x2 -#define CORE_RATIO 0x0 - -#define CLK_DIV_CPU0_VAL ((CORE2_RATIO << 28) \ - | (APLL_RATIO << 24) \ - | (PCLK_DBG_RATIO << 20) \ - | (ATB_RATIO << 16) \ - | (PERIPH_RATIO << 12) \ - | (COREM1_RATIO << 8) \ - | (COREM0_RATIO << 4) \ - | (CORE_RATIO)) -#define CORES_RATIO 0x3 -#define HPM_RATIO 0x0 -#define COPY_RATIO 0x3 + | (G2D_ACP_RATIO)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL 0x0 /* 0 = DOUT133, 1 = DOUT166 */ +#define MUX_ACLK_133_SEL 0x0 /* 0 = SCLKMPLL, 1 = SCLKAPLL */ +#define MUX_ACLK_160_SEL 0x0 /* MPLL */ +#define MUX_ACLK_100_SEL 0x0 /* MPLL */ +#define MUX_ACLK_200_SEL 0x0 /* MPLL */ +#define MUX_VPLL_SEL 0x1 /* FOUTVPLL */ +#define MUX_EPLL_SEL 0x1 /* FOUTEPLL */ +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL << 28) \ + | (MUX_ACLK_133_SEL << 24) \ + | (MUX_ACLK_160_SEL << 20) \ + | (MUX_ACLK_100_SEL << 16) \ + | (MUX_ACLK_200_SEL << 12) \ + | (MUX_VPLL_SEL << 8) \ + | (MUX_EPLL_SEL << 4)) + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL 0x0 /* 0 = FINPLL, 1 = SCLKHDMI27M */ +#define MUX_ACLK_400_MCUISP_SUB_SEL 0x1 /*DIVOUT_ACLK_400_MCUISP */ +#define MUX_ACLK_200_SUB_SEL 0x1 /*DIVOUT_ACLK_200*/ +#define MUX_ACLK_266_GPS_SUB_SEL 0x1 /*DIVOUT_ACLK_266_GPS*/ +#define MUX_MPLL_USER_T_SEL 0x1 /* SCLKMPLL */ + +#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_MCUISP_SUB_SEL << 24) \ + | (MUX_ACLK_200_SUB_SEL << 20) \ + | (MUX_ACLK_266_GPS_SUB_SEL << 16) \ + | (MUX_MPLL_USER_T_SEL << 12)) + +/* CLK_DIV_TOP */ +#define ACLK_400_MCUISP_RATIO 0x1 +#define ACLK_266_GPS_RATIO 0x2 +#define ONENAND_RATIO 0x1 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x4 + +#define CLK_DIV_TOP_VAL ((ACLK_400_MCUISP_RATIO << 24) \ + | (ACLK_266_GPS_RATIO << 20) \ + | (ONENAND_RATIO << 16) \ + | (ACLK_133_RATIO << 12) \ + | (ACLK_160_RATIO << 8) \ + | (ACLK_100_RATIO << 4) \ + | (ACLK_200_RATIO)) + + +/* CLK_SRC_LEFTBUS */ +#define CLK_SRC_LEFTBUS_VAL (0x10) /* MPLL, GDL from MPLL */ + + +/* CLK_DIV_LEFTBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) \ + | (GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define CLK_SRC_RIGHTBUS_VAL (0x10) + + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) \ + | (GDR_RATIO)) + +/* APLL_LOCK */ +#define APLL_LOCK_VAL (0x3E8) +/* MPLL_LOCK */ +#define MPLL_LOCK_VAL (0x2F1) +/* EPLL_LOCK */ +#define EPLL_LOCK_VAL (0x2321) +/* VPLL_LOCK */ +#define VPLL_LOCK_VAL (0x2321) + + +/* CLK_SRC_PERIL0 */ +#define PWM_SEL 0 +#define UART5_SEL 6 +#define UART4_SEL 6 +#define UART3_SEL 6 +#define UART2_SEL 6 +#define UART1_SEL 6 +#define UART0_SEL 6 +#define CLK_SRC_PERIL0_VAL ((PWM_SEL << 24)\ + | (UART5_SEL << 20) \ + | (UART4_SEL << 16) \ + | (UART3_SEL << 12) \ + | (UART2_SEL<< 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL)) + +/* CLK_DIV_PERIL0 */ +#if 0 //defined(CONFIG_CLK_BUS_DMC_165_330) +#define UART5_RATIO 7 +#define UART4_RATIO 7 +#define UART3_RATIO 7 +#define UART2_RATIO 7 +#define UART1_RATIO 7 +#define UART0_RATIO 7 +#else // defined(CONFIG_CLK_BUS_DMC_200_400) +#define UART5_RATIO 8 +#define UART4_RATIO 8 +#define UART3_RATIO 8 +#define UART2_RATIO 8 +#define UART1_RATIO 8 +#define UART0_RATIO 8 +#endif + +#define CLK_DIV_PERIL0_VAL ((UART5_RATIO << 20) \ + | (UART4_RATIO << 16) \ + | (UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO)) + + +#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1))) + + +#define SCLK_UART MPLL_DEC / (UART1_RATIO+1) + +#if 0 //defined(CONFIG_CLK_BUS_DMC_165_330) +#define UART_UBRDIV_VAL 0x2B/* (SCLK_UART/(115200*16) -1) */ +#define UART_UDIVSLOT_VAL 0xC /*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/ +#else // defined(CONFIG_CLK_BUS_DMC_200_400) +#define UART_UBRDIV_VAL 0x2F /* (SCLK_UART/(115200*16) -1) */ +#define UART_UDIVSLOT_VAL 0x3 /*((((SCLK_UART*10/(115200*16) -10))%10)*16/10)*/ +#endif + +/* DMC PHYCONTROL0 */ +#define CTRL_FORCE (0x7f << 24) +#define CTRL_INC (0x10 << 16) +#define CTRL_START_POINT (0x10 << 8) +#define DQS_DELAY (0x0 << 4) +#define CTRL_DFDQS (0x1 << 3) +#define CTRL_HALF (0x0 << 2) +#define CTRL_DLL_ON (0x1 << 1) +#define CTRL_DLL_START (0x1 << 0) + +/* CTRL_DLL_START will be ORd in when appropriate */ +#define PHYCONTROL0_VAL (CTRL_FORCE | CTRL_INC \ + | CTRL_START_POINT | DQS_DELAY \ + | CTRL_DFDQS | CTRL_HALF | CTRL_DLL_ON) + +/* DMC PHYCONTROL1 */ +#define MEM_TERM_EN (0x1 << 31) +#define PHY_READ_EN (0x1 << 30) +#define CTRL_SHGATE (0x1 << 29) +#define FP_RESYNC (0x1 << 3) +#define CTRL_REF(x) (x << 4) +#define CTRL_SHIFTC(x) (x << 0) + +#define DMC_PHYCONTROL1 (MEM_TERM_EN | PHY_READ_EN \ + | CTRL_SHGATE | CTRL_REF | CTRL_SHIFTC) + +/* DMC CONCONTROL */ +#define TIMEOUT_LEVEL0 (0xfff << 16) +#define RD_FETCH (0x3 << 12) +#define DRV_TYPE (0x3 << 6) +#define AREF_EN (0x1 << 5) +#define PDN_DQ_DISABLE (0x1 << 4) +#define IO_PDN_CON (0x1 << 3) +#define CLK_RATIO (0x1 << 1) + +#define DMC_CONCONTROL (TIMEOUT_LEVEL0 | RD_FETCH \ + | DRV_TYPE | AREF_EN \ + | PDN_DQ_DISABLE | IO_PDN_CON \ + | CLK_RATIO) + +/* DMC MEMCONTROL */ +#define BURSTLEN (0x2 << 20) +#define MEM_WIDTH (0x2 << 12) +#define MEM_TYPE (0x5 << 8) /* LPDDR2-S4 */ +#define DSREF_EN (0x1 << 5) +#define TP_EN (0x1 << 4) +#define DPWRDN_EN (0x1 << 1) +#define CLK_STOP_EN (0x1 << 0) + +#define DMC_MEMCONTROL (BURSTLEN | MEM_WIDTH \ + | MEM_TYPE | DSREF_EN \ + | TP_EN | DPWRDN_EN \ + | CLK_STOP_EN) + +#endif -#define CLK_DIV_CPU1_VAL ((CORES_RATIO << 8) \ - | (HPM_RATIO << 4) \ - | (COPY_RATIO)) - -/* APLL control */ -#define RESV0 0x1 -#define LOCK_CON_IN 0x3 -#define LOCK_CON_DLY 0x8 -#define APLL_CON1_VAL ((RESV0 << 23) \ - | (LOCK_CON_IN << 12) \ - | (LOCK_CON_DLY << 8)) - -#define MPLL_CON1_VAL APLL_CON1_VAL - -/* PLL dividers */ -#define APLL_M 0x64 -#define APLL_P 0x3 -#define APLL_S 0x0 - -// for 200MHZ BUSCLK, 400MHZ DMCCLK -#define MPLL_M 0x64 -#define MPLL_P 0x3 -#define MPLL_S 0x0 - -#define EPLL_M 0x40 -#define EPLL_P 0x2 -#define EPLL_S 0x3 - -#define VPLL_M 0x48 -#define VPLL_P 0x2 -#define VPLL_S 0x3 - -#define set_pll(m, p, s) (1 << 31 | m << 16 | p << 8 | s) - -#define APLL_CON0_VAL set_pll(APLL_M, APLL_P, APLL_S) -#define MPLL_CON0_VAL set_pll(MPLL_M, MPLL_P, MPLL_S) -#define EPLL_CON0_VAL set_pll(EPLL_M, EPLL_P, EPLL_S) -#define VPLL_CON0_VAL set_pll(VPLL_M, VPLL_P, VPLL_S) - -#define EPLL_CON1_VAL 0x66010000 -#define EPLL_CON2_VAL 0x00000080 -#define VPLL_CON1_VAL 0x66010000 -#define VPLL_CON2_VAL 0x00000080