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trying to figure out why u-boot isn't loaded

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fourkbomb committed Apr 25, 2018
1 parent 6b524c6 commit cb57ecbb38805e3b22b2de9255406b2d6cdf01f4
@@ -226,5 +226,6 @@ int do_lowlevel_init(void)
tzpc_init();
}

printascii("lowlevel_init done\n");
return actions & DO_WAKEUP;
}
@@ -225,6 +225,7 @@ void copy_uboot_to_ram(void)
#ifdef CONFIG_SUPPORT_EMMC_BOOT
case BOOT_MODE_EMMC:
case BOOT_MODE_EMMC_SD:
printascii("trying EMMC\n");
/* Set the FSYS1 clock divisor value for EMMC boot */
emmc_boot_clk_div_set();

@@ -241,8 +242,19 @@ void copy_uboot_to_ram(void)
case BOOT_MODE_EMMC_SD:
#endif
case BOOT_MODE_SD:
printascii("booting from SD\n");
printascii("first two bytes now:\n");
printhex2(((char *)CONFIG_SYS_TEXT_BASE)[0]);
printascii(" ");
printhex2(((char *)CONFIG_SYS_TEXT_BASE)[1]);
printascii("\n");
offset = BL2_START_OFFSET;
size = BL2_SIZE_BLOC_COUNT;
printascii("offset/size:");
printhex4(offset);
printascii("/");
printhex4(size);
printascii("\n");
copy_bl2 = get_irom_func(MMC_INDEX);
break;
#ifdef CONFIG_USB_BOOTING
@@ -258,11 +270,22 @@ void copy_uboot_to_ram(void)
break;
#endif
default:
printascii("bad boot mode!\n");
break;
}

printascii("copy_bl2:");
printhex8(copy_bl2);
printascii(" copy to:");
printhex8(CONFIG_SYS_TEXT_BASE);
printascii("\n");
if (copy_bl2)
copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
else
printascii("not copying anything\n");

char *b = (char *)CONFIG_SYS_TEXT_BASE;
b[0] = 0xdd;
}

void memzero(void *s, size_t n)
@@ -300,8 +323,20 @@ void board_init_f(unsigned long bootflag)
if (do_lowlevel_init())
power_exit_wakeup();

printascii("copy uboot to ram\n");
copy_uboot_to_ram();

char *byte = (char *)CONFIG_SYS_TEXT_BASE;
printascii("here's some bytes: ");
for (int i = 0; i < 8192; i++) {
printhex2(byte[i]);
printascii(" ");
if ((i+1) % 0x20 == 0)
printascii("\n");
}
printascii("\n");

printascii("booting u-boot!\n");
/* Jump to U-Boot image */
uboot = (void *)CONFIG_SYS_TEXT_BASE;
(*uboot)();
@@ -33,6 +33,7 @@
#define CLK_SRC_TOP0_OFFSET 0x0C210
#define CLK_SRC_TOP1_OFFSET 0x0C214
#define CLK_SRC_FSYS_OFFSET 0x0C240
#define CLK_DIV_FSYS2_OFFSET 0x0C548
#define CLK_SRC_PERIL0_OFFSET 0x0C250
#define CLK_DIV_TOP_OFFSET 0x0C510
#define CLK_DIV_FSYS1_OFFSET 0x0C544
@@ -328,6 +329,12 @@ skip_mpll:
ldr r2, =DMC_MEMCONTROL
str r1, [r0, r2]

ldr r0, =ELFIN_CLOCK_BASE
ldr r2, =CLK_DIV_FSYS2_OFFSET
ldr r1, [r0, r2]
orr r1, r1, #0xf
str r1, [r0, r2] @ MMC2_RATIO

v310_2:
pop {pc}

@@ -50,6 +50,10 @@ lowlevel_init:

bl uart_asm_init

#ifndef CONFIG_SPL_BUILD
b not_spl
#endif

bl mem_asm_init

bl system_clock_init_asm
@@ -80,12 +84,32 @@ uart_bl2_put:
9: subs r0, r0, #1
bne 9b

b uart_bl2_put
pop {pc}

not_spl:
mov r0, #'X'
bl uart_putc
mov r0, #'L'
bl uart_putc
mov r0, #'3'
bl uart_putc
mov r0, #' '
bl uart_putc
mov r0, #'!'
bl uart_putc
mov r0, #' '
bl uart_putc
mov r0, #'B'
bl uart_putc
mov r0, #'3'
bl uart_putc

pop {pc}

uart_putc:


.globl uart_putc
uart_putc: @ ARM calling convention: must preserve r4-r11
mov r2, r0
ldr r0, =UART2_BASE
1:

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