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ARM: exynos: add exynos4412 TZASC init
we initialise the address space controller to allow access by both secure and non-secure worlds to the whole RAM.
1 parent df5a5ec commit e15666d

3 files changed

Lines changed: 37 additions & 1 deletion

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arch/arm/mach-exynos/dmc_init_exynos4412.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,21 @@
99
#include "common_setup.h"
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#include "exynos4412_setup.h"
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#define NR_TZASC_BANKS 4
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/* Allow non-secure and secure access to all memory */
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#define RA0_VAL 0xf0000000
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static void tzasc_init(void) {
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unsigned int start = samsung_get_base_dmc_tzasc();
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unsigned int end = start + (DMC_OFFSET * (NR_TZASC_BANKS - 1));
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for (; start <= end; start += DMC_OFFSET) {
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struct exynos4412_tzasc *asc = (struct exynos4412_tzasc *)start;
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writel(RA0_VAL, &asc->region_attributes_0);
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}
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}
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void mem_ctrl_init(int reset)
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{
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struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
@@ -124,6 +139,8 @@ void mem_ctrl_init(int reset)
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writel(DMC_MEMCONTROL, &dmc->memcontrol);
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writel(DMC_MEMCONTROL, &dmc1->memcontrol);
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tzasc_init();
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}
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arch/arm/mach-exynos/include/mach/cpu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@
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#define EXYNOS4X12_TZPC_BASE 0x10110000
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#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
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#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
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#define EXYNOS4X12_DMC_TZASC_BASE 0x10700000
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#define EXYNOS4X12_ACE_SFR_BASE 0x10830000
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#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
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#define EXYNOS4X12_GPIO_PART2_0 0x11000000
@@ -101,7 +102,6 @@
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#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
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#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE
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/* EXYNOS5 */
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#define EXYNOS5_I2C_SPACING 0x10000

arch/arm/mach-exynos/include/mach/dmc.h

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -419,6 +419,25 @@ struct exynos5420_phy_control {
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unsigned int phy_con42;
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};
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struct exynos4412_tzasc {
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unsigned char res1[0x100];
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unsigned int region_setup_low_0; // 100
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unsigned int region_setup_high_0; // 104
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unsigned int region_attributes_0; // 108
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unsigned int res2; // 10c
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unsigned int region_setup_low_1; // 110
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unsigned int region_setup_high_1; // 114
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unsigned int region_setup_attributes_1; // 118
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unsigned int res3;
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unsigned int region_setup_low_2; // 120
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unsigned int region_setup_high_2; // 124
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unsigned int region_setup_attributes_2; // 128
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unsigned int res4;
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unsigned int region_setup_low_3; // 130
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unsigned int region_setup_high_3; // 134
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unsigned int region_attributes_3; // 138
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};
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struct exynos5420_tzasc {
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unsigned char res1[0xf00];
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unsigned int membaseconfig0;

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