Skip to content

Commit

Permalink
ARM: exynos: add exynos4412 TZASC init
Browse files Browse the repository at this point in the history
we initialise the address space controller to allow
access by both secure and non-secure worlds to the whole
RAM.
  • Loading branch information
fourkbomb committed Jun 18, 2018
1 parent df5a5ec commit e15666d
Show file tree
Hide file tree
Showing 3 changed files with 37 additions and 1 deletion.
17 changes: 17 additions & 0 deletions arch/arm/mach-exynos/dmc_init_exynos4412.c
Expand Up @@ -9,6 +9,21 @@
#include "common_setup.h" #include "common_setup.h"
#include "exynos4412_setup.h" #include "exynos4412_setup.h"


#define NR_TZASC_BANKS 4

/* Allow non-secure and secure access to all memory */
#define RA0_VAL 0xf0000000

static void tzasc_init(void) {
unsigned int start = samsung_get_base_dmc_tzasc();
unsigned int end = start + (DMC_OFFSET * (NR_TZASC_BANKS - 1));

for (; start <= end; start += DMC_OFFSET) {
struct exynos4412_tzasc *asc = (struct exynos4412_tzasc *)start;
writel(RA0_VAL, &asc->region_attributes_0);
}
}

void mem_ctrl_init(int reset) void mem_ctrl_init(int reset)
{ {
struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl(); struct exynos4_dmc *dmc = (struct exynos4_dmc *)samsung_get_base_dmc_ctrl();
Expand Down Expand Up @@ -124,6 +139,8 @@ void mem_ctrl_init(int reset)
writel(DMC_MEMCONTROL, &dmc->memcontrol); writel(DMC_MEMCONTROL, &dmc->memcontrol);
writel(DMC_MEMCONTROL, &dmc1->memcontrol); writel(DMC_MEMCONTROL, &dmc1->memcontrol);


tzasc_init();

} }




2 changes: 1 addition & 1 deletion arch/arm/mach-exynos/include/mach/cpu.h
Expand Up @@ -70,6 +70,7 @@
#define EXYNOS4X12_TZPC_BASE 0x10110000 #define EXYNOS4X12_TZPC_BASE 0x10110000
#define EXYNOS4X12_DMC_CTRL_BASE 0x10600000 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
#define EXYNOS4X12_DMC_TZASC_BASE 0x10700000
#define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000
#define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
#define EXYNOS4X12_GPIO_PART2_0 0x11000000 #define EXYNOS4X12_GPIO_PART2_0 0x11000000
Expand Down Expand Up @@ -101,7 +102,6 @@
#define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS4X12_DMC_TZASC_BASE DEVICE_NOT_AVAILABLE


/* EXYNOS5 */ /* EXYNOS5 */
#define EXYNOS5_I2C_SPACING 0x10000 #define EXYNOS5_I2C_SPACING 0x10000
Expand Down
19 changes: 19 additions & 0 deletions arch/arm/mach-exynos/include/mach/dmc.h
Expand Up @@ -419,6 +419,25 @@ struct exynos5420_phy_control {
unsigned int phy_con42; unsigned int phy_con42;
}; };


struct exynos4412_tzasc {
unsigned char res1[0x100];
unsigned int region_setup_low_0; // 100
unsigned int region_setup_high_0; // 104
unsigned int region_attributes_0; // 108
unsigned int res2; // 10c
unsigned int region_setup_low_1; // 110
unsigned int region_setup_high_1; // 114
unsigned int region_setup_attributes_1; // 118
unsigned int res3;
unsigned int region_setup_low_2; // 120
unsigned int region_setup_high_2; // 124
unsigned int region_setup_attributes_2; // 128
unsigned int res4;
unsigned int region_setup_low_3; // 130
unsigned int region_setup_high_3; // 134
unsigned int region_attributes_3; // 138
};

struct exynos5420_tzasc { struct exynos5420_tzasc {
unsigned char res1[0xf00]; unsigned char res1[0xf00];
unsigned int membaseconfig0; unsigned int membaseconfig0;
Expand Down

0 comments on commit e15666d

Please sign in to comment.