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Branch: master
Commits on Oct 9, 2019
  1. The mounting holes must be present in the schematic to prevent them f…

    foxostro committed Oct 9, 2019
    …rom disappearing when I update.
  2. Add Gerber plots for PCBs.

    foxostro committed Oct 9, 2019
  3. Fix RAM card DRC errors

    foxostro committed Oct 9, 2019
Commits on Oct 8, 2019
Commits on Oct 7, 2019
  1. WIP: Move register D to the right hand side of the board.

    foxostro committed Oct 7, 2019
    * This puts the PI/PO lines near the expansion cards, which is good.
    * The board outline needed to expand to accomodate the new ICs.
    * Several control signals were re-routed due to the change.
    * There's a large empty spot where register D used to be. I cannot get rid
    of this without re-routing a large portion of the lower left hand corner.
  2. Prepare PCB for new parts

    foxostro committed Oct 7, 2019
Commits on Oct 4, 2019
  1. Instruction RAM uses Device Select lines 0 and 1 now.

    foxostro committed Oct 4, 2019
    This is a deviation from the breadboard prototype, but should be more
    elegant. Other devices with higher assigned numbers will be off board.
  2. Route the Register Clock.

    foxostro committed Oct 4, 2019
  3. Route the control clock.

    foxostro committed Oct 4, 2019
  4. Route RST signal.

    foxostro committed Oct 4, 2019
  5. There are a few control signals I want to route on the outer layers. …

    foxostro committed Oct 4, 2019
    …Also, outline the bus.
  6. Switch to six layer again and delete routed control signals.

    foxostro committed Oct 4, 2019
    I've been waffling on the issue of choosing four vs six layer PCB. I'm
    finding now that routing all the control signals is going to be a real
    pain. So, switch back to a six layer board and reserve In.Cu for clock and
    control signals.
    
    This layer is sandwiched between two gorund planes which should help
    isolate it from electrical noise.
  7. Route the Reset, Clock, and Speed Dial modules.

    foxostro committed Oct 4, 2019
    Control and clock signals have not yet been routed.
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