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set_property PACKAGE_PIN H23 [get_ports spi_rtl_sck_io]
# Enable internal termination resistor on LVDS 125MHz ref_clk
set_property DIFF_TERM_ADV TERM_100 [get_ports {ref_clk_p[0]}]
set_property DIFF_TERM_ADV TERM_100 [get_ports {ref_clk_n[0]}]
# Define I/O standards
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_0_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_fsel[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_1_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_0_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {ref_clk_oe[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_1_mdc]
#set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_rxc]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_rxc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_rx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_rx_ctl]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[2]}]
#set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_tx_ctl]
#set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_2_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[3]}]
set_property IOSTANDARD LVDS [get_ports {ref_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {ref_clk_n[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_rd[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_txc]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_0_td[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_0_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_1_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_1_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_1[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_rd[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[0]}]
#set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_2_txc]
#set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_2_td[3]}]
#set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_2_mdc]
#set_property IOSTANDARD LVCMOS18 [get_ports reset_port_2]
set_property IOSTANDARD LVCMOS18 [get_ports {rgmii_port_3_td[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_txc]
set_property IOSTANDARD LVCMOS18 [get_ports rgmii_port_3_tx_ctl]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_3_mdc]
set_property IOSTANDARD LVCMOS18 [get_ports mdio_io_port_3_mdio_io]
set_property IOSTANDARD LVCMOS18 [get_ports {reset_port_3[0]}]
set_property PACKAGE_PIN V29 [get_ports {rgmii_port_1_rd[0]}]
set_property PACKAGE_PIN W29 [get_ports mdio_io_port_0_mdio_io]
set_property PACKAGE_PIN T23 [get_ports {rgmii_port_1_rd[2]}]
set_property PACKAGE_PIN U21 [get_ports {ref_clk_fsel[0]}]
set_property PACKAGE_PIN U22 [get_ports mdio_io_port_1_mdio_io]
set_property PACKAGE_PIN AB30 [get_ports rgmii_port_3_rxc]
set_property PACKAGE_PIN AB31 [get_ports rgmii_port_3_rx_ctl]
set_property PACKAGE_PIN AG31 [get_ports {rgmii_port_3_rd[1]}]
set_property PACKAGE_PIN AG32 [get_ports {rgmii_port_3_rd[3]}]
set_property PACKAGE_PIN W25 [get_ports rgmii_port_1_rxc]
set_property PACKAGE_PIN Y25 [get_ports rgmii_port_1_rx_ctl]
set_property PACKAGE_PIN V27 [get_ports mdio_io_port_0_mdc]
set_property PACKAGE_PIN V28 [get_ports {reset_port_0[0]}]
set_property PACKAGE_PIN V26 [get_ports {rgmii_port_1_rd[1]}]
set_property PACKAGE_PIN W26 [get_ports {rgmii_port_1_rd[3]}]
set_property PACKAGE_PIN AA20 [get_ports {ref_clk_oe[0]}]
set_property PACKAGE_PIN AB20 [get_ports mdio_io_port_1_mdc]
#set_property PACKAGE_PIN AA32 [get_ports rgmii_port_2_rxc]
#set_property PACKAGE_PIN AD30 [get_ports {rgmii_port_2_rd[2]}]
#set_property PACKAGE_PIN AD31 [get_ports {rgmii_port_2_rd[3]}]
set_property PACKAGE_PIN AF33 [get_ports {rgmii_port_3_rd[0]}]
set_property PACKAGE_PIN AG34 [get_ports {rgmii_port_3_rd[2]}]
set_property PACKAGE_PIN W23 [get_ports rgmii_port_0_rxc]
set_property PACKAGE_PIN W24 [get_ports rgmii_port_0_rx_ctl]
set_property PACKAGE_PIN W28 [get_ports {rgmii_port_0_rd[2]}]
set_property PACKAGE_PIN Y28 [get_ports {rgmii_port_0_rd[3]}]
set_property PACKAGE_PIN U24 [get_ports {rgmii_port_0_td[1]}]
set_property PACKAGE_PIN U25 [get_ports {rgmii_port_0_td[2]}]
set_property PACKAGE_PIN AC23 [get_ports {rgmii_port_1_td[0]}]
set_property PACKAGE_PIN AB21 [get_ports {rgmii_port_1_td[2]}]
set_property PACKAGE_PIN AC21 [get_ports {rgmii_port_1_td[3]}]
#set_property PACKAGE_PIN AA34 [get_ports rgmii_port_2_rx_ctl]
#set_property PACKAGE_PIN AB34 [get_ports {rgmii_port_2_rd[0]}]
#set_property PACKAGE_PIN AC34 [get_ports {rgmii_port_2_td[1]}]
#set_property PACKAGE_PIN AD34 [get_ports {rgmii_port_2_td[2]}]
#set_property PACKAGE_PIN AE33 [get_ports rgmii_port_2_tx_ctl]
#set_property PACKAGE_PIN AF34 [get_ports mdio_io_port_2_mdio_io]
set_property PACKAGE_PIN V34 [get_ports {rgmii_port_3_td[0]}]
set_property PACKAGE_PIN V33 [get_ports {rgmii_port_3_td[2]}]
set_property PACKAGE_PIN W34 [get_ports {rgmii_port_3_td[3]}]
set_property PACKAGE_PIN AA24 [get_ports {ref_clk_p[0]}]
set_property PACKAGE_PIN AA25 [get_ports {ref_clk_n[0]}]
set_property PACKAGE_PIN AA22 [get_ports {rgmii_port_0_rd[0]}]
set_property PACKAGE_PIN AB22 [get_ports {rgmii_port_0_rd[1]}]
set_property PACKAGE_PIN U26 [get_ports {rgmii_port_0_td[0]}]
set_property PACKAGE_PIN U27 [get_ports rgmii_port_0_txc]
set_property PACKAGE_PIN V22 [get_ports {rgmii_port_0_td[3]}]
set_property PACKAGE_PIN V23 [get_ports rgmii_port_0_tx_ctl]
set_property PACKAGE_PIN V21 [get_ports {rgmii_port_1_td[1]}]
set_property PACKAGE_PIN W21 [get_ports rgmii_port_1_txc]
set_property PACKAGE_PIN AB25 [get_ports rgmii_port_1_tx_ctl]
set_property PACKAGE_PIN AB26 [get_ports {reset_port_1[0]}]
#set_property PACKAGE_PIN AA29 [get_ports {rgmii_port_2_rd[1]}]
#set_property PACKAGE_PIN AB29 [get_ports {rgmii_port_2_td[0]}]
#set_property PACKAGE_PIN AC33 [get_ports rgmii_port_2_txc]
#set_property PACKAGE_PIN AD33 [get_ports {rgmii_port_2_td[3]}]
#set_property PACKAGE_PIN AE32 [get_ports mdio_io_port_2_mdc]
#set_property PACKAGE_PIN AF32 [get_ports reset_port_2]
set_property PACKAGE_PIN V31 [get_ports {rgmii_port_3_td[1]}]
set_property PACKAGE_PIN W31 [get_ports rgmii_port_3_txc]
set_property PACKAGE_PIN Y31 [get_ports rgmii_port_3_tx_ctl]
set_property PACKAGE_PIN Y32 [get_ports mdio_io_port_3_mdc]
set_property PACKAGE_PIN W30 [get_ports mdio_io_port_3_mdio_io]
set_property PACKAGE_PIN Y30 [get_ports {reset_port_3[0]}]
#create_clock -period 8.000 -name ref_clk_p -waveform {0.000 4.000} [get_ports ref_clk_p]
#QSPI
set_property PACKAGE_PIN M20 [get_ports spi_rtl_io0_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io0_io]
set_property PACKAGE_PIN L20 [get_ports spi_rtl_io1_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io1_io]
set_property PACKAGE_PIN R22 [get_ports spi_rtl_io2_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io2_io]
set_property PACKAGE_PIN R21 [get_ports spi_rtl_io3_io]
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_io3_io]
set_property PACKAGE_PIN G26 [get_ports {spi_rtl_ss_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {spi_rtl_ss_io[0]}]
# SCK not used - loc it to unused pin: GPIO_LED_1_LS
set_property IOSTANDARD LVCMOS18 [get_ports spi_rtl_sck_io]
# In Vivado 2018.2, auto-placement of some of the BUFGCEs for RGMII RX CLK is not ideal and we don't achieve
# timing closure. The following constraints change the placement of these BUFGCEs to replicate the same
# placement used by the older Vivado 2017.3 tools in which the timing did close. The constraints were auto-generated in
# Vivado 2018.2 by modifying the implemented design.
current_instance kcu105_lpc_axieth_i/ddr4_0/inst
set_property LOC MMCME3_ADV_X0Y1 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]
current_instance -quiet
set_property INTERNAL_VREF 0.84 [get_iobanks 46]
set_property INTERNAL_VREF 0.84 [get_iobanks 44]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk]
set_property LOC BUFGCE_X0Y76 [get_cells kcu105_lpc_axieth_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/bufg_rgmii_rx_clk]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout1_buf]
set_property LOC BUFGCE_X0Y84 [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout1_buf]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout2_buf]
set_property LOC BUFGCE_X0Y75 [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout2_buf]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/bufg_rgmii_rx_clk]
set_property LOC BUFGCE_X0Y78 [get_cells kcu105_lpc_axieth_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/bufg_rgmii_rx_clk]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout3_buf]
set_property LOC BUFGCE_X0Y72 [get_cells kcu105_lpc_axieth_i/clk_wiz_0/inst/clkout3_buf]
set_property BEL BUFCE [get_cells kcu105_lpc_axieth_i/axi_ethernet_3/inst/mac/inst/rgmii_interface/bufg_rgmii_rx_clk]
set_property LOC BUFGCE_X0Y104 [get_cells kcu105_lpc_axieth_i/axi_ethernet_3/inst/mac/inst/rgmii_interface/bufg_rgmii_rx_clk]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]