From 004eddf805fb29fffbca3a9326264032adf33df0 Mon Sep 17 00:00:00 2001 From: David Sidler Date: Tue, 26 Jun 2018 01:36:53 +0200 Subject: [PATCH] major update to vc709 example project --- constraints/vc709.xdc | 8 +- projetcs/create_vc709_proj.tcl | 161 +-- rtl/7series/vc709/mem_inf.v | 1271 ++++++++--------------- rtl/7series/vc709/tcp_ip_top.v | 1743 +++++++++++--------------------- 4 files changed, 1081 insertions(+), 2102 deletions(-) diff --git a/constraints/vc709.xdc b/constraints/vc709.xdc index b359dcb..edae533 100644 --- a/constraints/vc709.xdc +++ b/constraints/vc709.xdc @@ -30,10 +30,10 @@ set_property IOSTANDARD LVCMOS18 [get_ports button_west] set_property PACKAGE_PIN AR40 [get_ports button_north] set_property IOSTANDARD LVCMOS18 [get_ports button_north] -#set_property PACKAGE_PIN AP40 [get_ports button_south] -#set_property IOSTANDARD LVCMOS18 [get_ports button_south] -#set_property PACKAGE_PIN AV39 [get_ports button_center] -#set_property IOSTANDARD LVCMOS18 [get_ports button_center] +set_property PACKAGE_PIN AP40 [get_ports button_south] +set_property IOSTANDARD LVCMOS18 [get_ports button_south] +set_property PACKAGE_PIN AV39 [get_ports button_center] +set_property IOSTANDARD LVCMOS18 [get_ports button_center] #UART diff --git a/projetcs/create_vc709_proj.tcl b/projetcs/create_vc709_proj.tcl index ad4c566..f1a965d 100755 --- a/projetcs/create_vc709_proj.tcl +++ b/projetcs/create_vc709_proj.tcl @@ -1,14 +1,16 @@ set proj_name "tcp_ip_vc709" set root_dir [pwd] -set proj_dir $root_dir/build/proj_vc709 +set proj_dir $root_dir/$proj_name set src_dir $root_dir/../rtl set ip_dir $root_dir/../ip +set ip_repo $root_dir/../iprepo set constraints_dir $root_dir/../constraints -if { [file isdirectory $root_dir/build/ipRepository] } { - set lib_dir "$root_dir/build/ipRepository" +#Check if iprepo is available +if { [file isdirectory $ip_repo] } { + set lib_dir "$ip_repo" } else { - puts "ipRepository directory could not be found." + puts "iprepo directory could not be found." exit 1 } # Create project @@ -27,126 +29,143 @@ add_files $src_dir/common add_files -norecurse $src_dir/7series add_files $src_dir/7series/vc709 set_property top tcp_ip_top [current_fileset] -remove_files $src_dir/common/arpServerWrapper.vhd add_files $ip_dir/mig_axi_mm_dual.dcp add_files $ip_dir/SmartCamCtl.dcp -#add_files $ip_dir/SmartCamCtlArp.dcp add_files -fileset constrs_1 $constraints_dir/vc709.xdc +#create ip directory +file mkdir $ip_dir/vc709 #create ips -create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -version 6.0 -module_name ten_gig_eth_pcs_pma_ip + +#Network interface + +create_ip -name ten_gig_eth_pcs_pma -vendor xilinx.com -library ip -version 6.0 -module_name ten_gig_eth_pcs_pma_ip -dir $ip_dir/vc709 set_property -dict [list CONFIG.MDIO_Management {false} CONFIG.base_kr {BASE-R} CONFIG.baser32 {64bit}] [get_ips ten_gig_eth_pcs_pma_ip] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/ten_gig_eth_pcs_pma_ip/ten_gig_eth_pcs_pma_ip.xci] +generate_target {instantiation_template} [get_files $ip_dir/vc709/ten_gig_eth_pcs_pma_ip/ten_gig_eth_pcs_pma_ip.xci] update_compile_order -fileset sources_1 -create_ip -name ten_gig_eth_mac -vendor xilinx.com -library ip -version 15.1 -module_name ten_gig_eth_mac_ip +create_ip -name ten_gig_eth_mac -vendor xilinx.com -library ip -version 15.1 -module_name ten_gig_eth_mac_ip -dir $ip_dir/vc709 set_property -dict [list CONFIG.Management_Interface {false} CONFIG.Statistics_Gathering {false}] [get_ips ten_gig_eth_mac_ip] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/ten_gig_eth_mac_ip/ten_gig_eth_mac_ip.xci] +generate_target {instantiation_template} [get_files $ip_dir/vc709/ten_gig_eth_mac_ip/ten_gig_eth_mac_ip.xci] update_compile_order -fileset sources_1 -#This is used in rx_isolation, maybe we use this later again -#create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.0 -module_name rx_fifo -#set_property -dict [list CONFIG.INTERFACE_TYPE {AXI_STREAM} CONFIG.TDATA_NUM_BYTES {8} CONFIG.TUSER_WIDTH {0} CONFIG.Enable_TLAST {true} CONFIG.HAS_TKEEP {true} CONFIG.Enable_Data_Counts_axis {true} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.TSTRB_WIDTH {8} CONFIG.TKEEP_WIDTH {8} CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wach {15} CONFIG.Empty_Threshold_Assert_Value_wach {14} CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wrch {15} CONFIG.Empty_Threshold_Assert_Value_wrch {14} CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_rach {15} CONFIG.Empty_Threshold_Assert_Value_rach {14}] [get_ips rx_fifo] -#generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/rx_fifo/rx_fifo.xci] -#update_compile_order -fileset sources_1 +#FIFOs -create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.1 -module_name axis_sync_fifo -set_property -dict [list CONFIG.INTERFACE_TYPE {AXI_STREAM} CONFIG.TDATA_NUM_BYTES {8} CONFIG.TUSER_WIDTH {0} CONFIG.Enable_TLAST {true} CONFIG.HAS_TKEEP {true} CONFIG.Enable_Data_Counts_axis {true} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.TSTRB_WIDTH {8} CONFIG.TKEEP_WIDTH {8} CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wach {15} CONFIG.Empty_Threshold_Assert_Value_wach {14} CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wrch {15} CONFIG.Empty_Threshold_Assert_Value_wrch {14} CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_rach {15} CONFIG.Empty_Threshold_Assert_Value_rach {14}] [get_ips axis_sync_fifo] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axis_sync_fifo/axis_sync_fifo.xci] -update_compile_order -fileset sources_1 +create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 1.1 -module_name axis_data_fifo_64_cc -dir $ip_dir/vc709 +set_property -dict [list CONFIG.TDATA_NUM_BYTES {8} CONFIG.IS_ACLK_ASYNC {1} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1} CONFIG.SYNCHRONIZATION_STAGES {3} CONFIG.Component_Name {axis_data_fifo_64_cc}] [get_ips axis_data_fifo_64_cc] +generate_target {instantiation_template} [get_files $ip_dir/vc709/axis_data_fifo_64_cc/axis_data_fifo_64_cc.xci] -# We could add it by .xcic -#add_files -norecurse /home/dasidler/workspace/fpga-network-stack/ip/cmd_fifo_xgemac_rxif.xcix -#export_ip_user_files -of_objects [get_files /home/dasidler/workspace/fpga-network-stack/ip/cmd_fifo_xgemac_rxif/cmd_fifo_xgemac_rxif.xci] -force -quiet -#update_compile_order -fileset sources_1 - -#or we could add it by .xci -#add_files -norecurse /home/dasidler/workspace/fpga-network-stack/ip/cmd_fifo_xgemac_rxif/cmd_fifo_xgemac_rxif.xci -#export_ip_user_files -of_objects [get_files /home/dasidler/workspace/fpga-network-stack/ip/cmd_fifo_xgemac_rxif/cmd_fifo_xgemac_rxif.xci] -force -quiet -#update_compile_order -fileset sources_1 +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name axis_sync_fifo -dir $ip_dir/vc709 +set_property -dict [list CONFIG.INTERFACE_TYPE {AXI_STREAM} CONFIG.FIFO_Implementation_axis {Common_Clock_Block_RAM} CONFIG.TDATA_NUM_BYTES {8} CONFIG.TUSER_WIDTH {0} CONFIG.Enable_TLAST {true} CONFIG.HAS_TKEEP {true} CONFIG.Enable_Data_Counts_axis {true} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.TSTRB_WIDTH {8} CONFIG.TKEEP_WIDTH {8} CONFIG.FIFO_Implementation_wach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wach {15} CONFIG.Empty_Threshold_Assert_Value_wach {14} CONFIG.FIFO_Implementation_wrch {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_wrch {15} CONFIG.Empty_Threshold_Assert_Value_wrch {14} CONFIG.FIFO_Implementation_rach {Common_Clock_Distributed_RAM} CONFIG.Full_Threshold_Assert_Value_rach {15} CONFIG.Empty_Threshold_Assert_Value_rach {14}] [get_ips axis_sync_fifo] +generate_target {instantiation_template} [get_files $ip_dir/vc709/axis_sync_fifo/axis_sync_fifo.xci] +update_compile_order -fileset sources_1 -create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.1 -module_name cmd_fifo_xgemac_rxif -set_property -dict [list CONFIG.Input_Data_Width {16} CONFIG.Output_Data_Width {16} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1}] [get_ips cmd_fifo_xgemac_rxif] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/cmd_fifo_xgemac_rxif/cmd_fifo_xgemac_rxif.xci] +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name cmd_fifo_xgemac_rxif -dir $ip_dir/vc709 +set_property -dict [list CONFIG.Fifo_Implementation {Common_Clock_Block_RAM} CONFIG.Input_Data_Width {16} CONFIG.Output_Data_Width {16} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.Use_Embedded_Registers {false} CONFIG.Full_Threshold_Assert_Value {1022} CONFIG.Full_Threshold_Negate_Value {1021} CONFIG.Enable_Safety_Circuit {false}] [get_ips cmd_fifo_xgemac_rxif] +generate_target {instantiation_template} [get_files $ip_dir/vc709/cmd_fifo_xgemac_rxif/cmd_fifo_xgemac_rxif.xci] update_compile_order -fileset sources_1 -create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.1 -module_name cmd_fifo_xgemac_txif -set_property -dict [list CONFIG.Input_Data_Width {1} CONFIG.Output_Data_Width {1} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1}] [get_ips cmd_fifo_xgemac_txif] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/cmd_fifo_xgemac_txif/cmd_fifo_xgemac_txif.xci] +create_ip -name fifo_generator -vendor xilinx.com -library ip -version 13.2 -module_name cmd_fifo_xgemac_txif -dir $ip_dir/vc709 +set_property -dict [list CONFIG.Fifo_Implementation {Common_Clock_Block_RAM} CONFIG.Input_Data_Width {1} CONFIG.Output_Data_Width {1} CONFIG.Reset_Type {Asynchronous_Reset} CONFIG.Full_Flags_Reset_Value {1} CONFIG.Full_Threshold_Assert_Value {1022} CONFIG.Full_Threshold_Negate_Value {1021} CONFIG.Enable_Safety_Circuit {false}] [get_ips cmd_fifo_xgemac_txif] +generate_target {instantiation_template} [get_files $ip_dir/vc709/cmd_fifo_xgemac_txif/cmd_fifo_xgemac_txif.xci] update_compile_order -fileset sources_1 -create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_64 +#Register slices + +create_ip -name axis_register_slice -vendor xilinx.com -library ip -version 1.1 -module_name axis_register_slice_64 -dir $ip_dir/vc709 set_property -dict [list CONFIG.TDATA_NUM_BYTES {8} CONFIG.HAS_TKEEP {1} CONFIG.HAS_TLAST {1}] [get_ips axis_register_slice_64] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axis_register_slice_64/axis_register_slice_64.xci] +generate_target {instantiation_template} [get_files $ip_dir/vc709/axis_register_slice_64/axis_register_slice_64.xci] update_compile_order -fileset sources_1 -create_ip -name toe -vendor ethz.systems -library hls -version 1.6 -module_name toe_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/toe_ip/toe_ip.xci] +#Interconnects + +create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_3to1 -dir $ip_dir/vc709 +set_property -dict [list CONFIG.C_NUM_SI_SLOTS {3} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true}] [get_ips axis_interconnect_3to1] +generate_target {instantiation_template} [get_files $ip_dir/vc709/axis_interconnect_3to1/axis_interconnect_3to1.xci] update_compile_order -fileset sources_1 -create_ip -name udp -vendor xilinx.labs -library hls -version 1.41 -module_name udp_0 -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/udp_0/udp_0.xci] +create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_2to1 -dir $ip_dir/vc709 +set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_2to1] +generate_target {instantiation_template} [get_files $ip_dir/axis_interconnect_2to1/axis_interconnect_2to1.xci] update_compile_order -fileset sources_1 -create_ip -name ip_handler -vendor ethz.systems -library hls -version 1.2 -module_name ip_handler_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/ip_handler_ip/ip_handler_ip.xci] +#HLS IP cores + +create_ip -name toe -vendor ethz.systems -library hls -version 1.6 -module_name toe_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/toe_ip/toe_ip.xci] update_compile_order -fileset sources_1 -create_ip -name mac_ip_encode -vendor xilinx.labs -library hls -version 1.04 -module_name mac_ip_encode_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/mac_ip_encode_ip/mac_ip_encode_ip.xci] +create_ip -name ip_handler -vendor ethz.systems -library hls -version 1.2 -module_name ip_handler_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/ip_handler_ip/ip_handler_ip.xci] update_compile_order -fileset sources_1 -create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_3to1 -set_property -dict [list CONFIG.C_NUM_SI_SLOTS {3} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_S02_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true} CONFIG.M00_S02_CONNECTIVITY {true}] [get_ips axis_interconnect_3to1] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axis_interconnect_3to1/axis_interconnect_3to1.xci] +create_ip -name mac_ip_encode -vendor xilinx.labs -library hls -version 1.04 -module_name mac_ip_encode_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/mac_ip_encode_ip/mac_ip_encode_ip.xci] update_compile_order -fileset sources_1 -create_ip -name axis_interconnect -vendor xilinx.com -library ip -version 1.1 -module_name axis_interconnect_2to1 -set_property -dict [list CONFIG.C_NUM_SI_SLOTS {2} CONFIG.SWITCH_TDATA_NUM_BYTES {8} CONFIG.HAS_TSTRB {false} CONFIG.HAS_TID {false} CONFIG.HAS_TDEST {false} CONFIG.SWITCH_PACKET_MODE {true} CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {0} CONFIG.C_M00_AXIS_REG_CONFIG {1} CONFIG.C_S00_AXIS_REG_CONFIG {1} CONFIG.C_S01_AXIS_REG_CONFIG {1} CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} CONFIG.M00_S01_CONNECTIVITY {true}] [get_ips axis_interconnect_2to1] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axis_interconnect_2to1/axis_interconnect_2to1.xci] +create_ip -name ethernet_frame_padding -vendor ethz.systems.fpga -library hls -version 0.1 -module_name ethernet_frame_padding_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/ethernet_frame_padding_ip/ethernet_frame_padding_ip.xci] update_compile_order -fileset sources_1 -create_ip -name icmp_server -vendor xilinx.labs -library hls -version 1.67 -module_name icmp_server_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/icmp_server_ip/icmp_server_ip.xci] +create_ip -name icmp_server -vendor xilinx.labs -library hls -version 1.67 -module_name icmp_server_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/icmp_server_ip/icmp_server_ip.xci] update_compile_order -fileset sources_1 -create_ip -name udpAppMux -vendor xilinx.labs -library hls -version 1.05 -module_name udpAppMux_0 -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/udpAppMux_0/udpAppMux_0.xci] +create_ip -name echo_server_application -vendor ethz.systems -library hls -version 1.2 -module_name echo_server_application_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/echo_server_application_ip/echo_server_application_ip.xci] update_compile_order -fileset sources_1 -create_ip -name dhcp_client -vendor xilinx.labs -library hls -version 1.05 -module_name dhcp_client_0 -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/dhcp_client_0/dhcp_client_0.xci] +create_ip -name iperf_client -vendor ethz.systems.fpga -library hls -version 1.0 -module_name iperf_client_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/iperf_client_ip/iperf_client_ip.xci] update_compile_order -fileset sources_1 -create_ip -name echo_server_application -vendor ethz.systems -library hls -version 1.1 -module_name echo_server_application_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/echo_server_application_ip/echo_server_application_ip.xci] +create_ip -name arp_server_subnet -vendor ethz.systems -library hls -version 1.0 -module_name arp_server_subnet_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/arp_server_subnet_ip/arp_server_subnet_ip.xci] update_compile_order -fileset sources_1 -create_ip -name udpLoopback -vendor xilinx.labs -library hls -version 1.10 -module_name udpLoopback_0 -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/udpLoopback_0/udpLoopback_0.xci] +create_ip -name ipv4 -vendor ethz.systems.fpga -library hls -version 0.1 -module_name ipv4_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/ipv4_ip/ipv4_ip.xci] update_compile_order -fileset sources_1 -create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_ip -set_property -dict [list CONFIG.INTERCONNECT_DATA_WIDTH {512} CONFIG.S00_AXI_DATA_WIDTH {512} CONFIG.S01_AXI_DATA_WIDTH {512} CONFIG.M00_AXI_DATA_WIDTH {512} CONFIG.S00_AXI_IS_ACLK_ASYNC {1} CONFIG.S01_AXI_IS_ACLK_ASYNC {1} CONFIG.M00_AXI_IS_ACLK_ASYNC {1} CONFIG.S00_AXI_WRITE_ACCEPTANCE {16} CONFIG.S01_AXI_WRITE_ACCEPTANCE {16} CONFIG.S00_AXI_READ_ACCEPTANCE {16} CONFIG.S01_AXI_READ_ACCEPTANCE {16} CONFIG.M00_AXI_WRITE_ISSUING {16} CONFIG.M00_AXI_READ_ISSUING {16} CONFIG.S00_AXI_REGISTER {1} CONFIG.S01_AXI_REGISTER {1} CONFIG.M00_AXI_REGISTER {1}] [get_ips axi_interconnect_ip] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axi_interconnect_ip/axi_interconnect_ip.xci] +create_ip -name udp -vendor ethz.systems.fpga -library hls -version 0.4 -module_name udp_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/udp_ip/udp_ip.xci] update_compile_order -fileset sources_1 -create_ip -name axi_datamover -vendor xilinx.com -library ip -version 5.1 -module_name axi_datamover_0 -set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512} CONFIG.c_m_axis_mm2s_tdata_width {64} CONFIG.c_include_mm2s_dre {true} CONFIG.c_mm2s_burst_size {16} CONFIG.c_m_axi_s2mm_data_width {512} CONFIG.c_s_axis_s2mm_tdata_width {64} CONFIG.c_include_s2mm_dre {true} CONFIG.c_s2mm_burst_size {16}] [get_ips axi_datamover_0] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axi_datamover_0/axi_datamover_0.xci] +create_ip -name iperf_udp_client -vendor ethz.systems.fpga -library hls -version 0.8 -module_name iperf_udp_client_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/iperf_udp_client_ip/iperf_udp_client_ip.xci] update_compile_order -fileset sources_1 -create_ip -name axi_datamover -vendor xilinx.com -library ip -version 5.1 -module_name axi_datamover_1 -set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512} CONFIG.c_m_axis_mm2s_tdata_width {512} CONFIG.c_mm2s_burst_size {2} CONFIG.c_mm2s_btt_used {10} CONFIG.c_m_axi_s2mm_data_width {512} CONFIG.c_s_axis_s2mm_tdata_width {512} CONFIG.c_s2mm_btt_used {10} CONFIG.c_mm2s_include_sf {false} CONFIG.c_s2mm_include_sf {false} CONFIG.c_s2mm_burst_size {4}] [get_ips axi_datamover_1] -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/axi_datamover_1/axi_datamover_1.xci] +#create_ip -name udpAppMux -vendor xilinx.labs -library hls -version 1.05 -module_name udpAppMux_0 -dir $ip_dir/vc709 +#generate_target {instantiation_template} [get_files $ip_dir/vc709/udpAppMux_0/udpAppMux_0.xci] +#update_compile_order -fileset sources_1 + +create_ip -name dhcp_client -vendor xilinx.labs -library hls -version 1.05 -module_name dhcp_client_ip -dir $ip_dir/vc709 +generate_target {instantiation_template} [get_files $ip_dir/vc709/dhcp_client_ip/dhcp_client_ip.xci] update_compile_order -fileset sources_1 -create_ip -name arp_server_subnet -vendor ethz.systems -library hls -version 1.0 -module_name arp_server_subnet_ip -generate_target {instantiation_template} [get_files $proj_dir/tcp_ip.srcs/sources_1/ip/arp_server_subnet_ip/arp_server_subnet_ip.xci] + +#VIOs + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name vio_iperf -dir $ip_dir/vc709 +set_property -dict [list CONFIG.C_NUM_PROBE_OUT {2} CONFIG.C_EN_PROBE_IN_ACTIVITY {0} CONFIG.C_NUM_PROBE_IN {0} CONFIG.Component_Name {vio_iperf}] [get_ips vio_iperf] +generate_target {instantiation_template} [get_files $ip_dir/vc709/vio_iperf/vio_iperf.xci] + +create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name vio_udp_iperf_client -dir $ip_dir/vc709 +set_property -dict [list CONFIG.C_EN_PROBE_IN_ACTIVITY {0} CONFIG.C_NUM_PROBE_IN {0} CONFIG.Component_Name {vio_udp_iperf_client}] [get_ips vio_udp_iperf_client] +generate_target {instantiation_template} [get_files $ip_dir/vc709/vio_udp_iperf_client/vio_udp_iperf_client.xci] + +#Memory interface + +create_ip -name axi_datamover -vendor xilinx.com -library ip -version 5.1 -module_name axi_datamover_64_to_512 -dir $ip_dir/vc709 +set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512} CONFIG.c_m_axis_mm2s_tdata_width {64} CONFIG.c_include_mm2s_dre {true} CONFIG.c_mm2s_burst_size {16} CONFIG.c_m_axi_s2mm_data_width {512} CONFIG.c_s_axis_s2mm_tdata_width {64} CONFIG.c_include_s2mm_dre {true} CONFIG.c_s2mm_burst_size {16} CONFIG.c_mm2s_stscmd_is_async {true} CONFIG.c_s2mm_stscmd_is_async {true}] [get_ips axi_datamover_64_to_512] +generate_target {instantiation_template} [get_files $ip_dir/vc709/axi_datamover_64_to_512/axi_datamover_64_to_512.xci] update_compile_order -fileset sources_1 + + + #add MIG for VC709 #add_files -norecurse $ip_dir/mig_axi_mm_dual/mig_axi_mm_dual.xci #export_ip_user_files -of_objects [get_files $ip_dir/mig_axi_mm_dual/mig_axi_mm_dual.xci] -force -quiet diff --git a/rtl/7series/vc709/mem_inf.v b/rtl/7series/vc709/mem_inf.v index ce65d10..ec5a37b 100755 --- a/rtl/7series/vc709/mem_inf.v +++ b/rtl/7series/vc709/mem_inf.v @@ -1,9 +1,10 @@ `timescale 1ns / 1ps +`default_nettype none ////////////////////////////////////////////////////////////////////////////////// // Company: -// Engineer: +// Engineer: David Sidler // -// Create Date: 11/11/2013 02:22:48 PM +// Create Date: 05/09/2018 02:32:06 PM // Design Name: // Module Name: mem_inf // Project Name: @@ -20,183 +21,124 @@ ////////////////////////////////////////////////////////////////////////////////// -module mem_inf #( - parameter C0_SIMULATION = "FALSE", - parameter C1_SIMULATION = "FALSE", - parameter C0_SIM_BYPASS_INIT_CAL = "OFF", - parameter C1_SIM_BYPASS_INIT_CAL = "OFF" -) -( -input clk156_25, -input reset156_25_n, -input clk212, -input clk200, -input sys_rst, +module mem_inf #( + parameter ENABLE_DDR0 = 1, + parameter ENABLE_DDR1 = 1 +)( +input wire clk156_25, +input wire reset156_25_n, +input wire clk212, +input wire clk200, +input wire sys_rst, //ddr3 pins //SODIMM 0 // Inouts -inout [63:0] c0_ddr3_dq, -inout [7:0] c0_ddr3_dqs_n, -inout [7:0] c0_ddr3_dqs_p, - -// Outputs -output [15:0] c0_ddr3_addr, -output [2:0] c0_ddr3_ba, -output c0_ddr3_ras_n, -output c0_ddr3_cas_n, -output c0_ddr3_we_n, -output c0_ddr3_reset_n, -output c0_ddr3_ck_p, -output c0_ddr3_ck_n, -output c0_ddr3_cke, -output c0_ddr3_cs_n, -output [7:0] c0_ddr3_dm, -output c0_ddr3_odt, -output c0_ui_clk, -output c0_init_calib_complete, +inout wire [63:0] c0_ddr3_dq, +inout wire [7:0] c0_ddr3_dqs_n, +inout wire [7:0] c0_ddr3_dqs_p, + +// output wires +output wire [15:0] c0_ddr3_addr, +output wire [2:0] c0_ddr3_ba, +output wire c0_ddr3_ras_n, +output wire c0_ddr3_cas_n, +output wire c0_ddr3_we_n, +output wire c0_ddr3_reset_n, +output wire c0_ddr3_ck_p, +output wire c0_ddr3_ck_n, +output wire c0_ddr3_cke, +output wire c0_ddr3_cs_n, +output wire [7:0] c0_ddr3_dm, +output wire c0_ddr3_odt, +output wire c0_ui_clk, +output wire c0_init_calib_complete, //SODIMM 1 // Inouts -inout [63:0] c1_ddr3_dq, -inout [7:0] c1_ddr3_dqs_n, -inout [7:0] c1_ddr3_dqs_p, - -// Outputs -output [15:0] c1_ddr3_addr, -output [2:0] c1_ddr3_ba, -output c1_ddr3_ras_n, -output c1_ddr3_cas_n, -output c1_ddr3_we_n, -output c1_ddr3_reset_n, -output c1_ddr3_ck_p, -output c1_ddr3_ck_n, -output c1_ddr3_cke, -output c1_ddr3_cs_n, -output [7:0] c1_ddr3_dm, -output c1_ddr3_odt, - -//ui outputs -output c1_ui_clk, -output c1_init_calib_complete, - -//toe stream interface signals -input toeTX_s_axis_read_cmd_tvalid, -output toeTX_s_axis_read_cmd_tready, -input[71:0] toeTX_s_axis_read_cmd_tdata, -//read status -output toeTX_m_axis_read_sts_tvalid, -input toeTX_m_axis_read_sts_tready, -output[7:0] toeTX_m_axis_read_sts_tdata, -//read stream -output[63:0] toeTX_m_axis_read_tdata, -output[7:0] toeTX_m_axis_read_tkeep, -output toeTX_m_axis_read_tlast, -output toeTX_m_axis_read_tvalid, -input toeTX_m_axis_read_tready, - -//write commands -input toeTX_s_axis_write_cmd_tvalid, -output toeTX_s_axis_write_cmd_tready, -input[71:0] toeTX_s_axis_write_cmd_tdata, -//write status -output toeTX_m_axis_write_sts_tvalid, -input toeTX_m_axis_write_sts_tready, -output[7:0] toeTX_m_axis_write_sts_tdata, -//write stream -input[63:0] toeTX_s_axis_write_tdata, -input[7:0] toeTX_s_axis_write_tkeep, -input toeTX_s_axis_write_tlast, -input toeTX_s_axis_write_tvalid, -output toeTX_s_axis_write_tready, - -input toeRX_s_axis_read_cmd_tvalid, -output toeRX_s_axis_read_cmd_tready, -input[71:0] toeRX_s_axis_read_cmd_tdata, -//read status -output toeRX_m_axis_read_sts_tvalid, -input toeRX_m_axis_read_sts_tready, -output[7:0] toeRX_m_axis_read_sts_tdata, -//read stream -output[63:0] toeRX_m_axis_read_tdata, -output[7:0] toeRX_m_axis_read_tkeep, -output toeRX_m_axis_read_tlast, -output toeRX_m_axis_read_tvalid, -input toeRX_m_axis_read_tready, - -//write commands -input toeRX_s_axis_write_cmd_tvalid, -output toeRX_s_axis_write_cmd_tready, -input[71:0] toeRX_s_axis_write_cmd_tdata, -//write status -output toeRX_m_axis_write_sts_tvalid, -input toeRX_m_axis_write_sts_tready, -output[7:0] toeRX_m_axis_write_sts_tdata, -//write stream -input[63:0] toeRX_s_axis_write_tdata, -input[7:0] toeRX_s_axis_write_tkeep, -input toeRX_s_axis_write_tlast, -input toeRX_s_axis_write_tvalid, -output toeRX_s_axis_write_tready, -//ht stream interface signals -input ht_s_axis_read_cmd_tvalid, -output ht_s_axis_read_cmd_tready, -input[71:0] ht_s_axis_read_cmd_tdata, -//read status -output ht_m_axis_read_sts_tvalid, -input ht_m_axis_read_sts_tready, -output[7:0] ht_m_axis_read_sts_tdata, -//read stream -output[511:0] ht_m_axis_read_tdata, -output[63:0] ht_m_axis_read_tkeep, -output ht_m_axis_read_tlast, -output ht_m_axis_read_tvalid, -input ht_m_axis_read_tready, - -//write commands -input ht_s_axis_write_cmd_tvalid, -output ht_s_axis_write_cmd_tready, -input[71:0] ht_s_axis_write_cmd_tdata, -//write status -output ht_m_axis_write_sts_tvalid, -input ht_m_axis_write_sts_tready, -output[7:0] ht_m_axis_write_sts_tdata, -//write stream -input[511:0] ht_s_axis_write_tdata, -input[63:0] ht_s_axis_write_tkeep, -input ht_s_axis_write_tlast, -input ht_s_axis_write_tvalid, -output ht_s_axis_write_tready, - -//upd stream interface signals -input upd_s_axis_read_cmd_tvalid, -output upd_s_axis_read_cmd_tready, -input[71:0] upd_s_axis_read_cmd_tdata, -//read status -output upd_m_axis_read_sts_tvalid, -input upd_m_axis_read_sts_tready, -output[7:0] upd_m_axis_read_sts_tdata, -//read stream -output[511:0] upd_m_axis_read_tdata, -output[63:0] upd_m_axis_read_tkeep, -output upd_m_axis_read_tlast, -output upd_m_axis_read_tvalid, -input upd_m_axis_read_tready, - -//write commands -input upd_s_axis_write_cmd_tvalid, -output upd_s_axis_write_cmd_tready, -input[71:0] upd_s_axis_write_cmd_tdata, -//write status -output upd_m_axis_write_sts_tvalid, -input upd_m_axis_write_sts_tready, -output[7:0] upd_m_axis_write_sts_tdata, -//write stream -input[511:0] upd_s_axis_write_tdata, -input[63:0] upd_s_axis_write_tkeep, -input upd_s_axis_write_tlast, -input upd_s_axis_write_tvalid, -output upd_s_axis_write_tready); +inout wire [63:0] c1_ddr3_dq, +inout wire [7:0] c1_ddr3_dqs_n, +inout wire [7:0] c1_ddr3_dqs_p, + +// output wires +output wire [15:0] c1_ddr3_addr, +output wire [2:0] c1_ddr3_ba, +output wire c1_ddr3_ras_n, +output wire c1_ddr3_cas_n, +output wire c1_ddr3_we_n, +output wire c1_ddr3_reset_n, +output wire c1_ddr3_ck_p, +output wire c1_ddr3_ck_n, +output wire c1_ddr3_cke, +output wire c1_ddr3_cs_n, +output wire [7:0] c1_ddr3_dm, +output wire c1_ddr3_odt, + +//ui output wires +output wire c1_ui_clk, +output wire c1_init_calib_complete, + +//memory access + //memory 0 read path + input wire s_axis_mem0_read_cmd_tvalid, + output wire s_axis_mem0_read_cmd_tready, + input wire[71:0] s_axis_mem0_read_cmd_tdata, + //read status + output wire m_axis_mem0_read_sts_tvalid, + input wire m_axis_mem0_read_sts_tready, + output wire[7:0] m_axis_mem0_read_sts_tdata, + //read stream + output wire[63:0] m_axis_mem0_read_tdata, + output wire[7:0] m_axis_mem0_read_tkeep, + output wire m_axis_mem0_read_tlast, + output wire m_axis_mem0_read_tvalid, + input wire m_axis_mem0_read_tready, + + //memory 0 write path + input wire s_axis_mem0_write_cmd_tvalid, + output wire s_axis_mem0_write_cmd_tready, + input wire[71:0] s_axis_mem0_write_cmd_tdata, + //write status + output wire m_axis_mem0_write_sts_tvalid, + input wire m_axis_mem0_write_sts_tready, + output wire[7:0] m_axis_mem0_write_sts_tdata, + //write stream + input wire[63:0] s_axis_mem0_write_tdata, + input wire[7:0] s_axis_mem0_write_tkeep, + input wire s_axis_mem0_write_tlast, + input wire s_axis_mem0_write_tvalid, + output wire s_axis_mem0_write_tready, + + //memory 1 read path + input wire s_axis_mem1_read_cmd_tvalid, + output wire s_axis_mem1_read_cmd_tready, + input wire[71:0] s_axis_mem1_read_cmd_tdata, + //read status + output wire m_axis_mem1_read_sts_tvalid, + input wire m_axis_mem1_read_sts_tready, + output wire[7:0] m_axis_mem1_read_sts_tdata, + //read stream + output wire[63:0] m_axis_mem1_read_tdata, + output wire[7:0] m_axis_mem1_read_tkeep, + output wire m_axis_mem1_read_tlast, + output wire m_axis_mem1_read_tvalid, + input wire m_axis_mem1_read_tready, + + //memory 1 write path + input wire s_axis_mem1_write_cmd_tvalid, + output wire s_axis_mem1_write_cmd_tready, + input wire[71:0] s_axis_mem1_write_cmd_tdata, + //write status + output wire m_axis_mem1_write_sts_tvalid, + input wire m_axis_mem1_write_sts_tready, + output wire[7:0] m_axis_mem1_write_sts_tdata, + //write stream + input wire[63:0] s_axis_mem1_write_tdata, + input wire[7:0] s_axis_mem1_write_tkeep, + input wire s_axis_mem1_write_tlast, + input wire s_axis_mem1_write_tvalid, + output wire s_axis_mem1_write_tready +); localparam C0_C_S_AXI_ID_WIDTH = 1; localparam C0_C_S_AXI_ADDR_WIDTH = 33; @@ -461,725 +403,320 @@ always @(posedge c0_ui_clk) always @(posedge c1_ui_clk) c1_aresetn_r <= ~c1_ui_clk_sync_rst & c1_mmcm_locked; + + +/* + * CLOCK CROSSING + */ + +wire axis_mem0_cc_to_dm_write_tvalid; +wire axis_mem0_cc_to_dm_write_tready; +wire[63:0] axis_mem0_cc_to_dm_write_tdata; +wire[7:0] axis_mem0_cc_to_dm_write_tkeep; +wire axis_mem0_cc_to_dm_write_tlast; + +wire axis_mem0_dm_to_cc_read_tvalid; +wire axis_mem0_dm_to_cc_read_tready; +wire[63:0] axis_mem0_dm_to_cc_read_tdata; +wire[7:0] axis_mem0_dm_to_cc_read_tkeep; +wire axis_mem0_dm_to_cc_read_tlast; + +generate + if (ENABLE_DDR0 == 1) begin - wire [0 : 0] S10_AXI_AWID; - wire [31 : 0] S10_AXI_AWADDR; - wire [7 : 0] S10_AXI_AWLEN; - wire [2 : 0] S10_AXI_AWSIZE; - wire [1 : 0] S10_AXI_AWBURST; - wire S10_AXI_AWLOCK; - wire [3 : 0] S10_AXI_AWCACHE; - wire [2 : 0] S10_AXI_AWPROT; - wire [3 : 0] S10_AXI_AWQOS; - wire S10_AXI_AWVALID; - wire S10_AXI_AWREADY; - wire [511 : 0] S10_AXI_WDATA; - wire [63 : 0] S10_AXI_WSTRB; - wire S10_AXI_WLAST; - wire S10_AXI_WVALID; - wire S10_AXI_WREADY; - wire [0 : 0] S10_AXI_BID; - wire [1 : 0] S10_AXI_BRESP; - wire S10_AXI_BVALID; - wire S10_AXI_BREADY; - wire [0 : 0] S10_AXI_ARID; - wire [31 : 0] S10_AXI_ARADDR; - wire [7 : 0] S10_AXI_ARLEN; - wire [2 : 0] S10_AXI_ARSIZE; - wire [1 : 0] S10_AXI_ARBURST; - wire S10_AXI_ARLOCK; - wire [3 : 0] S10_AXI_ARCACHE; - wire [2 : 0] S10_AXI_ARPROT; - wire [3 : 0] S10_AXI_ARQOS; - wire S10_AXI_ARVALID; - wire S10_AXI_ARREADY; - wire [0 : 0] S10_AXI_RID; - wire [511 : 0] S10_AXI_RDATA; - wire [1 : 0] S10_AXI_RRESP; - wire S10_AXI_RLAST; - wire S10_AXI_RVALID; - wire S10_AXI_RREADY; - wire S11_AXI_ARESET_OUT_N; - wire S11_AXI_ACLK; - wire [0 : 0] S11_AXI_AWID; - wire [31 : 0] S11_AXI_AWADDR; - wire [7 : 0] S11_AXI_AWLEN; - wire [2 : 0] S11_AXI_AWSIZE; - wire [1 : 0] S11_AXI_AWBURST; - wire S11_AXI_AWLOCK; - wire [3 : 0] S11_AXI_AWCACHE; - wire [2 : 0] S11_AXI_AWPROT; - wire [3 : 0] S11_AXI_AWQOS; - wire S11_AXI_AWVALID; - wire S11_AXI_AWREADY; - wire [511 : 0] S11_AXI_WDATA; - wire [63 : 0] S11_AXI_WSTRB; - wire S11_AXI_WLAST; - wire S11_AXI_WVALID; - wire S11_AXI_WREADY; - wire [0 : 0] S11_AXI_BID; - wire [1 : 0] S11_AXI_BRESP; - wire S11_AXI_BVALID; - wire S11_AXI_BREADY; - wire [0 : 0] S11_AXI_ARID; - wire [31 : 0] S11_AXI_ARADDR; - wire [7 : 0] S11_AXI_ARLEN; - wire [2 : 0] S11_AXI_ARSIZE; - wire [1 : 0] S11_AXI_ARBURST; - wire S11_AXI_ARLOCK; - wire [3 : 0] S11_AXI_ARCACHE; - wire [2 : 0] S11_AXI_ARPROT; - wire [3 : 0] S11_AXI_ARQOS; - wire S11_AXI_ARVALID; - wire S11_AXI_ARREADY; - wire [0 : 0] S11_AXI_RID; - wire [511 : 0] S11_AXI_RDATA; - wire [1 : 0] S11_AXI_RRESP; - wire S11_AXI_RLAST; - wire S11_AXI_RVALID; - wire S11_AXI_RREADY; - - wire [3:0] c0_s_axi_arid_x; - assign c0_s_axi_arid = c0_s_axi_arid_x[0]; - wire [3:0] S10_AXI_ARID_x, S10_AXI_AWID_x; - assign S10_AXI_ARID = S10_AXI_ARID_x[0]; - assign S10_AXI_AWID = S10_AXI_AWID_x[0]; - - wire [3:0] S11_AXI_ARID_x, S11_AXI_AWID_x; - assign S11_AXI_ARID = S11_AXI_ARID_x[0]; - assign S11_AXI_AWID = S11_AXI_AWID_x[0]; +axis_data_fifo_64_cc axis_write_data_fifo_mem0 ( + .s_axis_aclk(clk156_25), // input wire s_axis_aclk + .s_axis_aresetn(reset156_25_n), // input wire s_axis_aresetn + .s_axis_tvalid(s_axis_mem0_write_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_mem0_write_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_mem0_write_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_mem0_write_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_mem0_write_tlast), // input wire s_axis_tlast + + .m_axis_aclk(c0_ui_clk), // input wire m_axis_aclk + .m_axis_aresetn(c0_aresetn_r), // input wire m_axis_aresetn + .m_axis_tvalid(axis_mem0_cc_to_dm_write_tvalid), // output wire m_axis_tvalid + .m_axis_tready(axis_mem0_cc_to_dm_write_tready), // input wire m_axis_tready + .m_axis_tdata(axis_mem0_cc_to_dm_write_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(axis_mem0_cc_to_dm_write_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(axis_mem0_cc_to_dm_write_tlast), // output wire m_axis_tlast + + .axis_data_count(), // output wire [31 : 0] axis_data_count + .axis_wr_data_count(), // output wire [31 : 0] axis_wr_data_count + .axis_rd_data_count() // output wire [31 : 0] axis_rd_data_count + ); + +axis_data_fifo_64_cc axis_read_data_fifo_mem0 ( + .s_axis_aclk(c0_ui_clk), // input wire s_axis_aclk + .s_axis_aresetn(c0_aresetn_r), // input wire s_axis_aresetn + .s_axis_tvalid(axis_mem0_dm_to_cc_read_tvalid), // input wire s_axis_tvalid + .s_axis_tready(axis_mem0_dm_to_cc_read_tready), // output wire s_axis_tready + .s_axis_tdata(axis_mem0_dm_to_cc_read_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(axis_mem0_dm_to_cc_read_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(axis_mem0_dm_to_cc_read_tlast), // input wire s_axis_tlast + + .m_axis_aclk(clk156_25), // input wire m_axis_aclk + .m_axis_aresetn(reset156_25_n), // input wire m_axis_aresetn + .m_axis_tvalid(m_axis_mem0_read_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_mem0_read_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_mem0_read_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_mem0_read_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_mem0_read_tlast), // output wire m_axis_tlast + + .axis_data_count(), // output wire [31 : 0] axis_data_count + .axis_wr_data_count(), // output wire [31 : 0] axis_wr_data_count + .axis_rd_data_count() // output wire [31 : 0] axis_rd_data_count + ); + end + else begin + assign s_axis_mem0_write_tready = 1'b1; + assign m_axis_mem0_read_tvalid = 1'b0; + end +endgenerate + + +wire axis_mem1_cc_to_dm_write_tvalid; +wire axis_mem1_cc_to_dm_write_tready; +wire[63:0] axis_mem1_cc_to_dm_write_tdata; +wire[7:0] axis_mem1_cc_to_dm_write_tkeep; +wire axis_mem1_cc_to_dm_write_tlast; + +wire axis_mem1_dm_to_cc_read_tvalid; +wire axis_mem1_dm_to_cc_read_tready; +wire[63:0] axis_mem1_dm_to_cc_read_tdata; +wire[7:0] axis_mem1_dm_to_cc_read_tkeep; +wire axis_mem1_dm_to_cc_read_tlast; + +generate + if (ENABLE_DDR1 == 1) begin - axi_interconnect_ip toeTX_axi_switch ( - .INTERCONNECT_ACLK(clk156_25),//input ; - .INTERCONNECT_ARESETN(reset156_25_n),//input ; - .S00_AXI_ARESET_OUT_N(),//output ; - .S00_AXI_ACLK(clk156_25),//input ; - .S00_AXI_AWID(S10_AXI_AWID),//input [0 : 0] ; - .S00_AXI_AWADDR(S10_AXI_AWADDR[31:0]),//input [31 : 0] ; - .S00_AXI_AWLEN(S10_AXI_AWLEN),//input [7 : 0] ; - .S00_AXI_AWSIZE(S10_AXI_AWSIZE),//input [2 : 0] ; - .S00_AXI_AWBURST(S10_AXI_AWBURST),//input [1 : 0] ; - .S00_AXI_AWLOCK(1'b0),//input ; - .S00_AXI_AWCACHE(4'b0),//input [3 : 0] ; - .S00_AXI_AWPROT(3'b0),//input [2 : 0] ; - .S00_AXI_AWQOS(4'b0),//input [3 : 0] ; - .S00_AXI_AWVALID(S10_AXI_AWVALID),//input ; - .S00_AXI_AWREADY(S10_AXI_AWREADY),//output ; - .S00_AXI_WDATA(S10_AXI_WDATA),//input [511 : 0] ; - .S00_AXI_WSTRB(S10_AXI_WSTRB),//input [63 : 0] ; - .S00_AXI_WLAST(S10_AXI_WLAST),//input ; - .S00_AXI_WVALID(S10_AXI_WVALID),//input ; - .S00_AXI_WREADY(S10_AXI_WREADY),//output ; - .S00_AXI_BID(S10_AXI_BID),//output [0 : 0] ; - .S00_AXI_BRESP(S10_AXI_BRESP),//output [1 : 0] ; - .S00_AXI_BVALID(S10_AXI_BVALID),//output ; - .S00_AXI_BREADY(S10_AXI_BREADY),//input ; - .S00_AXI_ARID(S10_AXI_ARID),//input [0 : 0] ; - .S00_AXI_ARADDR(S10_AXI_ARADDR[31:0]),//input [31 : 0] ; - .S00_AXI_ARLEN(S10_AXI_ARLEN),//input [7 : 0] ; - .S00_AXI_ARSIZE(S10_AXI_ARSIZE),//input [2 : 0] ; - .S00_AXI_ARBURST(S10_AXI_ARBURST),//input [1 : 0] ; - .S00_AXI_ARLOCK(1'b0),//input ; - .S00_AXI_ARCACHE(4'b0),//input [3 : 0] ; - .S00_AXI_ARPROT(3'b0),//input [2 : 0] ; - .S00_AXI_ARQOS(4'b0),//input [3 : 0] ; - .S00_AXI_ARVALID(S10_AXI_ARVALID),//input ; - .S00_AXI_ARREADY(S10_AXI_ARREADY),//output ; - .S00_AXI_RID(S10_AXI_RID),//output [0 : 0] ; - .S00_AXI_RDATA(S10_AXI_RDATA),//output [511 : 0] ; - .S00_AXI_RRESP(S10_AXI_RRESP),//output [1 : 0] ; - .S00_AXI_RLAST(S10_AXI_RLAST),//output ; - .S00_AXI_RVALID(S10_AXI_RVALID),//output ; - .S00_AXI_RREADY(S10_AXI_RREADY),//input ; - .S01_AXI_ARESET_OUT_N(S11_AXI_ARESET_OUT_N),//output ; - .S01_AXI_ACLK(clk156_25),//input ; - .S01_AXI_AWID(S11_AXI_AWID),//input [0 : 0] ; - .S01_AXI_AWADDR(S11_AXI_AWADDR[31:0]),//input [31 : 0] ; - .S01_AXI_AWLEN(S11_AXI_AWLEN),//input [7 : 0] ; - .S01_AXI_AWSIZE(S11_AXI_AWSIZE),//input [2 : 0] ; - .S01_AXI_AWBURST(S11_AXI_AWBURST),//input [1 : 0] ; - .S01_AXI_AWLOCK(1'b0),//input ; - .S01_AXI_AWCACHE(4'b0),//input [3 : 0] ; - .S01_AXI_AWPROT(3'b0),//input [2 : 0] ; - .S01_AXI_AWQOS(4'b0),//input [3 : 0] ; - .S01_AXI_AWVALID(S11_AXI_AWVALID),//input ; - .S01_AXI_AWREADY(S11_AXI_AWREADY),//output ; - .S01_AXI_WDATA(S11_AXI_WDATA),//input [511 : 0] ; - .S01_AXI_WSTRB(S11_AXI_WSTRB),//input [63 : 0] ; - .S01_AXI_WLAST(S11_AXI_WLAST),//input ; - .S01_AXI_WVALID(S11_AXI_WVALID),//input ; - .S01_AXI_WREADY(S11_AXI_WREADY),//output ; - .S01_AXI_BID(S11_AXI_BID),//output [0 : 0] ; - .S01_AXI_BRESP(S11_AXI_BRESP),//output [1 : 0] ; - .S01_AXI_BVALID(S11_AXI_BVALID),//output ; - .S01_AXI_BREADY(S11_AXI_BREADY),//input ; - .S01_AXI_ARID(S11_AXI_ARID),//input [0 : 0] ; - .S01_AXI_ARADDR(S11_AXI_ARADDR[31:0]),//input [31 : 0] ; - .S01_AXI_ARLEN(S11_AXI_ARLEN),//input [7 : 0] ; - .S01_AXI_ARSIZE(S11_AXI_ARSIZE),//input [2 : 0] ; - .S01_AXI_ARBURST(S11_AXI_ARBURST),//input [1 : 0] ; - .S01_AXI_ARLOCK(1'b0),//input ; - .S01_AXI_ARCACHE(4'b0),//input [3 : 0] ; - .S01_AXI_ARPROT(3'b0),//input [2 : 0] ; - .S01_AXI_ARQOS(4'b0),//input [3 : 0] ; - .S01_AXI_ARVALID(S11_AXI_ARVALID),//input ; - .S01_AXI_ARREADY(S11_AXI_ARREADY),//output ; - .S01_AXI_RID(S11_AXI_RID),//output [0 : 0] ; - .S01_AXI_RDATA(S11_AXI_RDATA),//output [511 : 0] ; - .S01_AXI_RRESP(S11_AXI_RRESP),//output [1 : 0] ; - .S01_AXI_RLAST(S11_AXI_RLAST),//output ; - .S01_AXI_RVALID(S11_AXI_RVALID),//output ; - .S01_AXI_RREADY(S11_AXI_RREADY),//input ; - .M00_AXI_ARESET_OUT_N(),//output ; - .M00_AXI_ACLK(c0_ui_clk),//(clk156_25),//input ; - .M00_AXI_AWID(c0_s_axi_awid),//output [3 : 0] ; - .M00_AXI_AWADDR(c0_s_axi_awaddr[31:0]),//output [31 : 0] ; - .M00_AXI_AWLEN(c0_s_axi_awlen),//output [7 : 0] ; - .M00_AXI_AWSIZE(c0_s_axi_awsize),//output [2 : 0] ; - .M00_AXI_AWBURST(c0_s_axi_awburst),//output [1 : 0] ; - .M00_AXI_AWLOCK(),//output ; - .M00_AXI_AWCACHE(),//output [3 : 0] ; - .M00_AXI_AWPROT(),//output [2 : 0] ; - .M00_AXI_AWQOS(),//output [3 : 0] ; - .M00_AXI_AWVALID(c0_s_axi_awvalid),//output ; - .M00_AXI_AWREADY(c0_s_axi_awready),//input ; - .M00_AXI_WDATA(c0_s_axi_wdata),//output [511 : 0] ; - .M00_AXI_WSTRB(c0_s_axi_wstrb),//output [63 : 0] ; - .M00_AXI_WLAST(c0_s_axi_wlast),//output ; - .M00_AXI_WVALID(c0_s_axi_wvalid),//output ; - .M00_AXI_WREADY(c0_s_axi_wready),//input ; - .M00_AXI_BID({3'b0,c0_s_axi_bid}),//input [3 : 0] ; - .M00_AXI_BRESP(c0_s_axi_bresp),//input [1 : 0] ; - .M00_AXI_BVALID(c0_s_axi_bvalid),//input ; - .M00_AXI_BREADY(c0_s_axi_bready),//output ; - .M00_AXI_ARID(c0_s_axi_arid_x),//output [3 : 0] ; - .M00_AXI_ARADDR(c0_s_axi_araddr[31:0]),//output [31 : 0] ; - .M00_AXI_ARLEN(c0_s_axi_arlen),//output [7 : 0] ; - .M00_AXI_ARSIZE(c0_s_axi_arsize),//output [2 : 0] ; - .M00_AXI_ARBURST(c0_s_axi_arburst),//output [1 : 0] ; - .M00_AXI_ARLOCK(),//output ; - .M00_AXI_ARCACHE(),//output [3 : 0] ; - .M00_AXI_ARPROT(),//output [2 : 0] ; - .M00_AXI_ARQOS(),//output [3 : 0] ; - .M00_AXI_ARVALID(c0_s_axi_arvalid),//output ; - .M00_AXI_ARREADY(c0_s_axi_arready),//input ; - .M00_AXI_RID({3'b0, c0_s_axi_rid}),//input [3 : 0] ; - .M00_AXI_RDATA(c0_s_axi_rdata),//input [511 : 0] ; - .M00_AXI_RRESP(c0_s_axi_rresp),//input [1 : 0] ; - .M00_AXI_RLAST(c0_s_axi_rlast),//input ; - .M00_AXI_RVALID(c0_s_axi_rvalid),//input ; - .M00_AXI_RREADY(c0_s_axi_rready)//output ; - ); - - //convert 512-bit AXI full to 64-bit AXI stream - axi_datamover_0 toeTX_data_mover0 ( - .m_axi_mm2s_aclk(clk156_25), // input m_axi_mm2s_aclk - .m_axi_mm2s_aresetn(reset156_25_n), // input m_axi_mm2s_aresetn - .mm2s_err(), // output mm2s_err - .m_axis_mm2s_cmdsts_aclk(clk156_25), // input m_axis_mm2s_cmdsts_aclk - .m_axis_mm2s_cmdsts_aresetn(reset156_25_n), // input m_axis_mm2s_cmdsts_aresetn - // mm2s => read - .s_axis_mm2s_cmd_tvalid(toeTX_s_axis_read_cmd_tvalid), // input s_axis_mm2s_cmd_tvalid - .s_axis_mm2s_cmd_tready(toeTX_s_axis_read_cmd_tready), // output s_axis_mm2s_cmd_tready - .s_axis_mm2s_cmd_tdata(toeTX_s_axis_read_cmd_tdata), // input [71 : 0] s_axis_mm2s_cmd_tdata - .m_axis_mm2s_sts_tvalid(toeTX_m_axis_read_sts_tvalid), // output m_axis_mm2s_sts_tvalid - .m_axis_mm2s_sts_tready(toeTX_m_axis_read_sts_tready), // input m_axis_mm2s_sts_tready - .m_axis_mm2s_sts_tdata(toeTX_m_axis_read_sts_tdata), // output [7 : 0] m_axis_mm2s_sts_tdata - .m_axis_mm2s_sts_tkeep(), // output [0 : 0] m_axis_mm2s_sts_tkeep - .m_axis_mm2s_sts_tlast(), // output m_axis_mm2s_sts_tlast - .m_axi_mm2s_arid(S10_AXI_ARID_x), // output [3 : 0] m_axi_mm2s_arid - .m_axi_mm2s_araddr(S10_AXI_ARADDR), // output [31 : 0] m_axi_mm2s_araddr - .m_axi_mm2s_arlen(S10_AXI_ARLEN), // output [7 : 0] m_axi_mm2s_arlen - .m_axi_mm2s_arsize(S10_AXI_ARSIZE), // output [2 : 0] m_axi_mm2s_arsize - .m_axi_mm2s_arburst(S10_AXI_ARBURST), // output [1 : 0] m_axi_mm2s_arburst - .m_axi_mm2s_arprot(), // output [2 : 0] m_axi_mm2s_arprot - .m_axi_mm2s_arcache(), // output [3 : 0] m_axi_mm2s_arcache - .m_axi_mm2s_aruser(), // output [3 : 0] m_axi_mm2s_aruser - .m_axi_mm2s_arvalid(S10_AXI_ARVALID), // output m_axi_mm2s_arvalid - .m_axi_mm2s_arready(S10_AXI_ARREADY), // input m_axi_mm2s_arready - .m_axi_mm2s_rdata(S10_AXI_RDATA), // input [511 : 0] m_axi_mm2s_rdata - .m_axi_mm2s_rresp(S10_AXI_RRESP), // input [1 : 0] m_axi_mm2s_rresp - .m_axi_mm2s_rlast(S10_AXI_RLAST), // input m_axi_mm2s_rlast - .m_axi_mm2s_rvalid(S10_AXI_RVALID), // input m_axi_mm2s_rvalid - .m_axi_mm2s_rready(S10_AXI_RREADY), // output m_axi_mm2s_rready - // read output to app - .m_axis_mm2s_tdata(toeTX_m_axis_read_tdata), // output [63 : 0] m_axis_mm2s_tdata - .m_axis_mm2s_tkeep(toeTX_m_axis_read_tkeep), // output [7 : 0] m_axis_mm2s_tkeep - .m_axis_mm2s_tlast(toeTX_m_axis_read_tlast), // output m_axis_mm2s_tlast - .m_axis_mm2s_tvalid(toeTX_m_axis_read_tvalid), // output m_axis_mm2s_tvalid - .m_axis_mm2s_tready(toeTX_m_axis_read_tready), // input m_axis_mm2s_tready - .m_axi_s2mm_aclk(clk156_25), // input m_axi_s2mm_aclk - .m_axi_s2mm_aresetn(reset156_25_n), // input m_axi_s2mm_aresetn - .s2mm_err(), // output s2mm_err - .m_axis_s2mm_cmdsts_awclk(clk156_25), // input m_axis_s2mm_cmdsts_awclk - .m_axis_s2mm_cmdsts_aresetn(reset156_25_n), // input m_axis_s2mm_cmdsts_aresetn - // s2mm => write - .s_axis_s2mm_cmd_tvalid(toeTX_s_axis_write_cmd_tvalid), // input s_axis_s2mm_cmd_tvalid - .s_axis_s2mm_cmd_tready(toeTX_s_axis_write_cmd_tready), // output s_axis_s2mm_cmd_tready - .s_axis_s2mm_cmd_tdata(toeTX_s_axis_write_cmd_tdata), // input [71 : 0] s_axis_s2mm_cmd_tdata - .m_axis_s2mm_sts_tvalid(toeTX_m_axis_write_sts_tvalid), // output m_axis_s2mm_sts_tvalid - .m_axis_s2mm_sts_tready(toeTX_m_axis_write_sts_tready), // input m_axis_s2mm_sts_tready - .m_axis_s2mm_sts_tdata(toeTX_m_axis_write_sts_tdata), // OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axis_s2mm_sts_tkeep(), // output [0 : 0] m_axis_s2mm_sts_tkeep - .m_axis_s2mm_sts_tlast(), // output m_axis_s2mm_sts_tlast - .m_axi_s2mm_awid(S10_AXI_AWID_x), // output [3 : 0] m_axi_s2mm_awid - .m_axi_s2mm_awaddr(S10_AXI_AWADDR), // output [31 : 0] m_axi_s2mm_awaddr - .m_axi_s2mm_awlen(S10_AXI_AWLEN), // output [7 : 0] m_axi_s2mm_awlen - .m_axi_s2mm_awsize(S10_AXI_AWSIZE), // output [2 : 0] m_axi_s2mm_awsize - .m_axi_s2mm_awburst(S10_AXI_AWBURST), // output [1 : 0] m_axi_s2mm_awburst - .m_axi_s2mm_awprot(), // output [2 : 0] m_axi_s2mm_awprot - .m_axi_s2mm_awcache(), // output [3 : 0] m_axi_s2mm_awcache - .m_axi_s2mm_awuser(), // output [3 : 0] m_axi_s2mm_awuser - .m_axi_s2mm_awvalid(S10_AXI_AWVALID), // output m_axi_s2mm_awvalid - .m_axi_s2mm_awready(S10_AXI_AWREADY), // input m_axi_s2mm_awready - .m_axi_s2mm_wdata(S10_AXI_WDATA), // output [511 : 0] m_axi_s2mm_wdata - .m_axi_s2mm_wstrb(S10_AXI_WSTRB), // output [63 : 0] m_axi_s2mm_wstrb - .m_axi_s2mm_wlast(S10_AXI_WLAST), // output m_axi_s2mm_wlast - .m_axi_s2mm_wvalid(S10_AXI_WVALID), // output m_axi_s2mm_wvalid - .m_axi_s2mm_wready(S10_AXI_WREADY), // input m_axi_s2mm_wready - .m_axi_s2mm_bresp(S10_AXI_BRESP), // input [1 : 0] m_axi_s2mm_bresp - .m_axi_s2mm_bvalid(S10_AXI_BVALID), // input m_axi_s2mm_bvalid - .m_axi_s2mm_bready(S10_AXI_BREADY), // output m_axi_s2mm_bready - // write input from tcp - .s_axis_s2mm_tdata(toeTX_s_axis_write_tdata), // input [63 : 0] s_axis_s2mm_tdata - .s_axis_s2mm_tkeep(toeTX_s_axis_write_tkeep), // input [7 : 0] s_axis_s2mm_tkeep - .s_axis_s2mm_tlast(toeTX_s_axis_write_tlast), // input s_axis_s2mm_tlast - .s_axis_s2mm_tvalid(toeTX_s_axis_write_tvalid), // input s_axis_s2mm_tvalid - .s_axis_s2mm_tready(toeTX_s_axis_write_tready) // output s_axis_s2mm_tready -); - -//convert 512-bit AXI full to 64-bit AXI stream -axi_datamover_0 toeRX_data_mover0 ( - .m_axi_mm2s_aclk(clk156_25), // input m_axi_mm2s_aclk - .m_axi_mm2s_aresetn(reset156_25_n), // input m_axi_mm2s_aresetn - .mm2s_err(), // output mm2s_err - .m_axis_mm2s_cmdsts_aclk(clk156_25), // input m_axis_mm2s_cmdsts_aclk - .m_axis_mm2s_cmdsts_aresetn(reset156_25_n), // input m_axis_mm2s_cmdsts_aresetn - // mm2s => read - .s_axis_mm2s_cmd_tvalid(toeRX_s_axis_read_cmd_tvalid), // input s_axis_mm2s_cmd_tvalid - .s_axis_mm2s_cmd_tready(toeRX_s_axis_read_cmd_tready), // output s_axis_mm2s_cmd_tready - .s_axis_mm2s_cmd_tdata(toeRX_s_axis_read_cmd_tdata), // input [71 : 0] s_axis_mm2s_cmd_tdata - .m_axis_mm2s_sts_tvalid(toeRX_m_axis_read_sts_tvalid), // output m_axis_mm2s_sts_tvalid - .m_axis_mm2s_sts_tready(toeRX_m_axis_read_sts_tready), // input m_axis_mm2s_sts_tready - .m_axis_mm2s_sts_tdata(toeRX_m_axis_read_sts_tdata), // output [7 : 0] m_axis_mm2s_sts_tdata - .m_axis_mm2s_sts_tkeep(), // output [0 : 0] m_axis_mm2s_sts_tkeep - .m_axis_mm2s_sts_tlast(), // output m_axis_mm2s_sts_tlast - .m_axi_mm2s_arid(S11_AXI_ARID_x), // output [3 : 0] m_axi_mm2s_arid - .m_axi_mm2s_araddr(S11_AXI_ARADDR), // output [31 : 0] m_axi_mm2s_araddr - .m_axi_mm2s_arlen(S11_AXI_ARLEN), // output [7 : 0] m_axi_mm2s_arlen - .m_axi_mm2s_arsize(S11_AXI_ARSIZE), // output [2 : 0] m_axi_mm2s_arsize - .m_axi_mm2s_arburst(S11_AXI_ARBURST), // output [1 : 0] m_axi_mm2s_arburst - .m_axi_mm2s_arprot(), // output [2 : 0] m_axi_mm2s_arprot - .m_axi_mm2s_arcache(), // output [3 : 0] m_axi_mm2s_arcache - .m_axi_mm2s_aruser(), // output [3 : 0] m_axi_mm2s_aruser - .m_axi_mm2s_arvalid(S11_AXI_ARVALID), // output m_axi_mm2s_arvalid - .m_axi_mm2s_arready(S11_AXI_ARREADY), // input m_axi_mm2s_arready - .m_axi_mm2s_rdata(S11_AXI_RDATA), // input [511 : 0] m_axi_mm2s_rdata - .m_axi_mm2s_rresp(S11_AXI_RRESP), // input [1 : 0] m_axi_mm2s_rresp - .m_axi_mm2s_rlast(S11_AXI_RLAST), // input m_axi_mm2s_rlast - .m_axi_mm2s_rvalid(S11_AXI_RVALID), // input m_axi_mm2s_rvalid - .m_axi_mm2s_rready(S11_AXI_RREADY), // output m_axi_mm2s_rready - // read output to app - .m_axis_mm2s_tdata(toeRX_m_axis_read_tdata), // output [63 : 0] m_axis_mm2s_tdata - .m_axis_mm2s_tkeep(toeRX_m_axis_read_tkeep), // output [7 : 0] m_axis_mm2s_tkeep - .m_axis_mm2s_tlast(toeRX_m_axis_read_tlast), // output m_axis_mm2s_tlast - .m_axis_mm2s_tvalid(toeRX_m_axis_read_tvalid), // output m_axis_mm2s_tvalid - .m_axis_mm2s_tready(toeRX_m_axis_read_tready), // input m_axis_mm2s_tready - .m_axi_s2mm_aclk(clk156_25), // input m_axi_s2mm_aclk - .m_axi_s2mm_aresetn(reset156_25_n), // input m_axi_s2mm_aresetn - .s2mm_err(), // output s2mm_err - .m_axis_s2mm_cmdsts_awclk(clk156_25), // input m_axis_s2mm_cmdsts_awclk - .m_axis_s2mm_cmdsts_aresetn(reset156_25_n), // input m_axis_s2mm_cmdsts_aresetn - // s2mm => write - .s_axis_s2mm_cmd_tvalid(toeRX_s_axis_write_cmd_tvalid), // input s_axis_s2mm_cmd_tvalid - .s_axis_s2mm_cmd_tready(toeRX_s_axis_write_cmd_tready), // output s_axis_s2mm_cmd_tready - .s_axis_s2mm_cmd_tdata(toeRX_s_axis_write_cmd_tdata), // input [71 : 0] s_axis_s2mm_cmd_tdata - .m_axis_s2mm_sts_tvalid(toeRX_m_axis_write_sts_tvalid), // output m_axis_s2mm_sts_tvalid - .m_axis_s2mm_sts_tready(toeRX_m_axis_write_sts_tready), // input m_axis_s2mm_sts_tready - .m_axis_s2mm_sts_tdata(toeRX_m_axis_write_sts_tdata), // OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axis_s2mm_sts_tkeep(), // output [0 : 0] m_axis_s2mm_sts_tkeep - .m_axis_s2mm_sts_tlast(), // output m_axis_s2mm_sts_tlast - .m_axi_s2mm_awid(S11_AXI_AWID_x), // output [3 : 0] m_axi_s2mm_awid - .m_axi_s2mm_awaddr(S11_AXI_AWADDR), // output [31 : 0] m_axi_s2mm_awaddr - .m_axi_s2mm_awlen(S11_AXI_AWLEN), // output [7 : 0] m_axi_s2mm_awlen - .m_axi_s2mm_awsize(S11_AXI_AWSIZE), // output [2 : 0] m_axi_s2mm_awsize - .m_axi_s2mm_awburst(S11_AXI_AWBURST), // output [1 : 0] m_axi_s2mm_awburst - .m_axi_s2mm_awprot(), // output [2 : 0] m_axi_s2mm_awprot - .m_axi_s2mm_awcache(), // output [3 : 0] m_axi_s2mm_awcache - .m_axi_s2mm_awuser(), // output [3 : 0] m_axi_s2mm_awuser - .m_axi_s2mm_awvalid(S11_AXI_AWVALID), // output m_axi_s2mm_awvalid - .m_axi_s2mm_awready(S11_AXI_AWREADY), // input m_axi_s2mm_awready - .m_axi_s2mm_wdata(S11_AXI_WDATA), // output [511 : 0] m_axi_s2mm_wdata - .m_axi_s2mm_wstrb(S11_AXI_WSTRB), // output [63 : 0] m_axi_s2mm_wstrb - .m_axi_s2mm_wlast(S11_AXI_WLAST), // output m_axi_s2mm_wlast - .m_axi_s2mm_wvalid(S11_AXI_WVALID), // output m_axi_s2mm_wvalid - .m_axi_s2mm_wready(S11_AXI_WREADY), // input m_axi_s2mm_wready - .m_axi_s2mm_bresp(S11_AXI_BRESP), // input [1 : 0] m_axi_s2mm_bresp - .m_axi_s2mm_bvalid(S11_AXI_BVALID), // input m_axi_s2mm_bvalid - .m_axi_s2mm_bready(S11_AXI_BREADY), // output m_axi_s2mm_bready - // write input from tcp - .s_axis_s2mm_tdata(toeRX_s_axis_write_tdata), // input [63 : 0] s_axis_s2mm_tdata - .s_axis_s2mm_tkeep(toeRX_s_axis_write_tkeep), // input [7 : 0] s_axis_s2mm_tkeep - .s_axis_s2mm_tlast(toeRX_s_axis_write_tlast), // input s_axis_s2mm_tlast - .s_axis_s2mm_tvalid(toeRX_s_axis_write_tvalid), // input s_axis_s2mm_tvalid - .s_axis_s2mm_tready(toeRX_s_axis_write_tready) // output s_axis_s2mm_tready -); - -wire [0 : 0] S00_AXI_AWID; -wire [31 : 0] S00_AXI_AWADDR; -wire [7 : 0] S00_AXI_AWLEN; -wire [2 : 0] S00_AXI_AWSIZE; -wire [1 : 0] S00_AXI_AWBURST; -wire S00_AXI_AWLOCK; -wire [3 : 0] S00_AXI_AWCACHE; -wire [2 : 0] S00_AXI_AWPROT; -wire [3 : 0] S00_AXI_AWQOS; -wire S00_AXI_AWVALID; -wire S00_AXI_AWREADY; -wire [511 : 0] S00_AXI_WDATA; -wire [63 : 0] S00_AXI_WSTRB; -wire S00_AXI_WLAST; -wire S00_AXI_WVALID; -wire S00_AXI_WREADY; -wire [0 : 0] S00_AXI_BID; -wire [1 : 0] S00_AXI_BRESP; -wire S00_AXI_BVALID; -wire S00_AXI_BREADY; -wire [0 : 0] S00_AXI_ARID; -wire [31 : 0] S00_AXI_ARADDR; -wire [7 : 0] S00_AXI_ARLEN; -wire [2 : 0] S00_AXI_ARSIZE; -wire [1 : 0] S00_AXI_ARBURST; -wire S00_AXI_ARLOCK; -wire [3 : 0] S00_AXI_ARCACHE; -wire [2 : 0] S00_AXI_ARPROT; -wire [3 : 0] S00_AXI_ARQOS; -wire S00_AXI_ARVALID; -wire S00_AXI_ARREADY; -wire [0 : 0] S00_AXI_RID; -wire [511 : 0] S00_AXI_RDATA; -wire [1 : 0] S00_AXI_RRESP; -wire S00_AXI_RLAST; -wire S00_AXI_RVALID; -wire S00_AXI_RREADY; -wire S01_AXI_ARESET_OUT_N; -wire S01_AXI_ACLK; -wire [0 : 0] S01_AXI_AWID; -wire [31 : 0] S01_AXI_AWADDR; -wire [7 : 0] S01_AXI_AWLEN; -wire [2 : 0] S01_AXI_AWSIZE; -wire [1 : 0] S01_AXI_AWBURST; -wire S01_AXI_AWLOCK; -wire [3 : 0] S01_AXI_AWCACHE; -wire [2 : 0] S01_AXI_AWPROT; -wire [3 : 0] S01_AXI_AWQOS; -wire S01_AXI_AWVALID; -wire S01_AXI_AWREADY; -wire [511 : 0] S01_AXI_WDATA; -wire [63 : 0] S01_AXI_WSTRB; -wire S01_AXI_WLAST; -wire S01_AXI_WVALID; -wire S01_AXI_WREADY; -wire [0 : 0] S01_AXI_BID; -wire [1 : 0] S01_AXI_BRESP; -wire S01_AXI_BVALID; -wire S01_AXI_BREADY; -wire [0 : 0] S01_AXI_ARID; -wire [31 : 0] S01_AXI_ARADDR; -wire [7 : 0] S01_AXI_ARLEN; -wire [2 : 0] S01_AXI_ARSIZE; -wire [1 : 0] S01_AXI_ARBURST; -wire S01_AXI_ARLOCK; -wire [3 : 0] S01_AXI_ARCACHE; -wire [2 : 0] S01_AXI_ARPROT; -wire [3 : 0] S01_AXI_ARQOS; -wire S01_AXI_ARVALID; -wire S01_AXI_ARREADY; -wire [0 : 0] S01_AXI_RID; -wire [511 : 0] S01_AXI_RDATA; -wire [1 : 0] S01_AXI_RRESP; -wire S01_AXI_RLAST; -wire S01_AXI_RVALID; -wire S01_AXI_RREADY; - -//wire [3:0] c1_m_axi_arid_x; -//assign c1_m_axi_arid = c1_m_axi_arid_x[0]; - -wire [3:0] c1_s_axi_arid_x; -assign c1_s_axi_arid = c1_s_axi_arid_x[0]; - - -axi_interconnect_ip ht_upd_axi_switch ( -.INTERCONNECT_ACLK(clk156_25),//input ; -.INTERCONNECT_ARESETN(reset156_25_n),//input ; -.S00_AXI_ARESET_OUT_N(),//output ; -.S00_AXI_ACLK(clk156_25),//input ; -.S00_AXI_AWID(S00_AXI_AWID),//input [0 : 0] ; -.S00_AXI_AWADDR(S00_AXI_AWADDR),//input [31 : 0] ; -.S00_AXI_AWLEN(S00_AXI_AWLEN),//input [7 : 0] ; -.S00_AXI_AWSIZE(S00_AXI_AWSIZE),//input [2 : 0] ; -.S00_AXI_AWBURST(S00_AXI_AWBURST),//input [1 : 0] ; -.S00_AXI_AWLOCK(1'b0),//input ; -.S00_AXI_AWCACHE(4'b0),//input [3 : 0] ; -.S00_AXI_AWPROT(3'b0),//input [2 : 0] ; -.S00_AXI_AWQOS(4'b0),//input [3 : 0] ; -.S00_AXI_AWVALID(S00_AXI_AWVALID),//input ; -.S00_AXI_AWREADY(S00_AXI_AWREADY),//output ; -.S00_AXI_WDATA(S00_AXI_WDATA),//input [511 : 0] ; -.S00_AXI_WSTRB(S00_AXI_WSTRB),//input [63 : 0] ; -.S00_AXI_WLAST(S00_AXI_WLAST),//input ; -.S00_AXI_WVALID(S00_AXI_WVALID),//input ; -.S00_AXI_WREADY(S00_AXI_WREADY),//output ; -.S00_AXI_BID(S00_AXI_BID),//output [0 : 0] ; -.S00_AXI_BRESP(S00_AXI_BRESP),//output [1 : 0] ; -.S00_AXI_BVALID(S00_AXI_BVALID),//output ; -.S00_AXI_BREADY(S00_AXI_BREADY),//input ; -.S00_AXI_ARID(S00_AXI_ARID),//input [0 : 0] ; -.S00_AXI_ARADDR(S00_AXI_ARADDR),//input [31 : 0] ; -.S00_AXI_ARLEN(S00_AXI_ARLEN),//input [7 : 0] ; -.S00_AXI_ARSIZE(S00_AXI_ARSIZE),//input [2 : 0] ; -.S00_AXI_ARBURST(S00_AXI_ARBURST),//input [1 : 0] ; -.S00_AXI_ARLOCK(1'b0),//input ; -.S00_AXI_ARCACHE(4'b0),//input [3 : 0] ; -.S00_AXI_ARPROT(3'b0),//input [2 : 0] ; -.S00_AXI_ARQOS(4'b0),//input [3 : 0] ; -.S00_AXI_ARVALID(S00_AXI_ARVALID),//input ; -.S00_AXI_ARREADY(S00_AXI_ARREADY),//output ; -.S00_AXI_RID(S00_AXI_RID),//output [0 : 0] ; -.S00_AXI_RDATA(S00_AXI_RDATA),//output [511 : 0] ; -.S00_AXI_RRESP(S00_AXI_RRESP),//output [1 : 0] ; -.S00_AXI_RLAST(S00_AXI_RLAST),//output ; -.S00_AXI_RVALID(S00_AXI_RVALID),//output ; -.S00_AXI_RREADY(S00_AXI_RREADY),//input ; -.S01_AXI_ARESET_OUT_N(S01_AXI_ARESET_OUT_N),//output ; -.S01_AXI_ACLK(clk156_25),//input ; -.S01_AXI_AWID(S01_AXI_AWID),//input [0 : 0] ; -.S01_AXI_AWADDR(S01_AXI_AWADDR),//input [31 : 0] ; -.S01_AXI_AWLEN(S01_AXI_AWLEN),//input [7 : 0] ; -.S01_AXI_AWSIZE(S01_AXI_AWSIZE),//input [2 : 0] ; -.S01_AXI_AWBURST(S01_AXI_AWBURST),//input [1 : 0] ; -.S01_AXI_AWLOCK(1'b0),//input ; -.S01_AXI_AWCACHE(4'b0),//input [3 : 0] ; -.S01_AXI_AWPROT(3'b0),//input [2 : 0] ; -.S01_AXI_AWQOS(4'b0),//input [3 : 0] ; -.S01_AXI_AWVALID(S01_AXI_AWVALID),//input ; -.S01_AXI_AWREADY(S01_AXI_AWREADY),//output ; -.S01_AXI_WDATA(S01_AXI_WDATA),//input [511 : 0] ; -.S01_AXI_WSTRB(S01_AXI_WSTRB),//input [63 : 0] ; -.S01_AXI_WLAST(S01_AXI_WLAST),//input ; -.S01_AXI_WVALID(S01_AXI_WVALID),//input ; -.S01_AXI_WREADY(S01_AXI_WREADY),//output ; -.S01_AXI_BID(S01_AXI_BID),//output [0 : 0] ; -.S01_AXI_BRESP(S01_AXI_BRESP),//output [1 : 0] ; -.S01_AXI_BVALID(S01_AXI_BVALID),//output ; -.S01_AXI_BREADY(S01_AXI_BREADY),//input ; -.S01_AXI_ARID(S01_AXI_ARID),//input [0 : 0] ; -.S01_AXI_ARADDR(S01_AXI_ARADDR),//input [31 : 0] ; -.S01_AXI_ARLEN(S01_AXI_ARLEN),//input [7 : 0] ; -.S01_AXI_ARSIZE(S01_AXI_ARSIZE),//input [2 : 0] ; -.S01_AXI_ARBURST(S01_AXI_ARBURST),//input [1 : 0] ; -.S01_AXI_ARLOCK(1'b0),//input ; -.S01_AXI_ARCACHE(4'b0),//input [3 : 0] ; -.S01_AXI_ARPROT(3'b0),//input [2 : 0] ; -.S01_AXI_ARQOS(4'b0),//input [3 : 0] ; -.S01_AXI_ARVALID(S01_AXI_ARVALID),//input ; -.S01_AXI_ARREADY(S01_AXI_ARREADY),//output ; -.S01_AXI_RID(S01_AXI_RID),//output [0 : 0] ; -.S01_AXI_RDATA(S01_AXI_RDATA),//output [511 : 0] ; -.S01_AXI_RRESP(S01_AXI_RRESP),//output [1 : 0] ; -.S01_AXI_RLAST(S01_AXI_RLAST),//output ; -.S01_AXI_RVALID(S01_AXI_RVALID),//output ; -.S01_AXI_RREADY(S01_AXI_RREADY),//input ; -.M00_AXI_ARESET_OUT_N(),//output ; -.M00_AXI_ACLK(c1_ui_clk),//(clk156_25),//input ; -.M00_AXI_AWID(c1_s_axi_awid),//output [3 : 0] ; -.M00_AXI_AWADDR(c1_s_axi_awaddr),//output [31 : 0] ; -.M00_AXI_AWLEN(c1_s_axi_awlen),//output [7 : 0] ; -.M00_AXI_AWSIZE(c1_s_axi_awsize),//output [2 : 0] ; -.M00_AXI_AWBURST(c1_s_axi_awburst),//output [1 : 0] ; -.M00_AXI_AWLOCK(),//output ; -.M00_AXI_AWCACHE(),//output [3 : 0] ; -.M00_AXI_AWPROT(),//output [2 : 0] ; -.M00_AXI_AWQOS(),//output [3 : 0] ; -.M00_AXI_AWVALID(c1_s_axi_awvalid),//output ; -.M00_AXI_AWREADY(c1_s_axi_awready),//input ; -.M00_AXI_WDATA(c1_s_axi_wdata),//output [511 : 0] ; -.M00_AXI_WSTRB(c1_s_axi_wstrb),//output [63 : 0] ; -.M00_AXI_WLAST(c1_s_axi_wlast),//output ; -.M00_AXI_WVALID(c1_s_axi_wvalid),//output ; -.M00_AXI_WREADY(c1_s_axi_wready),//input ; -.M00_AXI_BID({3'b0,c1_s_axi_bid}),//input [3 : 0] ; -.M00_AXI_BRESP(c1_s_axi_bresp),//input [1 : 0] ; -.M00_AXI_BVALID(c1_s_axi_bvalid),//input ; -.M00_AXI_BREADY(c1_s_axi_bready),//output ; -.M00_AXI_ARID(c1_s_axi_arid_x),//output [3 : 0] ; -.M00_AXI_ARADDR(c1_s_axi_araddr),//output [31 : 0] ; -.M00_AXI_ARLEN(c1_s_axi_arlen),//output [7 : 0] ; -.M00_AXI_ARSIZE(c1_s_axi_arsize),//output [2 : 0] ; -.M00_AXI_ARBURST(c1_s_axi_arburst),//output [1 : 0] ; -.M00_AXI_ARLOCK(),//output ; -.M00_AXI_ARCACHE(),//output [3 : 0] ; -.M00_AXI_ARPROT(),//output [2 : 0] ; -.M00_AXI_ARQOS(),//output [3 : 0] ; -.M00_AXI_ARVALID(c1_s_axi_arvalid),//output ; -.M00_AXI_ARREADY(c1_s_axi_arready),//input ; -.M00_AXI_RID({3'b0, c1_s_axi_rid}),//input [3 : 0] ; -.M00_AXI_RDATA(c1_s_axi_rdata),//input [511 : 0] ; -.M00_AXI_RRESP(c1_s_axi_rresp),//input [1 : 0] ; -.M00_AXI_RLAST(c1_s_axi_rlast),//input ; -.M00_AXI_RVALID(c1_s_axi_rvalid),//input ; -.M00_AXI_RREADY(c1_s_axi_rready)//output ; -); - -wire [3:0] S00_AXI_ARID_x, S00_AXI_AWID_x; -assign S00_AXI_ARID = S00_AXI_ARID_x[0]; -assign S00_AXI_AWID = S00_AXI_AWID_x[0]; -//data movers between ht and upd axi streams and S00, S01 axi full interfaces -axi_datamover_1 ht_data_mover ( - .m_axi_mm2s_aclk(clk156_25),// : IN STD_LOGIC; - .m_axi_mm2s_aresetn(reset156_25_n), //: IN STD_LOGIC; - .mm2s_err(), //: OUT STD_LOGIC; +axis_data_fifo_64_cc axis_write_data_fifo_mem1 ( + .s_axis_aclk(clk156_25), // input wire s_axis_aclk + .s_axis_aresetn(reset156_25_n), // input wire s_axis_aresetn + .s_axis_tvalid(s_axis_mem1_write_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_mem1_write_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_mem1_write_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(s_axis_mem1_write_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(s_axis_mem1_write_tlast), // input wire s_axis_tlast + + .m_axis_aclk(c1_ui_clk), // input wire m_axis_aclk + .m_axis_aresetn(c1_aresetn_r), // input wire m_axis_aresetn + .m_axis_tvalid(axis_mem1_cc_to_dm_write_tvalid), // output wire m_axis_tvalid + .m_axis_tready(axis_mem1_cc_to_dm_write_tready), // input wire m_axis_tready + .m_axis_tdata(axis_mem1_cc_to_dm_write_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(axis_mem1_cc_to_dm_write_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(axis_mem1_cc_to_dm_write_tlast), // output wire m_axis_tlast + + .axis_data_count(), // output wire [31 : 0] axis_data_count + .axis_wr_data_count(), // output wire [31 : 0] axis_wr_data_count + .axis_rd_data_count() // output wire [31 : 0] axis_rd_data_count + ); + +axis_data_fifo_64_cc axis_read_data_fifo_mem1 ( + .s_axis_aclk(c1_ui_clk), // input wire s_axis_aclk + .s_axis_aresetn(c1_aresetn_r), // input wire s_axis_aresetn + .s_axis_tvalid(axis_mem1_dm_to_cc_read_tvalid), // input wire s_axis_tvalid + .s_axis_tready(axis_mem1_dm_to_cc_read_tready), // output wire s_axis_tready + .s_axis_tdata(axis_mem1_dm_to_cc_read_tdata), // input wire [255 : 0] s_axis_tdata + .s_axis_tkeep(axis_mem1_dm_to_cc_read_tkeep), // input wire [31 : 0] s_axis_tkeep + .s_axis_tlast(axis_mem1_dm_to_cc_read_tlast), // input wire s_axis_tlast + + .m_axis_aclk(clk156_25), // input wire m_axis_aclk + .m_axis_aresetn(reset156_25_n), // input wire m_axis_aresetn + .m_axis_tvalid(m_axis_mem1_read_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_mem1_read_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_mem1_read_tdata), // output wire [255 : 0] m_axis_tdata + .m_axis_tkeep(m_axis_mem1_read_tkeep), // output wire [31 : 0] m_axis_tkeep + .m_axis_tlast(m_axis_mem1_read_tlast), // output wire m_axis_tlast + + .axis_data_count(), // output wire [31 : 0] axis_data_count + .axis_wr_data_count(), // output wire [31 : 0] axis_wr_data_count + .axis_rd_data_count() // output wire [31 : 0] axis_rd_data_count + ); + end + else begin + assign s_axis_mem1_write_tready = 1'b1; + assign m_axis_mem1_read_tvalid = 1'b0; + end +endgenerate +/* + * DATA MOVERS + */ + + +generate + if (ENABLE_DDR0 == 1) begin +wire m0_s2mm_err; +wire m0_mm2s_err; + +axi_datamover_64_to_512 datamover_m0 ( + .m_axi_mm2s_aclk(c0_ui_clk),// : IN STD_LOGIC; + .m_axi_mm2s_aresetn(c0_aresetn_r), //: IN STD_LOGIC; + .mm2s_err(m0_mm2s_err), //: OUT STD_LOGIC; .m_axis_mm2s_cmdsts_aclk(clk156_25), //: IN STD_LOGIC; .m_axis_mm2s_cmdsts_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s_axis_mm2s_cmd_tvalid(ht_s_axis_read_cmd_tvalid), //: IN STD_LOGIC; - .s_axis_mm2s_cmd_tready(ht_s_axis_read_cmd_tready), //: OUT STD_LOGIC; - .s_axis_mm2s_cmd_tdata(ht_s_axis_read_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); - .m_axis_mm2s_sts_tvalid(ht_m_axis_read_sts_tvalid), //: OUT STD_LOGIC; - .m_axis_mm2s_sts_tready(ht_m_axis_read_sts_tready), //: IN STD_LOGIC; - .m_axis_mm2s_sts_tdata(ht_m_axis_read_sts_tdata), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .s_axis_mm2s_cmd_tvalid(s_axis_mem0_read_cmd_tvalid), //: IN STD_LOGIC; + .s_axis_mm2s_cmd_tready(s_axis_mem0_read_cmd_tready), //: OUT STD_LOGIC; + .s_axis_mm2s_cmd_tdata(s_axis_mem0_read_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); + .m_axis_mm2s_sts_tvalid(m_axis_mem0_read_sts_tvalid), //: OUT STD_LOGIC; + .m_axis_mm2s_sts_tready(m_axis_mem0_read_sts_tready), //: IN STD_LOGIC; + .m_axis_mm2s_sts_tdata(m_axis_mem0_read_sts_tdata), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); .m_axis_mm2s_sts_tkeep(), //: OUT STD_LOGIC_VECTOR(0 DOWNTO 0); .m_axis_mm2s_sts_tlast(), //: OUT STD_LOGIC; - .m_axi_mm2s_arid(S00_AXI_ARID_x), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_mm2s_araddr(S00_AXI_ARADDR), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axi_mm2s_arlen(S00_AXI_ARLEN), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - .m_axi_mm2s_arsize(S00_AXI_ARSIZE), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_mm2s_arburst(S00_AXI_ARBURST), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_mm2s_arprot(), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_mm2s_arcache(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_mm2s_arid(c0_s_axi_arid), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_mm2s_araddr(c0_s_axi_araddr), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axi_mm2s_arlen(c0_s_axi_arlen), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .m_axi_mm2s_arsize(c0_s_axi_arsize), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_mm2s_arburst(c0_s_axi_arburst), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_mm2s_arprot(c0_s_axi_arprot), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_mm2s_arcache(c0_s_axi_arcache), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axi_mm2s_aruser(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_mm2s_arvalid(S00_AXI_ARVALID), //: OUT STD_LOGIC; - .m_axi_mm2s_arready(S00_AXI_ARREADY), //: IN STD_LOGIC; - .m_axi_mm2s_rdata(S00_AXI_RDATA), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axi_mm2s_rresp(S00_AXI_RRESP), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_mm2s_rlast(S00_AXI_RLAST), //: IN STD_LOGIC; - .m_axi_mm2s_rvalid(S00_AXI_RVALID), //: IN STD_LOGIC; - .m_axi_mm2s_rready(S00_AXI_RREADY), //: OUT STD_LOGIC; - .m_axis_mm2s_tdata(ht_m_axis_read_tdata), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axis_mm2s_tkeep(ht_m_axis_read_tkeep), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - .m_axis_mm2s_tlast(ht_m_axis_read_tlast), //: OUT STD_LOGIC; - .m_axis_mm2s_tvalid(ht_m_axis_read_tvalid), //: OUT STD_LOGIC; - .m_axis_mm2s_tready(ht_m_axis_read_tready), //: IN STD_LOGIC; - .m_axi_s2mm_aclk(clk156_25), //: IN STD_LOGIC; - .m_axi_s2mm_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s2mm_err(), //: OUT STD_LOGIC; + .m_axi_mm2s_arvalid(c0_s_axi_arvalid), //: OUT STD_LOGIC; + .m_axi_mm2s_arready(c0_s_axi_arready), //: IN STD_LOGIC; + .m_axi_mm2s_rdata(c0_s_axi_rdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); + .m_axi_mm2s_rresp(c0_s_axi_rresp), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_mm2s_rlast(c0_s_axi_rlast), //: IN STD_LOGIC; + .m_axi_mm2s_rvalid(c0_s_axi_rvalid), //: IN STD_LOGIC; + .m_axi_mm2s_rready(c0_s_axi_rready), //: OUT STD_LOGIC; + .m_axis_mm2s_tdata(axis_mem0_dm_to_cc_read_tdata), //: OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + .m_axis_mm2s_tkeep(axis_mem0_dm_to_cc_read_tkeep), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axis_mm2s_tlast(axis_mem0_dm_to_cc_read_tlast), //: OUT STD_LOGIC; + .m_axis_mm2s_tvalid(axis_mem0_dm_to_cc_read_tvalid), //: OUT STD_LOGIC; + .m_axis_mm2s_tready(axis_mem0_dm_to_cc_read_tready), //: IN STD_LOGIC; + .m_axi_s2mm_aclk(c0_ui_clk), //: IN STD_LOGIC; + .m_axi_s2mm_aresetn(c0_aresetn_r), //: IN STD_LOGIC; + .s2mm_err(m0_s2mm_err), //: OUT STD_LOGIC; .m_axis_s2mm_cmdsts_awclk(clk156_25), //: IN STD_LOGIC; .m_axis_s2mm_cmdsts_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s_axis_s2mm_cmd_tvalid(ht_s_axis_write_cmd_tvalid), //: IN STD_LOGIC; - .s_axis_s2mm_cmd_tready(ht_s_axis_write_cmd_tready), //: OUT STD_LOGIC; - .s_axis_s2mm_cmd_tdata(ht_s_axis_write_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); - .m_axis_s2mm_sts_tvalid(ht_m_axis_write_sts_tvalid), //: OUT STD_LOGIC; - .m_axis_s2mm_sts_tready(ht_m_axis_write_sts_tready), //: IN STD_LOGIC; - .m_axis_s2mm_sts_tdata(ht_m_axis_write_sts_tdata), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .s_axis_s2mm_cmd_tvalid(s_axis_mem0_write_cmd_tvalid), //: IN STD_LOGIC; + .s_axis_s2mm_cmd_tready(s_axis_mem0_write_cmd_tready), //: OUT STD_LOGIC; + .s_axis_s2mm_cmd_tdata(s_axis_mem0_write_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); + .m_axis_s2mm_sts_tvalid(m_axis_mem0_write_sts_tvalid), //: OUT STD_LOGIC; + .m_axis_s2mm_sts_tready(m_axis_mem0_write_sts_tready), //: IN STD_LOGIC; + .m_axis_s2mm_sts_tdata(m_axis_mem0_write_sts_tdata), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); .m_axis_s2mm_sts_tkeep(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axis_s2mm_sts_tlast(), //: OUT STD_LOGIC; - .m_axi_s2mm_awid(S00_AXI_AWID_x), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_s2mm_awaddr(S00_AXI_AWADDR), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axi_s2mm_awlen(S00_AXI_AWLEN), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - .m_axi_s2mm_awsize(S00_AXI_AWSIZE), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_s2mm_awburst(S00_AXI_AWBURST), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_s2mm_awprot(), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_s2mm_awcache(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_s2mm_awid(c0_s_axi_awid), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_s2mm_awaddr(c0_s_axi_awaddr), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axi_s2mm_awlen(c0_s_axi_awlen), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .m_axi_s2mm_awsize(c0_s_axi_awsize), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_s2mm_awburst(c0_s_axi_awburst), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_s2mm_awprot(c0_s_axi_awprot), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_s2mm_awcache(c0_s_axi_awcache), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axi_s2mm_awuser(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_s2mm_awvalid(S00_AXI_AWVALID), //: OUT STD_LOGIC; - .m_axi_s2mm_awready(S00_AXI_AWREADY), //: IN STD_LOGIC; - .m_axi_s2mm_wdata(S00_AXI_WDATA), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axi_s2mm_wstrb(S00_AXI_WSTRB), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - .m_axi_s2mm_wlast(S00_AXI_WLAST), //: OUT STD_LOGIC; - .m_axi_s2mm_wvalid(S00_AXI_WVALID), //: OUT STD_LOGIC; - .m_axi_s2mm_wready(S00_AXI_WREADY), //: IN STD_LOGIC; - .m_axi_s2mm_bresp(S00_AXI_BRESP), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_s2mm_bvalid(S00_AXI_BVALID), //: IN STD_LOGIC; - .m_axi_s2mm_bready(S00_AXI_BREADY), //: OUT STD_LOGIC; - .s_axis_s2mm_tdata(ht_s_axis_write_tdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); - .s_axis_s2mm_tkeep(ht_s_axis_write_tkeep), //: IN STD_LOGIC_VECTOR(63 DOWNTO 0); - .s_axis_s2mm_tlast(ht_s_axis_write_tlast), //: IN STD_LOGIC; - .s_axis_s2mm_tvalid(ht_s_axis_write_tvalid), //: IN STD_LOGIC; - .s_axis_s2mm_tready(ht_s_axis_write_tready) //: OUT STD_LOGIC; + .m_axi_s2mm_awvalid(c0_s_axi_awvalid), //: OUT STD_LOGIC; + .m_axi_s2mm_awready(c0_s_axi_awready), //: IN STD_LOGIC; + .m_axi_s2mm_wdata(c0_s_axi_wdata), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + .m_axi_s2mm_wstrb(c0_s_axi_wstrb), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + .m_axi_s2mm_wlast(c0_s_axi_wlast), //: OUT STD_LOGIC; + .m_axi_s2mm_wvalid(c0_s_axi_wvalid), //: OUT STD_LOGIC; + .m_axi_s2mm_wready(c0_s_axi_wready), //: IN STD_LOGIC; + .m_axi_s2mm_bresp(c0_s_axi_bresp), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_s2mm_bvalid(c0_s_axi_bvalid), //: IN STD_LOGIC; + .m_axi_s2mm_bready(c0_s_axi_bready), //: OUT STD_LOGIC; + .s_axis_s2mm_tdata(axis_mem0_cc_to_dm_write_tdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); + .s_axis_s2mm_tkeep(axis_mem0_cc_to_dm_write_tkeep), //: IN STD_LOGIC_VECTOR(63 DOWNTO 0); + .s_axis_s2mm_tlast(axis_mem0_cc_to_dm_write_tlast), //: IN STD_LOGIC; + .s_axis_s2mm_tvalid(axis_mem0_cc_to_dm_write_tvalid), //: IN STD_LOGIC; + .s_axis_s2mm_tready(axis_mem0_cc_to_dm_write_tready) //: OUT STD_LOGIC; ); + end +else begin + assign s_axis_mem0_read_cmd_tready = 1'b1; + assign m_axis_mem0_read_sts_tvalid = 1'b0; + assign s_axis_mem0_write_cmd_tready = 1'b1; + assign m_axis_mem0_write_sts_tvalid = 1'b0; +end +endgenerate + -wire [3:0] S01_AXI_ARID_x, S01_AXI_AWID_x; -assign S01_AXI_ARID = S01_AXI_ARID_x[0]; -assign S01_AXI_AWID = S01_AXI_AWID_x[0]; -axi_datamover_1 upd_data_mover ( - .m_axi_mm2s_aclk(clk156_25),// : IN STD_LOGIC; - .m_axi_mm2s_aresetn(reset156_25_n), //: IN STD_LOGIC; - .mm2s_err(), //: OUT STD_LOGIC; +generate + if (ENABLE_DDR1 == 1) begin +wire m1_s2mm_err; +wire m1_mm2s_err; + + +axi_datamover_64_to_512 datamover_m1 ( + .m_axi_mm2s_aclk(c1_ui_clk),// : IN STD_LOGIC; + .m_axi_mm2s_aresetn(c1_aresetn_r), //: IN STD_LOGIC; + .mm2s_err(m1_mm2s_err), //: OUT STD_LOGIC; .m_axis_mm2s_cmdsts_aclk(clk156_25), //: IN STD_LOGIC; .m_axis_mm2s_cmdsts_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s_axis_mm2s_cmd_tvalid(upd_s_axis_read_cmd_tvalid), //: IN STD_LOGIC; - .s_axis_mm2s_cmd_tready(upd_s_axis_read_cmd_tready), //: OUT STD_LOGIC; - .s_axis_mm2s_cmd_tdata(upd_s_axis_read_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); - .m_axis_mm2s_sts_tvalid(upd_m_axis_read_sts_tvalid), //: OUT STD_LOGIC; - .m_axis_mm2s_sts_tready(upd_m_axis_read_sts_tready), //: IN STD_LOGIC; - .m_axis_mm2s_sts_tdata(upd_m_axis_read_sts_tdata), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .s_axis_mm2s_cmd_tvalid(s_axis_mem1_read_cmd_tvalid), //: IN STD_LOGIC; + .s_axis_mm2s_cmd_tready(s_axis_mem1_read_cmd_tready), //: OUT STD_LOGIC; + .s_axis_mm2s_cmd_tdata(s_axis_mem1_read_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); + .m_axis_mm2s_sts_tvalid(m_axis_mem1_read_sts_tvalid), //: OUT STD_LOGIC; + .m_axis_mm2s_sts_tready(m_axis_mem1_read_sts_tready), //: IN STD_LOGIC; + .m_axis_mm2s_sts_tdata(m_axis_mem1_read_sts_tdata), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); .m_axis_mm2s_sts_tkeep(), //: OUT STD_LOGIC_VECTOR(0 DOWNTO 0); .m_axis_mm2s_sts_tlast(), //: OUT STD_LOGIC; - .m_axi_mm2s_arid(S01_AXI_ARID_x), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_mm2s_araddr(S01_AXI_ARADDR), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axi_mm2s_arlen(S01_AXI_ARLEN), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - .m_axi_mm2s_arsize(S01_AXI_ARSIZE), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_mm2s_arburst(S01_AXI_ARBURST), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_mm2s_arprot(), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_mm2s_arcache(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_mm2s_arid(c1_s_axi_arid), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_mm2s_araddr(c1_s_axi_araddr), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axi_mm2s_arlen(c1_s_axi_arlen), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .m_axi_mm2s_arsize(c1_s_axi_arsize), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_mm2s_arburst(c1_s_axi_arburst), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_mm2s_arprot(c1_s_axi_arprot), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_mm2s_arcache(c1_s_axi_arcache), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axi_mm2s_aruser(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_mm2s_arvalid(S01_AXI_ARVALID), //: OUT STD_LOGIC; - .m_axi_mm2s_arready(S01_AXI_ARREADY), //: IN STD_LOGIC; - .m_axi_mm2s_rdata(S01_AXI_RDATA), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axi_mm2s_rresp(S01_AXI_RRESP), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_mm2s_rlast(S01_AXI_RLAST), //: IN STD_LOGIC; - .m_axi_mm2s_rvalid(S01_AXI_RVALID), //: IN STD_LOGIC; - .m_axi_mm2s_rready(S01_AXI_RREADY), //: OUT STD_LOGIC; - .m_axis_mm2s_tdata(upd_m_axis_read_tdata), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axis_mm2s_tkeep(upd_m_axis_read_tkeep), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - .m_axis_mm2s_tlast(upd_m_axis_read_tlast), //: OUT STD_LOGIC; - .m_axis_mm2s_tvalid(upd_m_axis_read_tvalid), //: OUT STD_LOGIC; - .m_axis_mm2s_tready(upd_m_axis_read_tready), //: IN STD_LOGIC; - .m_axi_s2mm_aclk(clk156_25), //: IN STD_LOGIC; - .m_axi_s2mm_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s2mm_err(), //: OUT STD_LOGIC; + .m_axi_mm2s_arvalid(c1_s_axi_arvalid), //: OUT STD_LOGIC; + .m_axi_mm2s_arready(c1_s_axi_arready), //: IN STD_LOGIC; + .m_axi_mm2s_rdata(c1_s_axi_rdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); + .m_axi_mm2s_rresp(c1_s_axi_rresp), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_mm2s_rlast(c1_s_axi_rlast), //: IN STD_LOGIC; + .m_axi_mm2s_rvalid(c1_s_axi_rvalid), //: IN STD_LOGIC; + .m_axi_mm2s_rready(c1_s_axi_rready), //: OUT STD_LOGIC; + .m_axis_mm2s_tdata(axis_mem1_dm_to_cc_read_tdata), //: OUT STD_LOGIC_VECTOR(255 DOWNTO 0); + .m_axis_mm2s_tkeep(axis_mem1_dm_to_cc_read_tkeep), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axis_mm2s_tlast(axis_mem1_dm_to_cc_read_tlast), //: OUT STD_LOGIC; + .m_axis_mm2s_tvalid(axis_mem1_dm_to_cc_read_tvalid), //: OUT STD_LOGIC; + .m_axis_mm2s_tready(axis_mem1_dm_to_cc_read_tready), //: IN STD_LOGIC; + .m_axi_s2mm_aclk(c1_ui_clk), //: IN STD_LOGIC; + .m_axi_s2mm_aresetn(c1_aresetn_r), //: IN STD_LOGIC; + .s2mm_err(m1_s2mm_err), //: OUT STD_LOGIC; .m_axis_s2mm_cmdsts_awclk(clk156_25), //: IN STD_LOGIC; .m_axis_s2mm_cmdsts_aresetn(reset156_25_n), //: IN STD_LOGIC; - .s_axis_s2mm_cmd_tvalid(upd_s_axis_write_cmd_tvalid), //: IN STD_LOGIC; - .s_axis_s2mm_cmd_tready(upd_s_axis_write_cmd_tready), //: OUT STD_LOGIC; - .s_axis_s2mm_cmd_tdata(upd_s_axis_write_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); - .m_axis_s2mm_sts_tvalid(upd_m_axis_write_sts_tvalid), //: OUT STD_LOGIC; - .m_axis_s2mm_sts_tready(upd_m_axis_write_sts_tready), //: IN STD_LOGIC; - .m_axis_s2mm_sts_tdata(upd_m_axis_write_sts_tdata), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .s_axis_s2mm_cmd_tvalid(s_axis_mem1_write_cmd_tvalid), //: IN STD_LOGIC; + .s_axis_s2mm_cmd_tready(s_axis_mem1_write_cmd_tready), //: OUT STD_LOGIC; + .s_axis_s2mm_cmd_tdata(s_axis_mem1_write_cmd_tdata), //: IN STD_LOGIC_VECTOR(71 DOWNTO 0); + .m_axis_s2mm_sts_tvalid(m_axis_mem1_write_sts_tvalid), //: OUT STD_LOGIC; + .m_axis_s2mm_sts_tready(m_axis_mem1_write_sts_tready), //: IN STD_LOGIC; + .m_axis_s2mm_sts_tdata(m_axis_mem1_write_sts_tdata), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); .m_axis_s2mm_sts_tkeep(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axis_s2mm_sts_tlast(), //: OUT STD_LOGIC; - .m_axi_s2mm_awid(S01_AXI_AWID_x), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_s2mm_awaddr(S01_AXI_AWADDR), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); - .m_axi_s2mm_awlen(S01_AXI_AWLEN), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); - .m_axi_s2mm_awsize(S01_AXI_AWSIZE), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_s2mm_awburst(S01_AXI_AWBURST), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_s2mm_awprot(), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); - .m_axi_s2mm_awcache(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_s2mm_awid(c1_s_axi_awid), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + .m_axi_s2mm_awaddr(c1_s_axi_awaddr), //: OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + .m_axi_s2mm_awlen(c1_s_axi_awlen), //: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + .m_axi_s2mm_awsize(c1_s_axi_awsize), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_s2mm_awburst(c1_s_axi_awburst), //: OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_s2mm_awprot(c1_s_axi_awprot), //: OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + .m_axi_s2mm_awcache(c1_s_axi_awcache), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); .m_axi_s2mm_awuser(), //: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - .m_axi_s2mm_awvalid(S01_AXI_AWVALID), //: OUT STD_LOGIC; - .m_axi_s2mm_awready(S01_AXI_AWREADY), //: IN STD_LOGIC; - .m_axi_s2mm_wdata(S01_AXI_WDATA), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); - .m_axi_s2mm_wstrb(S01_AXI_WSTRB), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); - .m_axi_s2mm_wlast(S01_AXI_WLAST), //: OUT STD_LOGIC; - .m_axi_s2mm_wvalid(S01_AXI_WVALID), //: OUT STD_LOGIC; - .m_axi_s2mm_wready(S01_AXI_WREADY), //: IN STD_LOGIC; - .m_axi_s2mm_bresp(S01_AXI_BRESP), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); - .m_axi_s2mm_bvalid(S01_AXI_BVALID), //: IN STD_LOGIC; - .m_axi_s2mm_bready(S01_AXI_BREADY), //: OUT STD_LOGIC; - .s_axis_s2mm_tdata(upd_s_axis_write_tdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); - .s_axis_s2mm_tkeep(upd_s_axis_write_tkeep), //: IN STD_LOGIC_VECTOR(63 DOWNTO 0); - .s_axis_s2mm_tlast(upd_s_axis_write_tlast), //: IN STD_LOGIC; - .s_axis_s2mm_tvalid(upd_s_axis_write_tvalid), //: IN STD_LOGIC; - .s_axis_s2mm_tready(upd_s_axis_write_tready) //: OUT STD_LOGIC; + .m_axi_s2mm_awvalid(c1_s_axi_awvalid), //: OUT STD_LOGIC; + .m_axi_s2mm_awready(c1_s_axi_awready), //: IN STD_LOGIC; + .m_axi_s2mm_wdata(c1_s_axi_wdata), //: OUT STD_LOGIC_VECTOR(511 DOWNTO 0); + .m_axi_s2mm_wstrb(c1_s_axi_wstrb), //: OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + .m_axi_s2mm_wlast(c1_s_axi_wlast), //: OUT STD_LOGIC; + .m_axi_s2mm_wvalid(c1_s_axi_wvalid), //: OUT STD_LOGIC; + .m_axi_s2mm_wready(c1_s_axi_wready), //: IN STD_LOGIC; + .m_axi_s2mm_bresp(c1_s_axi_bresp), //: IN STD_LOGIC_VECTOR(1 DOWNTO 0); + .m_axi_s2mm_bvalid(c1_s_axi_bvalid), //: IN STD_LOGIC; + .m_axi_s2mm_bready(c1_s_axi_bready), //: OUT STD_LOGIC; + .s_axis_s2mm_tdata(axis_mem1_cc_to_dm_write_tdata), //: IN STD_LOGIC_VECTOR(511 DOWNTO 0); + .s_axis_s2mm_tkeep(axis_mem1_cc_to_dm_write_tkeep), //: IN STD_LOGIC_VECTOR(63 DOWNTO 0); + .s_axis_s2mm_tlast(axis_mem1_cc_to_dm_write_tlast), //: IN STD_LOGIC; + .s_axis_s2mm_tvalid(axis_mem1_cc_to_dm_write_tvalid), //: IN STD_LOGIC; + .s_axis_s2mm_tready(axis_mem1_cc_to_dm_write_tready) //: OUT STD_LOGIC; ); + end + else begin + assign s_axis_mem1_read_cmd_tready = 1'b1; + assign m_axis_mem1_read_sts_tvalid = 1'b0; + assign s_axis_mem1_write_cmd_tready = 1'b1; + assign m_axis_mem1_write_sts_tvalid = 1'b0; + end +endgenerate + endmodule + +`default_nettype wire diff --git a/rtl/7series/vc709/tcp_ip_top.v b/rtl/7series/vc709/tcp_ip_top.v index 38f428b..2bfa5d0 100755 --- a/rtl/7series/vc709/tcp_ip_top.v +++ b/rtl/7series/vc709/tcp_ip_top.v @@ -1,25 +1,10 @@ `timescale 1ns / 1ps `default_nettype none -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 21.11.2013 10:45:37 -// Design Name: -// Module Name: toe -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// +`define USE_DDR +`define ECHO_SERVER +//`define IPERF_CLIENT +`define UDP module tcp_ip_top( // 212MHz clock input @@ -43,8 +28,10 @@ output wire xphy0_txn, input wire xphy0_rxp, input wire xphy0_rxn, +input wire button_center, input wire button_north, input wire button_east, +input wire button_south, input wire button_west, /* output wire xphy1_txp, @@ -106,183 +93,167 @@ output wire[3:0] sfp_tx_disable, input wire [7:0] gpio_switch, output wire [7:0] led ); - + +wire aclk; +wire aresetn; +wire clk_ref_200; wire reset; -wire network_init; +wire network_init; reg button_east_reg; reg[7:0] led_reg; wire[7:0] led_out; -assign reset = button_east_reg; -wire aresetn; - -reg[15:0] wrCmdCounter; -reg[15:0] rdCmdCounter; -reg[15:0] rdAppCounter; - -wire upd_req_TVALID_out; -wire upd_req_TREADY_out; -wire upd_req_TDATA_out; -wire upd_rsp_TVALID_out; -wire upd_rsp_TREADY_out; - +assign reset = button_east_reg; assign aresetn = network_init; -//assign sfp_on = 1'b1; -//assign dram_on = 2'b11; -//assign c0_ddr3_dm = 9'h0; -//assign c1_ddr3_dm = 9'h0; -//assign aresetn = init_calib_complete_r; //reset156_25_n; -wire axi_clk; -wire clk_ref_200; + +always @(posedge aclk) begin + button_east_reg <= button_east; + led_reg <= led_out; +end +assign led = led_reg; /* * Network Signals */ -wire AXI_M_Stream_TVALID; -wire AXI_M_Stream_TREADY; -wire[63:0] AXI_M_Stream_TDATA; -wire[7:0] AXI_M_Stream_TKEEP; -wire AXI_M_Stream_TLAST; +wire axis_net_rx_data_tvalid; +wire axis_net_rx_data_tready; +wire[63:0] axis_net_rx_data_tdata; +wire[7:0] axis_net_rx_data_tkeep; +wire axis_net_rx_data_tlast; -wire AXI_S_Stream_TVALID; -wire AXI_S_Stream_TREADY; -wire[63:0] AXI_S_Stream_TDATA; -wire[7:0] AXI_S_Stream_TKEEP; -wire AXI_S_Stream_TLAST; +wire axis_net_tx_data_tvalid; +wire axis_net_tx_data_tready; +wire[63:0] axis_net_tx_data_tdata; +wire[7:0] axis_net_tx_data_tkeep; +wire axis_net_tx_data_tlast; /* * RX Memory Signals */ // memory cmd streams -wire axis_rxread_cmd_TVALID; -wire axis_rxread_cmd_TREADY; -wire[71:0] axis_rxread_cmd_TDATA; -wire axis_rxwrite_cmd_TVALID; -wire axis_rxwrite_cmd_TREADY; -wire[71:0] axis_rxwrite_cmd_TDATA; +wire axis_rxread_cmd_tvalid; +wire axis_rxread_cmd_tready; +wire[71:0] axis_rxread_cmd_tdata; +wire axis_rxwrite_cmd_tvalid; +wire axis_rxwrite_cmd_tready; +wire[71:0] axis_rxwrite_cmd_tdata; // memory sts streams -wire axis_rxread_sts_TVALID; -wire axis_rxread_sts_TREADY; -wire[7:0] axis_rxread_sts_TDATA; -wire axis_rxwrite_sts_TVALID; -wire axis_rxwrite_sts_TREADY; -wire[7:0] axis_rxwrite_sts_TDATA; +wire axis_rxwrite_sts_tvalid; +wire axis_rxwrite_sts_tready; +wire[7:0] axis_rxwrite_sts_tdata; // memory data streams -wire axis_rxread_data_TVALID; -wire axis_rxread_data_TREADY; -wire[63:0] axis_rxread_data_TDATA; -wire[7:0] axis_rxread_data_TKEEP; -wire axis_rxread_data_TLAST; - -wire axis_rxwrite_data_TVALID; -wire axis_rxwrite_data_TREADY; -wire[63:0] axis_rxwrite_data_TDATA; -wire[7:0] axis_rxwrite_data_TKEEP; -wire axis_rxwrite_data_TLAST; +wire axis_rxread_data_tvalid; +wire axis_rxread_data_tready; +wire[63:0] axis_rxread_data_tdata; +wire[7:0] axis_rxread_data_tkeep; +wire axis_rxread_data_tlast; + +wire axis_rxwrite_data_tvalid; +wire axis_rxwrite_data_tready; +wire[63:0] axis_rxwrite_data_tdata; +wire[7:0] axis_rxwrite_data_tkeep; +wire axis_rxwrite_data_tlast; /* * TX Memory Signals */ // memory cmd streams -wire axis_txread_cmd_TVALID; -wire axis_txread_cmd_TREADY; -wire[71:0] axis_txread_cmd_TDATA; -wire axis_txwrite_cmd_TVALID; -wire axis_txwrite_cmd_TREADY; -wire[71:0] axis_txwrite_cmd_TDATA; +wire axis_txread_cmd_tvalid; +wire axis_txread_cmd_tready; +wire[71:0] axis_txread_cmd_tdata; +wire axis_txwrite_cmd_tvalid; +wire axis_txwrite_cmd_tready; +wire[71:0] axis_txwrite_cmd_tdata; // memory sts streams -wire axis_txread_sts_TVALID; -wire axis_txread_sts_TREADY; -wire[7:0] axis_txread_sts_TDATA; -wire axis_txwrite_sts_TVALID; -wire axis_txwrite_sts_TREADY; -wire[7:0] axis_txwrite_sts_TDATA; +wire axis_txwrite_sts_tvalid; +wire axis_txwrite_sts_tready; +wire[7:0] axis_txwrite_sts_tdata; // memory data streams -wire axis_txread_data_TVALID; -wire axis_txread_data_TREADY; -wire[63:0] axis_txread_data_TDATA; -wire[7:0] axis_txread_data_TKEEP; -wire axis_txread_data_TLAST; - -wire axis_txwrite_data_TVALID; -wire axis_txwrite_data_TREADY; -wire[63:0] axis_txwrite_data_TDATA; -wire[7:0] axis_txwrite_data_TKEEP; -wire axis_txwrite_data_TLAST; +wire axis_txread_data_tvalid; +wire axis_txread_data_tready; +wire[63:0] axis_txread_data_tdata; +wire[7:0] axis_txread_data_tkeep; +wire axis_txread_data_tlast; + +wire axis_txwrite_data_tvalid; +wire axis_txwrite_data_tready; +wire[63:0] axis_txwrite_data_tdata; +wire[7:0] axis_txwrite_data_tkeep; +wire axis_txwrite_data_tlast; /* * Application Signals */ // listen&close port // open&close connection -wire axis_listen_port_TVALID; -wire axis_listen_port_TREADY; -wire[15:0] axis_listen_port_TDATA; -wire axis_listen_port_status_TVALID; -wire axis_listen_port_status_TREADY; -wire[7:0] axis_listen_port_status_TDATA; -//wire axis_close_port_TVALID; -//wire axis_close_port_TREADY; -//wire[15:0] axis_close_port_TDATA; +wire axis_listen_port_tvalid; +wire axis_listen_port_tready; +wire[15:0] axis_listen_port_tdata; +wire axis_listen_port_status_tvalid; +wire axis_listen_port_status_tready; +wire[7:0] axis_listen_port_status_tdata; // notifications and pkg fetching -wire axis_notifications_TVALID; -wire axis_notifications_TREADY; -wire[87:0] axis_notifications_TDATA; -wire axis_read_package_TVALID; -wire axis_read_package_TREADY; -wire[31:0] axis_read_package_TDATA; +wire axis_notifications_tvalid; +wire axis_notifications_tready; +wire[87:0] axis_notifications_tdata; +wire axis_read_package_tvalid; +wire axis_read_package_tready; +wire[31:0] axis_read_package_tdata; // open&close connection -wire axis_open_connection_TVALID; -wire axis_open_connection_TREADY; -wire[47:0] axis_open_connection_TDATA; -wire axis_open_status_TVALID; -wire axis_open_status_TREADY; -wire[23:0] axis_open_status_TDATA; -wire axis_close_connection_TVALID; -wire axis_close_connection_TREADY; -wire[15:0] axis_close_connection_TDATA; +wire axis_open_connection_tvalid; +wire axis_open_connection_tready; +wire[47:0] axis_open_connection_tdata; +wire axis_open_status_tvalid; +wire axis_open_status_tready; +wire[23:0] axis_open_status_tdata; +wire axis_close_connection_tvalid; +wire axis_close_connection_tready; +wire[15:0] axis_close_connection_tdata; // rx data -wire axis_rx_metadata_TVALID; -wire axis_rx_metadata_TREADY; -wire[15:0] axis_rx_metadata_TDATA; -wire axis_rx_data_TVALID; -wire axis_rx_data_TREADY; -wire[63:0] axis_rx_data_TDATA; -wire[7:0] axis_rx_data_TKEEP; -wire axis_rx_data_TLAST; +wire axis_rx_metadata_tvalid; +wire axis_rx_metadata_tready; +wire[15:0] axis_rx_metadata_tdata; +wire axis_rx_data_tvalid; +wire axis_rx_data_tready; +wire[63:0] axis_rx_data_tdata; +wire[7:0] axis_rx_data_tkeep; +wire axis_rx_data_tlast; // tx data -wire axis_tx_metadata_TVALID; -wire axis_tx_metadata_TREADY; -wire[31:0] axis_tx_metadata_TDATA; -wire axis_tx_data_TVALID; -wire axis_tx_data_TREADY; -wire[63:0] axis_tx_data_TDATA; -wire[7:0] axis_tx_data_TKEEP; -wire axis_tx_data_TLAST; -wire axis_tx_status_TVALID; -wire axis_tx_status_TREADY; -wire[23:0] axis_tx_status_TDATA; - -wire[15:0] regSessionCount; -wire[15:0] relSessionCount; +wire axis_tx_metadata_tvalid; +wire axis_tx_metadata_tready; +wire[31:0] axis_tx_metadata_tdata; +wire axis_tx_data_tvalid; +wire axis_tx_data_tready; +wire[63:0] axis_tx_data_tdata; +wire[7:0] axis_tx_data_tkeep; +wire axis_tx_data_tlast; +wire axis_tx_status_tvalid; +wire axis_tx_status_tready; +wire[31:0] axis_tx_status_tdata; - -always @(posedge axi_clk) begin - button_east_reg <= button_east; - led_reg <= led_out; -/* runExperiment <= button_north | vio_cmd[0]; - dualModeEn <= vio_cmd[1]; - useConn <= vio_cmd[15:2]; - pkgWordCount <= vio_cmd[23:16]; - regIpSub0 <= vio_cmd[31:24]; - regIpSub1 <= vio_cmd[39:32]; - regIpSub2 <= vio_cmd[47:40]; - regIpSub3 <= vio_cmd[55:48];*/ - //regIpAddress1 <= vio_cmd[49:18]; - //numCons <= vio_cmd[33:18]; -end -assign led = led_reg; +/* + * UPD signals + */ +`ifdef UDP +wire axis_rx_udp_metadata_tvalid; +wire axis_rx_udp_metadata_tready; +wire[175:0] axis_rx_udp_metadata_tdata; +wire axis_rx_udp_data_tvalid; +wire axis_rx_udp_data_tready; +wire[63:0] axis_rx_udp_data_tdata; +wire[7:0] axis_rx_udp_data_tkeep; +wire axis_rx_udp_data_tlast; + +wire axis_tx_udp_metadata_tvalid; +wire axis_tx_udp_metadata_tready; +wire[175:0] axis_tx_udp_metadata_tdata; +wire axis_tx_udp_data_tvalid; +wire axis_tx_udp_data_tready; +wire[63:0] axis_tx_udp_data_tdata; +wire[7:0] axis_tx_udp_data_tkeep; +wire axis_tx_udp_data_tlast; +`endif /* @@ -310,23 +281,23 @@ vc709_10g_interface n10g_interface_inst //master - .axis_i_0_tdata(AXI_S_Stream_TDATA), - .axis_i_0_tvalid(AXI_S_Stream_TVALID), - .axis_i_0_tlast(AXI_S_Stream_TLAST), + .axis_i_0_tdata(axis_net_rx_data_tdata), + .axis_i_0_tvalid(axis_net_rx_data_tvalid), + .axis_i_0_tlast(axis_net_rx_data_tlast), .axis_i_0_tuser(), - .axis_i_0_tkeep(AXI_S_Stream_TKEEP), - .axis_i_0_tready(AXI_S_Stream_TREADY), + .axis_i_0_tkeep(axis_net_rx_data_tkeep), + .axis_i_0_tready(axis_net_rx_data_tready), //slave - .axis_o_0_tdata(AXI_M_Stream_TDATA), - .axis_o_0_tvalid(AXI_M_Stream_TVALID), - .axis_o_0_tlast(AXI_M_Stream_TLAST), + .axis_o_0_tdata(axis_net_tx_data_tdata), + .axis_o_0_tvalid(axis_net_tx_data_tvalid), + .axis_o_0_tlast(axis_net_tx_data_tlast), .axis_o_0_tuser(0), - .axis_o_0_tkeep(AXI_M_Stream_TKEEP), - .axis_o_0_tready(AXI_M_Stream_TREADY), + .axis_o_0_tkeep(axis_net_tx_data_tkeep), + .axis_o_0_tready(axis_net_tx_data_tready), .sfp_tx_disable(sfp_tx_disable), - .clk156_out(axi_clk), + .clk156_out(aclk), .clk_ref_200_out(clk_ref_200), .network_reset_done(network_init), .led(led_out) @@ -336,640 +307,400 @@ vc709_10g_interface n10g_interface_inst /* * TCP/IP Wrapper Module */ -wire [15:0] regSessionCount_V; -wire regSessionCount_V_ap_vld; - -wire[7:0] axi_debug1_tkeep; -wire[63:0] axi_debug1_tdata; -wire axi_debug1_tvalid; -wire axi_debug1_tready; -wire axi_debug1_tlast; - -wire[7:0] axi_debug2_tkeep; -wire[63:0] axi_debug2_tdata; -wire axi_debug2_tvalid; -wire axi_debug2_tready; -wire axi_debug2_tlast; +wire [15:0] regSessionCount; + wire regSessionCount_valid; + + wire[31:0] ip_address_out; + reg[31:0] local_ip_address; + reg[31:0] target_ip_address; + + always @(posedge aclk) begin + local_ip_address <= 32'hD1D4010A; //0x0A01D4D1 -> 10.1.212.209 + target_ip_address <= {24'h0AD401, 8'h0A + gpio_switch[3]}; // 10.1.212.10 + end + + +network_stack #( + .IP_SUBNET_MASK (32'h00FFFFFF), //reverse + .IP_DEFAULT_GATEWAY (32'h01D4010A) //reverse //TODO fix this + ) + network_stack_inst ( + .aclk (aclk), + .aresetn (aresetn), + + // network interface streams + .AXI_M_Stream_TVALID (axis_net_tx_data_tvalid), + .AXI_M_Stream_TREADY (axis_net_tx_data_tready), + .AXI_M_Stream_TDATA (axis_net_tx_data_tdata), + .AXI_M_Stream_TKEEP (axis_net_tx_data_tkeep), + .AXI_M_Stream_TLAST (axis_net_tx_data_tlast), + + .AXI_S_Stream_TVALID (axis_net_rx_data_tvalid), + .AXI_S_Stream_TREADY (axis_net_rx_data_tready), + .AXI_S_Stream_TDATA (axis_net_rx_data_tdata), + .AXI_S_Stream_TKEEP (axis_net_rx_data_tkeep), + .AXI_S_Stream_TLAST (axis_net_rx_data_tlast), + + // memory rx cmd streams + .m_axis_rxread_cmd_TVALID (axis_rxread_cmd_tvalid), + .m_axis_rxread_cmd_TREADY (axis_rxread_cmd_tready), + .m_axis_rxread_cmd_TDATA (axis_rxread_cmd_tdata), + .m_axis_rxwrite_cmd_TVALID (axis_rxwrite_cmd_tvalid), + .m_axis_rxwrite_cmd_TREADY (axis_rxwrite_cmd_tready), + .m_axis_rxwrite_cmd_TDATA (axis_rxwrite_cmd_tdata), + // memory rx status streams + .s_axis_rxwrite_sts_TVALID (axis_rxwrite_sts_tvalid), + .s_axis_rxwrite_sts_TREADY (axis_rxwrite_sts_tready), + .s_axis_rxwrite_sts_TDATA (axis_rxwrite_sts_tdata), + // memory rx data streams + .s_axis_rxread_data_TVALID (axis_rxread_data_tvalid), + .s_axis_rxread_data_TREADY (axis_rxread_data_tready), + .s_axis_rxread_data_TDATA (axis_rxread_data_tdata), + .s_axis_rxread_data_TKEEP (axis_rxread_data_tkeep), + .s_axis_rxread_data_TLAST (axis_rxread_data_tlast), + .m_axis_rxwrite_data_TVALID (axis_rxwrite_data_tvalid), + .m_axis_rxwrite_data_TREADY (axis_rxwrite_data_tready), + .m_axis_rxwrite_data_TDATA (axis_rxwrite_data_tdata), + .m_axis_rxwrite_data_TKEEP (axis_rxwrite_data_tkeep), + .m_axis_rxwrite_data_TLAST (axis_rxwrite_data_tlast), + + // memory tx cmd streams + .m_axis_txread_cmd_TVALID (axis_txread_cmd_tvalid), + .m_axis_txread_cmd_TREADY (axis_txread_cmd_tready), + .m_axis_txread_cmd_TDATA (axis_txread_cmd_tdata), + .m_axis_txwrite_cmd_TVALID (axis_txwrite_cmd_tvalid), + .m_axis_txwrite_cmd_TREADY (axis_txwrite_cmd_tready), + .m_axis_txwrite_cmd_TDATA (axis_txwrite_cmd_tdata), + // memory tx status streams + .s_axis_txwrite_sts_TVALID (axis_txwrite_sts_tvalid), + .s_axis_txwrite_sts_TREADY (axis_txwrite_sts_tready), + .s_axis_txwrite_sts_TDATA (axis_txwrite_sts_tdata), + // memory tx data streams + .s_axis_txread_data_TVALID (axis_txread_data_tvalid), + .s_axis_txread_data_TREADY (axis_txread_data_tready), + .s_axis_txread_data_TDATA (axis_txread_data_tdata), + .s_axis_txread_data_TKEEP (axis_txread_data_tkeep), + .s_axis_txread_data_TLAST (axis_txread_data_tlast), + .m_axis_txwrite_data_TVALID (axis_txwrite_data_tvalid), + .m_axis_txwrite_data_TREADY (axis_txwrite_data_tready), + .m_axis_txwrite_data_TDATA (axis_txwrite_data_tdata), + .m_axis_txwrite_data_TKEEP (axis_txwrite_data_tkeep), + .m_axis_txwrite_data_TLAST (axis_txwrite_data_tlast), + + //application interface streams + .m_axis_listen_port_status_TVALID (axis_listen_port_status_tvalid), + .m_axis_listen_port_status_TREADY (axis_listen_port_status_tready), + .m_axis_listen_port_status_TDATA (axis_listen_port_status_tdata), + .m_axis_notifications_TVALID (axis_notifications_tvalid), + .m_axis_notifications_TREADY (axis_notifications_tready), + .m_axis_notifications_TDATA (axis_notifications_tdata), + .m_axis_open_status_TVALID (axis_open_status_tvalid), + .m_axis_open_status_TREADY (axis_open_status_tready), + .m_axis_open_status_TDATA (axis_open_status_tdata), + .m_axis_rx_data_TVALID (axis_rx_data_tvalid), + .m_axis_rx_data_TREADY (axis_rx_data_tready), + .m_axis_rx_data_TDATA (axis_rx_data_tdata), + .m_axis_rx_data_TKEEP (axis_rx_data_tkeep), + .m_axis_rx_data_TLAST (axis_rx_data_tlast), + .m_axis_rx_metadata_TVALID (axis_rx_metadata_tvalid), + .m_axis_rx_metadata_TREADY (axis_rx_metadata_tready), + .m_axis_rx_metadata_TDATA (axis_rx_metadata_tdata), + .m_axis_tx_status_TVALID (axis_tx_status_tvalid), + .m_axis_tx_status_TREADY (axis_tx_status_tready), + .m_axis_tx_status_TDATA (axis_tx_status_tdata), + .s_axis_listen_port_TVALID (axis_listen_port_tvalid), + .s_axis_listen_port_TREADY (axis_listen_port_tready), + .s_axis_listen_port_TDATA (axis_listen_port_tdata), + .s_axis_close_connection_TVALID (axis_close_connection_tvalid), + .s_axis_close_connection_TREADY (axis_close_connection_tready), + .s_axis_close_connection_TDATA (axis_close_connection_tdata), + .s_axis_open_connection_TVALID (axis_open_connection_tvalid), + .s_axis_open_connection_TREADY (axis_open_connection_tready), + .s_axis_open_connection_TDATA (axis_open_connection_tdata), + .s_axis_read_package_TVALID (axis_read_package_tvalid), + .s_axis_read_package_TREADY (axis_read_package_tready), + .s_axis_read_package_TDATA (axis_read_package_tdata), + .s_axis_tx_data_TVALID (axis_tx_data_tvalid), + .s_axis_tx_data_TREADY (axis_tx_data_tready), + .s_axis_tx_data_TDATA (axis_tx_data_tdata), + .s_axis_tx_data_TKEEP (axis_tx_data_tkeep), + .s_axis_tx_data_TLAST (axis_tx_data_tlast), + .s_axis_tx_metadata_TVALID (axis_tx_metadata_tvalid), + .s_axis_tx_metadata_TREADY (axis_tx_metadata_tready), + .s_axis_tx_metadata_TDATA (axis_tx_metadata_tdata), + `ifdef UDP + //UPD interface + //RX + .m_axis_udp_metadata_TVALID (axis_rx_udp_metadata_tvalid), + .m_axis_udp_metadata_TREADY (axis_rx_udp_metadata_tready), + .m_axis_udp_metadata_TDATA (axis_rx_udp_metadata_tdata), + .m_axis_udp_data_TVALID (axis_rx_udp_data_tvalid), + .m_axis_udp_data_TREADY (axis_rx_udp_data_tready), + .m_axis_udp_data_TDATA (axis_rx_udp_data_tdata), + .m_axis_udp_data_TKEEP (axis_rx_udp_data_tkeep), + .m_axis_udp_data_TLAST (axis_rx_udp_data_tlast), + //TX + .s_axis_udp_metadata_TVALID (axis_tx_udp_metadata_tvalid), + .s_axis_udp_metadata_TREADY (axis_tx_udp_metadata_tready), + .s_axis_udp_metadata_TDATA (axis_tx_udp_metadata_tdata), + .s_axis_udp_data_TVALID (axis_tx_udp_data_tvalid), + .s_axis_udp_data_TREADY (axis_tx_udp_data_tready), + .s_axis_udp_data_TDATA (axis_tx_udp_data_tdata), + .s_axis_udp_data_TKEEP (axis_tx_udp_data_tkeep), + .s_axis_udp_data_TLAST (axis_tx_udp_data_tlast), + `endif + .ip_address_in(local_ip_address), + .ip_address_out(ip_address_out), + .regSessionCount_V(regSessionCount), + .regSessionCount_V_ap_vld(regSessionCount_valid), + + .board_number(gpio_switch[3:0]), + .subnet_number(gpio_switch[5:4]) + + ); + /* -ila_0 ila_out ( - .clk(axi_clk), // input wire clk - .probe0(axi_debug1_tdata), // input wire [63 : 0] probe1 - .probe1(axi_debug1_tkeep), // input wire [7 : 0] probe0 - .probe2(axi_debug1_tvalid), // input wire [0 : 0] probe2 - .probe3(axi_debug1_tready), // input wire [0 : 0] probe3 - .probe4(axi_debug1_tlast) // input wire [0 : 0] probe4 -); - - -ila_0 ila_in ( - .clk(axi_clk), // input wire clk - .probe1(axi_debug2_tkeep), // input wire [7 : 0] probe1 - .probe0(axi_debug2_tdata), // input wire [63 : 0] probe0 - .probe2(axi_debug2_tvalid), // input wire [0 : 0] probe2 - .probe3(axi_debug2_tready), // input wire [0 : 0] probe3 - .probe4(axi_debug2_tlast) // input wire [0 : 0] probe4 -);*/ - -/*ila_0 ila1 ( - .clk(axi_clk), // input wire clk - .probe1(AXI_S_Stream_TKEEP), // input wire [7 : 0] probe1 - .probe0(AXI_S_Stream_TDATA), // input wire [63 : 0] probe0 - .probe2(AXI_S_Stream_TVALID), // input wire [0 : 0] probe2 - .probe3(AXI_S_Stream_TREADY), // input wire [0 : 0] probe3 - .probe4(AXI_S_Stream_TLAST) // input wire [0 : 0] probe4 -); - -ila_0 ila2 ( - .clk(axi_clk), // input wire clk - .probe1(AXI_M_Stream_TKEEP), // input wire [7 : 0] probe1 - .probe0(AXI_M_Stream_TDATA), // input wire [63 : 0] probe0 - .probe2(AXI_M_Stream_TVALID), // input wire [0 : 0] probe2 - .probe3(AXI_M_Stream_TREADY), // input wire [0 : 0] probe3 - .probe4(AXI_M_Stream_TLAST) // input wire [0 : 0] probe4 -);*/ -// UDP Loopback App to UDP App Mux wires -wire shim2mux_requestPortOpenOut_V_TVALID; -wire shim2mux_requestPortOpenOut_V_TREADY; -wire[15:0] shim2mux_requestPortOpenOut_V_TDATA; // Used to request the opening of a port by the App -wire mux2shim_portOpenReplyIn_V_V_TVALID; -wire mux2shim_portOpenReplyIn_V_V_TREADY; -wire[7:0] mux2shim_portOpenReplyIn_V_V_TDATA; // Reply to the open port request from the UDD Offload Engine -wire mux2shimRxMetadataIn_V_TVALID; -wire mux2shimRxMetadataIn_V_TREADY; -wire[95:0] mux2shimRxMetadataIn_V_TDATA; // Metadata output from the UDP App Mux -wire mux2shimRxDataIn_TVALID; -wire mux2shimRxDataIn_TREADY; -wire[63:0] mux2shimRxDataIn_TDATA; // Packet data output from the UDP App Mux -wire mux2shimRxDataIn_TLAST; -wire[7:0] mux2shimRxDataIn_TKEEP; -wire shim2mux_TVALID; -wire shim2mux_TREADY; -wire[63:0] shim2mux_TDATA; -wire[7:0] shim2mux_TKEEP; -wire shim2mux_TLAST; -wire shim2muxTxMetadataOut_V_TVALID; -wire shim2muxTxMetadataOut_V_TREADY; -wire[95:0] shim2muxTxMetadataOut_V_TDATA; -wire shim2muxTxLengthOut_V_V_TVALID; -wire shim2muxTxLengthOut_V_V_TREADY; -wire[15:0] shim2muxTxLengthOut_V_V_TDATA; - -wire[31:0] ipAddressOut; - -/*ila_0 ipAddressIla ( - .clk(axi_clk), // input wire clk - .probe0(ipAddressOut) // input wire [31:0] probe0 -);*/ - -// Debug signals // -wire[99:0] metadataFifo_din; // [99:0] -wire metadataFifo_full; -wire metadataFifo_write; - -wire[15:0] metadataHandlerFifo_din; // [15:0] -wire metadataHandlerFifo_full; -wire metadataHandlerFifo_write; -//////////////////// -/*ila_0 mdFifo ( - .clk(axi_clk), // input wire clk - .probe0(metadataFifo_din), // input wire [99:0] probe0 - .probe1(metadataFifo_full), // input wire [0:0] probe1 - .probe2(metadataFifo_write) // input wire [0:0] probe2 -); - -ila_1 mdHandlerFifo ( - .clk(axi_clk), // input wire clk - .probe0(metadataHandlerFifo_din), // input wire [15:0] probe0 - .probe1(metadataHandlerFifo_full), // input wire [0:0] probe1 - .probe2(metadataHandlerFifo_write) // input wire [0:0] probe2 -);*/ - -network_stack network_stack_inst( -.aclk (axi_clk), -.aresetn (aresetn), -.myMacAddress (48'hE59D02350A00), -.inputIpAddress (32'hD1D4010A), -.dhcpEnable (1'b0), -.ipAddressOut (ipAddressOut), -.regSessionCount (regSessionCount), -.relSessionCount (relSessionCount), -////////////////////////////////////////////////// -.upd_req_TVALID_out(upd_req_TVALID_out), -.upd_req_TREADY_out(upd_req_TREADY_out), -.upd_req_TDATA_out(upd_req_TDATA_out), -.upd_rsp_TVALID_out(upd_rsp_TVALID_out), -.upd_rsp_TREADY_out(upd_rsp_TREADY_out), -// Debug streams -.axi_debug1_tkeep (axi_debug1_tkeep), // input wire [7 : 0] probe1 -.axi_debug1_tdata (axi_debug1_tdata), // input wire [63 : 0] probe0 -.axi_debug1_tvalid (axi_debug1_tvalid), // input wire [0 : 0] probe2 -.axi_debug1_tready (axi_debug1_tready), // input wire [0 : 0] probe3 -.axi_debug1_tlast (axi_debug1_tlast), // input wire [0 : 0] probe4 -.axi_debug2_tkeep (axi_debug2_tkeep), // input wire [7 : 0] probe1 -.axi_debug2_tdata (axi_debug2_tdata), // input wire [63 : 0] probe0 -.axi_debug2_tvalid (axi_debug2_tvalid), // input wire [0 : 0] probe2 -.axi_debug2_tready (axi_debug2_tready), // input wire [0 : 0] probe3 -.axi_debug2_tlast (axi_debug2_tlast), // input wire [0 : 0] probe4 -// Debug signals // -.metadataFifo_din(metadataFifo_din), -.metadataFifo_full(metadataFifo_full), -.metadataFifo_write(metadataFifo_write), -.metadataHandlerFifo_din(metadataHandlerFifo_din), -.metadataHandlerFifo_full(metadataHandlerFifo_full), -.metadataHandlerFifo_write(metadataHandlerFifo_write), -//////////////////// -// network interface streams -.AXI_M_Stream_TVALID (AXI_M_Stream_TVALID), -.AXI_M_Stream_TREADY (AXI_M_Stream_TREADY), -.AXI_M_Stream_TDATA (AXI_M_Stream_TDATA), -.AXI_M_Stream_TKEEP (AXI_M_Stream_TKEEP), -.AXI_M_Stream_TLAST (AXI_M_Stream_TLAST), - -.AXI_S_Stream_TVALID (AXI_S_Stream_TVALID), -.AXI_S_Stream_TREADY (AXI_S_Stream_TREADY), -.AXI_S_Stream_TDATA (AXI_S_Stream_TDATA), -.AXI_S_Stream_TKEEP (AXI_S_Stream_TKEEP), -.AXI_S_Stream_TLAST (AXI_S_Stream_TLAST), - -// memory rx cmd streams -.m_axis_rxread_cmd_TVALID (axis_rxread_cmd_TVALID), -.m_axis_rxread_cmd_TREADY (axis_rxread_cmd_TREADY), -.m_axis_rxread_cmd_TDATA (axis_rxread_cmd_TDATA), -.m_axis_rxwrite_cmd_TVALID (axis_rxwrite_cmd_TVALID), -.m_axis_rxwrite_cmd_TREADY (axis_rxwrite_cmd_TREADY), -.m_axis_rxwrite_cmd_TDATA (axis_rxwrite_cmd_TDATA), -// memory rx status streams -//.s_axis_rxread_sts_TVALID (axis_rxread_sts_TVALID), -//.s_axis_rxread_sts_TREADY (axis_rxread_sts_TREADY), -//.s_axis_rxread_sts_TDATA (axis_rxread_sts_TDATA), -.s_axis_rxwrite_sts_TVALID (axis_rxwrite_sts_TVALID), -.s_axis_rxwrite_sts_TREADY (axis_rxwrite_sts_TREADY), -.s_axis_rxwrite_sts_TDATA (axis_rxwrite_sts_TDATA), -// memory rx data streams -.s_axis_rxread_data_TVALID (axis_rxread_data_TVALID), -.s_axis_rxread_data_TREADY (axis_rxread_data_TREADY), -.s_axis_rxread_data_TDATA (axis_rxread_data_TDATA), -.s_axis_rxread_data_TKEEP (axis_rxread_data_TKEEP), -.s_axis_rxread_data_TLAST (axis_rxread_data_TLAST), -.m_axis_rxwrite_data_TVALID (axis_rxwrite_data_TVALID), -.m_axis_rxwrite_data_TREADY (axis_rxwrite_data_TREADY), -.m_axis_rxwrite_data_TDATA (axis_rxwrite_data_TDATA), -.m_axis_rxwrite_data_TKEEP (axis_rxwrite_data_TKEEP), -.m_axis_rxwrite_data_TLAST (axis_rxwrite_data_TLAST), - -// memory tx cmd streams -.m_axis_txread_cmd_TVALID (axis_txread_cmd_TVALID), -.m_axis_txread_cmd_TREADY (axis_txread_cmd_TREADY), -.m_axis_txread_cmd_TDATA (axis_txread_cmd_TDATA), -.m_axis_txwrite_cmd_TVALID (axis_txwrite_cmd_TVALID), -.m_axis_txwrite_cmd_TREADY (axis_txwrite_cmd_TREADY), -.m_axis_txwrite_cmd_TDATA (axis_txwrite_cmd_TDATA), -// memory tx status streams -//.s_axis_txread_sts_TVALID (axis_txread_sts_TVALID), -//.s_axis_txread_sts_TREADY (axis_txread_sts_TREADY), -//.s_axis_txread_sts_TDATA (axis_txread_sts_TDATA), -.s_axis_txwrite_sts_TVALID (axis_txwrite_sts_TVALID), -.s_axis_txwrite_sts_TREADY (axis_txwrite_sts_TREADY), -.s_axis_txwrite_sts_TDATA (axis_txwrite_sts_TDATA), -// memory tx data streams -.s_axis_txread_data_TVALID (axis_txread_data_TVALID), -.s_axis_txread_data_TREADY (axis_txread_data_TREADY), -.s_axis_txread_data_TDATA (axis_txread_data_TDATA), -.s_axis_txread_data_TKEEP (axis_txread_data_TKEEP), -.s_axis_txread_data_TLAST (axis_txread_data_TLAST), -.m_axis_txwrite_data_TVALID (axis_txwrite_data_TVALID), -.m_axis_txwrite_data_TREADY (axis_txwrite_data_TREADY), -.m_axis_txwrite_data_TDATA (axis_txwrite_data_TDATA), -.m_axis_txwrite_data_TKEEP (axis_txwrite_data_TKEEP), -.m_axis_txwrite_data_TLAST (axis_txwrite_data_TLAST), - -//application interface streams -.m_axis_listen_port_status_TVALID (axis_listen_port_status_TVALID), -.m_axis_listen_port_status_TREADY (axis_listen_port_status_TREADY), -.m_axis_listen_port_status_TDATA (axis_listen_port_status_TDATA), -.m_axis_notifications_TVALID (axis_notifications_TVALID), -.m_axis_notifications_TREADY (axis_notifications_TREADY), -.m_axis_notifications_TDATA (axis_notifications_TDATA), -.m_axis_open_status_TVALID (axis_open_status_TVALID), -.m_axis_open_status_TREADY (axis_open_status_TREADY), -.m_axis_open_status_TDATA (axis_open_status_TDATA), -.m_axis_rx_data_TVALID (axis_rx_data_TVALID), -.m_axis_rx_data_TREADY (axis_rx_data_TREADY), -.m_axis_rx_data_TDATA (axis_rx_data_TDATA), -.m_axis_rx_data_TKEEP (axis_rx_data_TKEEP), -.m_axis_rx_data_TLAST (axis_rx_data_TLAST), -.m_axis_rx_metadata_TVALID (axis_rx_metadata_TVALID), -.m_axis_rx_metadata_TREADY (axis_rx_metadata_TREADY), -.m_axis_rx_metadata_TDATA (axis_rx_metadata_TDATA), -.m_axis_tx_status_TVALID (axis_tx_status_TVALID), -.m_axis_tx_status_TREADY (axis_tx_status_TREADY), -.m_axis_tx_status_TDATA (axis_tx_status_TDATA), -.s_axis_listen_port_TVALID (axis_listen_port_TVALID), -.s_axis_listen_port_TREADY (axis_listen_port_TREADY), -.s_axis_listen_port_TDATA (axis_listen_port_TDATA), -//.s_axis_close_port_TVALID (axis_close_port_TVALID), -//.s_axis_close_port_TREADY (axis_close_port_TREADY), -//.s_axis_close_port_TDATA (axis_close_port_TDATA), -.s_axis_close_connection_TVALID (axis_close_connection_TVALID), -.s_axis_close_connection_TREADY (axis_close_connection_TREADY), -.s_axis_close_connection_TDATA (axis_close_connection_TDATA), -.s_axis_open_connection_TVALID (axis_open_connection_TVALID), -.s_axis_open_connection_TREADY (axis_open_connection_TREADY), -.s_axis_open_connection_TDATA (axis_open_connection_TDATA), -.s_axis_read_package_TVALID (axis_read_package_TVALID), -.s_axis_read_package_TREADY (axis_read_package_TREADY), -.s_axis_read_package_TDATA (axis_read_package_TDATA), -.s_axis_tx_data_TVALID (axis_tx_data_TVALID), -.s_axis_tx_data_TREADY (axis_tx_data_TREADY), -.s_axis_tx_data_TDATA (axis_tx_data_TDATA), -.s_axis_tx_data_TKEEP (axis_tx_data_TKEEP), -.s_axis_tx_data_TLAST (axis_tx_data_TLAST), -.s_axis_tx_metadata_TVALID (axis_tx_metadata_TVALID), -.s_axis_tx_metadata_TREADY (axis_tx_metadata_TREADY), -.s_axis_tx_metadata_TDATA (axis_tx_metadata_TDATA), -.regSessionCount_V (regSessionCount_V), -.regSessionCount_V_ap_vld (regSessionCount_V_ap_vld), -// UDP User I/F to Loopback module // -.lbPortOpenReplyIn_TVALID (mux2shim_portOpenReplyIn_V_V_TVALID), // output wire portOpenReplyIn_TVALID -.lbPortOpenReplyIn_TREADY (mux2shim_portOpenReplyIn_V_V_TREADY), // input wire portOpenReplyIn_TREADY -.lbPortOpenReplyIn_TDATA (mux2shim_portOpenReplyIn_V_V_TDATA), // output wire [7 : 0] portOpenReplyIn_TDATA -.lbRequestPortOpenOut_TVALID (shim2mux_requestPortOpenOut_V_TVALID), // input wire requestPortOpenOut_TVALID -.lbRequestPortOpenOut_TREADY (shim2mux_requestPortOpenOut_V_TREADY), // output wire requestPortOpenOut_TREADY -.lbRequestPortOpenOut_TDATA (shim2mux_requestPortOpenOut_V_TDATA), // input wire [15 : 0] requestPortOpenOut_TDATA -.lbRxDataIn_TVALID (mux2shimRxDataIn_TVALID), // output wire rxDataIn_TVALID -.lbRxDataIn_TREADY (mux2shimRxDataIn_TREADY), // input wire rxDataIn_TREADY -.lbRxDataIn_TDATA (mux2shimRxDataIn_TDATA), // output wire [63 : 0] rxDataIn_TDATA -.lbRxDataIn_TKEEP (mux2shimRxDataIn_TKEEP), // output wire [7 : 0] rxDataIn_TKEEP -.lbRxDataIn_TLAST (mux2shimRxDataIn_TLAST), // output wire [0 : 0] rxDataIn_TLAST -.lbRxMetadataIn_TVALID (mux2shimRxMetadataIn_V_TVALID), // output wire rxMetadataIn_TVALID -.lbRxMetadataIn_TREADY (mux2shimRxMetadataIn_V_TREADY), // input wire rxMetadataIn_TREADY -.lbRxMetadataIn_TDATA (mux2shimRxMetadataIn_V_TDATA), // output wire [95 : 0] rxMetadataIn_TDATA -.lbTxDataOut_TVALID (shim2mux_TVALID), // input wire txDataOut_TVALID -.lbTxDataOut_TREADY (shim2mux_TREADY), // output wire txDataOut_TREADY -.lbTxDataOut_TDATA (shim2mux_TDATA), // input wire [63 : 0] txDataOut_TDATA -.lbTxDataOut_TKEEP (shim2mux_TKEEP), // input wire [7 : 0] txDataOut_TKEEP -.lbTxDataOut_TLAST (shim2mux_TLAST), // input wire [0 : 0] txDataOut_TLAST -.lbTxLengthOut_TVALID (shim2muxTxLengthOut_V_V_TVALID), // input wire txLengthOut_TVALID -.lbTxLengthOut_TREADY (shim2muxTxLengthOut_V_V_TREADY), // output wire txLengthOut_TREADY -.lbTxLengthOut_TDATA (shim2muxTxLengthOut_V_V_TDATA), // input wire [15 : 0] txLengthOut_TDATA -.lbTxMetadataOut_TVALID (shim2muxTxMetadataOut_V_TVALID), // input wire txMetadataOut_TVALID -.lbTxMetadataOut_TREADY (shim2muxTxMetadataOut_V_TREADY), // output wire txMetadataOut_TREADY -.lbTxMetadataOut_TDATA (shim2muxTxMetadataOut_V_TDATA) // input wire [95 : 0] txMetadataOut_TDATA -); + * Application Module + */ + /*echo_server_application_ip echo_server ( + .m_axis_close_connection_V_V_TVALID(axis_close_connection_tvalid), // output wire m_axis_close_connection_TVALID + .m_axis_close_connection_V_V_TREADY(axis_close_connection_tready), // input wire m_axis_close_connection_TREADY + .m_axis_close_connection_V_V_TDATA(axis_close_connection_tdata), // output wire [15 : 0] m_axis_close_connection_TDATA + .m_axis_listen_port_V_V_TVALID(axis_listen_port_tvalid), // output wire m_axis_listen_port_TVALID + .m_axis_listen_port_V_V_TREADY(axis_listen_port_tready), // input wire m_axis_listen_port_TREADY + .m_axis_listen_port_V_V_TDATA(axis_listen_port_tdata), // output wire [15 : 0] m_axis_listen_port_TDATA + .m_axis_open_connection_V_TVALID(axis_open_connection_tvalid), // output wire m_axis_open_connection_TVALID + .m_axis_open_connection_V_TREADY(axis_open_connection_tready), // input wire m_axis_open_connection_TREADY + .m_axis_open_connection_V_TDATA(axis_open_connection_tdata), // output wire [47 : 0] m_axis_open_connection_TDATA + .m_axis_read_package_V_TVALID(axis_read_package_tvalid), // output wire m_axis_read_package_TVALID + .m_axis_read_package_V_TREADY(axis_read_package_tready), // input wire m_axis_read_package_TREADY + .m_axis_read_package_V_TDATA(axis_read_package_tdata), // output wire [31 : 0] m_axis_read_package_TDATA + .m_axis_tx_data_TVALID(axis_tx_data_tvalid), // output wire m_axis_tx_data_TVALID + .m_axis_tx_data_TREADY(axis_tx_data_tready), // input wire m_axis_tx_data_TREADY + .m_axis_tx_data_TDATA(axis_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA + .m_axis_tx_data_TKEEP(axis_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP + .m_axis_tx_data_TLAST(axis_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST + .m_axis_tx_metadata_V_TVALID(axis_tx_metadata_tvalid), // output wire m_axis_tx_metadata_TVALID + .m_axis_tx_metadata_V_TREADY(axis_tx_metadata_tready), // input wire m_axis_tx_metadata_TREADY + .m_axis_tx_metadata_V_TDATA(axis_tx_metadata_tdata), // output wire [15 : 0] m_axis_tx_metadata_TDATA + .s_axis_listen_port_status_V_TVALID(axis_listen_port_status_tvalid),//axis_listen_port_status_tvalid), // input wire s_axis_listen_port_status_TVALID + .s_axis_listen_port_status_V_TREADY(axis_listen_port_status_tready),//axis_listen_port_status_tready), // output wire s_axis_listen_port_status_TREADY + .s_axis_listen_port_status_V_TDATA(axis_listen_port_status_tdata),//axis_listen_port_status_tdata), // input wire [7 : 0] s_axis_listen_port_status_TDATA + .s_axis_notifications_V_TVALID(axis_notifications_tvalid), // input wire s_axis_notifications_TVALID + .s_axis_notifications_V_TREADY(axis_notifications_tready), // output wire s_axis_notifications_TREADY + .s_axis_notifications_V_TDATA(axis_notifications_tdata), // input wire [87 : 0] s_axis_notifications_TDATA + .s_axis_open_status_V_TVALID(axis_open_status_tvalid), // input wire s_axis_open_status_TVALID + .s_axis_open_status_V_TREADY(axis_open_status_tready), // output wire s_axis_open_status_TREADY + .s_axis_open_status_V_TDATA(axis_open_status_tdata), // input wire [23 : 0] s_axis_open_status_TDATA + .s_axis_rx_data_TVALID(axis_rx_data_tvalid), // input wire s_axis_rx_data_TVALID + .s_axis_rx_data_TREADY(axis_rx_data_tready), // output wire s_axis_rx_data_TREADY + .s_axis_rx_data_TDATA(axis_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA + .s_axis_rx_data_TKEEP(axis_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP + .s_axis_rx_data_TLAST(axis_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST + .s_axis_rx_metadata_V_V_TVALID(axis_rx_metadata_tvalid), // input wire s_axis_rx_metadata_TVALID + .s_axis_rx_metadata_V_V_TREADY(axis_rx_metadata_tready), // output wire s_axis_rx_metadata_TREADY + .s_axis_rx_metadata_V_V_TDATA(axis_rx_metadata_tdata), // input wire [15 : 0] s_axis_rx_metadata_TDATA + .s_axis_tx_status_V_TVALID(axis_tx_status_tvalid), // input wire s_axis_tx_status_TVALID + .s_axis_tx_status_V_TREADY(axis_tx_status_tready), // output wire s_axis_tx_status_TREADY + .s_axis_tx_status_V_TDATA(axis_tx_status_tdata), // input wire [23 : 0] s_axis_tx_status_TDATA + .ap_clk(aclk), // input wire aclk + .ap_rst_n(aresetn) // input wire aresetn + );*/ + + + `ifdef ECHO_SERVER + echo_server_application_ip echo_server ( + .m_axis_close_connection_TVALID(axis_close_connection_tvalid), // output wire m_axis_close_connection_TVALID + .m_axis_close_connection_TREADY(axis_close_connection_tready), // input wire m_axis_close_connection_TREADY + .m_axis_close_connection_TDATA(axis_close_connection_tdata), // output wire [15 : 0] m_axis_close_connection_TDATA + .m_axis_listen_port_TVALID(axis_listen_port_tvalid), // output wire m_axis_listen_port_TVALID + .m_axis_listen_port_TREADY(axis_listen_port_tready), // input wire m_axis_listen_port_TREADY + .m_axis_listen_port_TDATA(axis_listen_port_tdata), // output wire [15 : 0] m_axis_listen_port_TDATA + .m_axis_open_connection_TVALID(axis_open_connection_tvalid), // output wire m_axis_open_connection_TVALID + .m_axis_open_connection_TREADY(axis_open_connection_tready), // input wire m_axis_open_connection_TREADY + .m_axis_open_connection_TDATA(axis_open_connection_tdata), // output wire [47 : 0] m_axis_open_connection_TDATA + .m_axis_read_package_TVALID(axis_read_package_tvalid), // output wire m_axis_read_package_TVALID + .m_axis_read_package_TREADY(axis_read_package_tready), // input wire m_axis_read_package_TREADY + .m_axis_read_package_TDATA(axis_read_package_tdata), // output wire [31 : 0] m_axis_read_package_TDATA + .m_axis_tx_data_TVALID(axis_tx_data_tvalid), // output wire m_axis_tx_data_TVALID + .m_axis_tx_data_TREADY(axis_tx_data_tready), // input wire m_axis_tx_data_TREADY + .m_axis_tx_data_TDATA(axis_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA + .m_axis_tx_data_TKEEP(axis_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP + .m_axis_tx_data_TLAST(axis_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST + .m_axis_tx_metadata_TVALID(axis_tx_metadata_tvalid), // output wire m_axis_tx_metadata_TVALID + .m_axis_tx_metadata_TREADY(axis_tx_metadata_tready), // input wire m_axis_tx_metadata_TREADY + .m_axis_tx_metadata_TDATA(axis_tx_metadata_tdata), // output wire [15 : 0] m_axis_tx_metadata_TDATA + .s_axis_listen_port_status_TVALID(axis_listen_port_status_tvalid), // input wire s_axis_listen_port_status_TVALID + .s_axis_listen_port_status_TREADY(axis_listen_port_status_tready), // output wire s_axis_listen_port_status_TREADY + .s_axis_listen_port_status_TDATA(axis_listen_port_status_tdata), // input wire [7 : 0] s_axis_listen_port_status_TDATA + .s_axis_notifications_TVALID(axis_notifications_tvalid), // input wire s_axis_notifications_TVALID + .s_axis_notifications_TREADY(axis_notifications_tready), // output wire s_axis_notifications_TREADY + .s_axis_notifications_TDATA(axis_notifications_tdata), // input wire [87 : 0] s_axis_notifications_TDATA + .s_axis_open_status_TVALID(axis_open_status_tvalid), // input wire s_axis_open_status_TVALID + .s_axis_open_status_TREADY(axis_open_status_tready), // output wire s_axis_open_status_TREADY + .s_axis_open_status_TDATA(axis_open_status_tdata), // input wire [23 : 0] s_axis_open_status_TDATA + .s_axis_rx_data_TVALID(axis_rx_data_tvalid), // input wire s_axis_rx_data_TVALID + .s_axis_rx_data_TREADY(axis_rx_data_tready), // output wire s_axis_rx_data_TREADY + .s_axis_rx_data_TDATA(axis_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA + .s_axis_rx_data_TKEEP(axis_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP + .s_axis_rx_data_TLAST(axis_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST + .s_axis_rx_metadata_TVALID(axis_rx_metadata_tvalid), // input wire s_axis_rx_metadata_TVALID + .s_axis_rx_metadata_TREADY(axis_rx_metadata_tready), // output wire s_axis_rx_metadata_TREADY + .s_axis_rx_metadata_TDATA(axis_rx_metadata_tdata), // input wire [15 : 0] s_axis_rx_metadata_TDATA + .s_axis_tx_status_TVALID(axis_tx_status_tvalid), // input wire s_axis_tx_status_TVALID + .s_axis_tx_status_TREADY(axis_tx_status_tready), // output wire s_axis_tx_status_TREADY + .s_axis_tx_status_TDATA(axis_tx_status_tdata), // input wire [23 : 0] s_axis_tx_status_TDATA + .aclk(aclk), // input wire aclk + .aresetn(aresetn) // input wire aresetn + ); + `endif + + `ifdef IPERF_CLIENT + wire runExperiment; + wire dualMode; + wire[7:0] noOfConnections; + wire[7:0] pkgWordCount; + + vio_iperf vio_iperf_client_inst ( + .clk(aclk), // input wire clk + .probe_out0(runExperiment), // output wire [0 : 0] probe_out0 + .probe_out1(dualMode), // output wire [0 : 0] probe_out1 + .probe_out2(noOfConnections), // output wire [7 : 0] probe_out2 + .probe_out3(pkgWordCount) // output wire [7 : 0] probe_out3 + ); + + iperf_client_ip iperf_client ( + .m_axis_close_connection_TVALID(axis_close_connection_tvalid), // output wire m_axis_close_connection_TVALID + .m_axis_close_connection_TREADY(axis_close_connection_tready), // input wire m_axis_close_connection_TREADY + .m_axis_close_connection_TDATA(axis_close_connection_tdata), // output wire [15 : 0] m_axis_close_connection_TDATA + .m_axis_listen_port_TVALID(axis_listen_port_tvalid), // output wire m_axis_listen_port_TVALID + .m_axis_listen_port_TREADY(axis_listen_port_tready), // input wire m_axis_listen_port_TREADY + .m_axis_listen_port_TDATA(axis_listen_port_tdata), // output wire [15 : 0] m_axis_listen_port_TDATA + .m_axis_open_connection_TVALID(axis_open_connection_tvalid), // output wire m_axis_open_connection_TVALID + .m_axis_open_connection_TREADY(axis_open_connection_tready), // input wire m_axis_open_connection_TREADY + .m_axis_open_connection_TDATA(axis_open_connection_tdata), // output wire [47 : 0] m_axis_open_connection_TDATA + .m_axis_read_package_TVALID(axis_read_package_tvalid), // output wire m_axis_read_package_TVALID + .m_axis_read_package_TREADY(axis_read_package_tready), // input wire m_axis_read_package_TREADY + .m_axis_read_package_TDATA(axis_read_package_tdata), // output wire [31 : 0] m_axis_read_package_TDATA + .m_axis_tx_data_TVALID(axis_tx_data_tvalid), // output wire m_axis_tx_data_TVALID + .m_axis_tx_data_TREADY(axis_tx_data_tready), // input wire m_axis_tx_data_TREADY + .m_axis_tx_data_TDATA(axis_tx_data_tdata), // output wire [63 : 0] m_axis_tx_data_TDATA + .m_axis_tx_data_TKEEP(axis_tx_data_tkeep), // output wire [7 : 0] m_axis_tx_data_TKEEP + .m_axis_tx_data_TLAST(axis_tx_data_tlast), // output wire [0 : 0] m_axis_tx_data_TLAST + .m_axis_tx_metadata_TVALID(axis_tx_metadata_tvalid), // output wire m_axis_tx_metadata_TVALID + .m_axis_tx_metadata_TREADY(axis_tx_metadata_tready), // input wire m_axis_tx_metadata_TREADY + .m_axis_tx_metadata_TDATA(axis_tx_metadata_tdata), // output wire [15 : 0] m_axis_tx_metadata_TDATA + .s_axis_listen_port_status_TVALID(axis_listen_port_status_tvalid), // input wire s_axis_listen_port_status_TVALID + .s_axis_listen_port_status_TREADY(axis_listen_port_status_tready), // output wire s_axis_listen_port_status_TREADY + .s_axis_listen_port_status_TDATA(axis_listen_port_status_tdata), // input wire [7 : 0] s_axis_listen_port_status_TDATA + .s_axis_notifications_TVALID(axis_notifications_tvalid), // input wire s_axis_notifications_TVALID + .s_axis_notifications_TREADY(axis_notifications_tready), // output wire s_axis_notifications_TREADY + .s_axis_notifications_TDATA(axis_notifications_tdata), // input wire [87 : 0] s_axis_notifications_TDATA + .s_axis_open_status_TVALID(axis_open_status_tvalid), // input wire s_axis_open_status_TVALID + .s_axis_open_status_TREADY(axis_open_status_tready), // output wire s_axis_open_status_TREADY + .s_axis_open_status_TDATA(axis_open_status_tdata), // input wire [23 : 0] s_axis_open_status_TDATA + .s_axis_rx_data_TVALID(axis_rx_data_tvalid), // input wire s_axis_rx_data_TVALID + .s_axis_rx_data_TREADY(axis_rx_data_tready), // output wire s_axis_rx_data_TREADY + .s_axis_rx_data_TDATA(axis_rx_data_tdata), // input wire [63 : 0] s_axis_rx_data_TDATA + .s_axis_rx_data_TKEEP(axis_rx_data_tkeep), // input wire [7 : 0] s_axis_rx_data_TKEEP + .s_axis_rx_data_TLAST(axis_rx_data_tlast), // input wire [0 : 0] s_axis_rx_data_TLAST + .s_axis_rx_metadata_TVALID(axis_rx_metadata_tvalid), // input wire s_axis_rx_metadata_TVALID + .s_axis_rx_metadata_TREADY(axis_rx_metadata_tready), // output wire s_axis_rx_metadata_TREADY + .s_axis_rx_metadata_TDATA(axis_rx_metadata_tdata), // input wire [15 : 0] s_axis_rx_metadata_TDATA + .s_axis_tx_status_TVALID(axis_tx_status_tvalid), // input wire s_axis_tx_status_TVALID + .s_axis_tx_status_TREADY(axis_tx_status_tready), // output wire s_axis_tx_status_TREADY + .s_axis_tx_status_TDATA(axis_tx_status_tdata), // input wire [23 : 0] s_axis_tx_status_TDATA + + //Client only + .runExperiment_V(runExperiment | button_west), + .dualModeEn_V(dualMode), // input wire [0 : 0] dualModeEn_V + .useConn_V(noOfConnections), // input wire [7 : 0] useConn_V + .pkgWordCount_V(pkgWordCount), // input wire [7 : 0] pkgWordCount_V + .regIpAddress0_V(32'h0B01D40A), // input wire [31 : 0] regIpAddress1_V + .regIpAddress1_V(32'h0B01D40A), // input wire [31 : 0] regIpAddress1_V + .regIpAddress2_V(32'h0B01D40A), // input wire [31 : 0] regIpAddress1_V + .regIpAddress3_V(32'h0B01D40A), // input wire [31 : 0] regIpAddress1_V + .aclk(aclk), // input wire aclk + .aresetn(aresetn) // input wire aresetn + ); + `endif + + /* + * UDP Application Module + */ + `ifdef UDP + wire runUdpExperiment; + + vio_udp_iperf_client vio_udp_iperf_client_inst ( + .clk(aclk), // input wire clk + .probe_out0(runUdpExperiment) // output wire [0 : 0] probe_out0 + ); + + reg runIperfUdp; + reg[7:0] packetGap; + always @(posedge aclk) begin + if (~aresetn) begin + runIperfUdp <= 0; + packetGap <= 0; + end + else begin + runIperfUdp <= 0; + if (button_north) begin + packetGap <= 0; + runIperfUdp <= 1; + end + if (button_center) begin + packetGap <= 1; + runIperfUdp <= 1; + end + if (button_south) begin + packetGap <= 9; + runIperfUdp <= 1; + end + end + end + + iperf_udp_client_ip iperf_udp_client_inst ( + .aclk(aclk), // input wire aclk + .aresetn(aresetn), // input wire aresetn + .runExperiment_V(runUdpExperiment | runIperfUdp), // input wire [0 : 0] runExperiment_V + .regPacketGap_V(packetGap), + //.regMyIpAddress_V(32'h02D4010B), // input wire [31 : 0] regMyIpAddress_V + .regTargetIpAddress_V({target_ip_address, target_ip_address, target_ip_address, target_ip_address}), // input wire [31 : 0] regTargetIpAddress_V + + .s_axis_rx_metadata_TVALID(axis_rx_udp_metadata_tvalid), + .s_axis_rx_metadata_TREADY(axis_rx_udp_metadata_tready), + .s_axis_rx_metadata_TDATA(axis_rx_udp_metadata_tdata), + .s_axis_rx_data_TVALID(axis_rx_udp_data_tvalid), + .s_axis_rx_data_TREADY(axis_rx_udp_data_tready), + .s_axis_rx_data_TDATA(axis_rx_udp_data_tdata), + .s_axis_rx_data_TKEEP(axis_rx_udp_data_tkeep), + .s_axis_rx_data_TLAST(axis_rx_udp_data_tlast), + + .m_axis_tx_metadata_TVALID(axis_tx_udp_metadata_tvalid), + .m_axis_tx_metadata_TREADY(axis_tx_udp_metadata_tready), + .m_axis_tx_metadata_TDATA(axis_tx_udp_metadata_tdata), + .m_axis_tx_data_TVALID(axis_tx_udp_data_tvalid), + .m_axis_tx_data_TREADY(axis_tx_udp_data_tready), + .m_axis_tx_data_TDATA(axis_tx_udp_data_tdata), + .m_axis_tx_data_TKEEP(axis_tx_udp_data_tkeep), + .m_axis_tx_data_TLAST(axis_tx_udp_data_tlast) + ); + `endif -reg app_start; -always @(posedge axi_clk) -begin - if (aresetn == 0) begin - app_start <= 0; - end - else begin - app_start <= 1;//1; - end -end /* - * Application Module + * DDR MEMORY */ -//echo_server_application_ip echo_server -/* -iperf_ip iperf_server -//iperf_client_ip iperf_client -( -.m_axis_listen_port_TVALID(axis_listen_port_TVALID), -.m_axis_listen_port_TREADY(axis_listen_port_TREADY), -.m_axis_listen_port_TDATA(axis_listen_port_TDATA), -//.m_axis_close_port_TVALID(axis_close_port_TVALID), -//.m_axis_close_port_TREADY(axis_close_port_TREADY), -//.m_axis_close_port_TDATA(axis_close_port_TDATA), -.m_axis_close_connection_TVALID(axis_close_connection_TVALID), -.m_axis_close_connection_TREADY(axis_close_connection_TREADY), -.m_axis_close_connection_TDATA(axis_close_connection_TDATA), -.m_axis_open_connection_TVALID(axis_open_connection_TVALID), -.m_axis_open_connection_TREADY(axis_open_connection_TREADY), -.m_axis_open_connection_TDATA(axis_open_connection_TDATA), -.m_axis_read_package_TVALID(axis_read_package_TVALID), -.m_axis_read_package_TREADY(axis_read_package_TREADY), -.m_axis_read_package_TDATA(axis_read_package_TDATA), -.m_axis_tx_data_TVALID(axis_tx_data_TVALID), -.m_axis_tx_data_TREADY(axis_tx_data_TREADY), -.m_axis_tx_data_TDATA(axis_tx_data_TDATA), -.m_axis_tx_data_TKEEP(axis_tx_data_TKEEP), -.m_axis_tx_data_TLAST(axis_tx_data_TLAST), -.m_axis_tx_metadata_TVALID(axis_tx_metadata_TVALID), -.m_axis_tx_metadata_TREADY(axis_tx_metadata_TREADY), -.m_axis_tx_metadata_TDATA(axis_tx_metadata_TDATA), -.s_axis_listen_port_status_TVALID(axis_listen_port_status_TVALID), -.s_axis_listen_port_status_TREADY(axis_listen_port_status_TREADY), -.s_axis_listen_port_status_TDATA(axis_listen_port_status_TDATA), -.s_axis_notifications_TVALID(axis_notifications_TVALID), -.s_axis_notifications_TREADY(axis_notifications_TREADY), -.s_axis_notifications_TDATA(axis_notifications_TDATA), -.s_axis_open_status_TVALID(axis_open_status_TVALID), -.s_axis_open_status_TREADY(axis_open_status_TREADY), -.s_axis_open_status_TDATA(axis_open_status_TDATA), -.s_axis_rx_data_TVALID(axis_rx_data_TVALID), -.s_axis_rx_data_TREADY(axis_rx_data_TREADY), -.s_axis_rx_data_TDATA(axis_rx_data_TDATA), -.s_axis_rx_data_TKEEP(axis_rx_data_TKEEP), -.s_axis_rx_data_TLAST(axis_rx_data_TLAST), -.s_axis_rx_metadata_TVALID(axis_rx_metadata_TVALID), -.s_axis_rx_metadata_TREADY(axis_rx_metadata_TREADY), -.s_axis_rx_metadata_TDATA(axis_rx_metadata_TDATA), -.s_axis_tx_status_TVALID(axis_tx_status_TVALID), -.s_axis_tx_status_TREADY(axis_tx_status_TREADY), -.s_axis_tx_status_TDATA(axis_tx_status_TDATA), - -//Client only -//.runExperiment_V(runExperiment), -//.useConn_V(8'h01), - -.aclk(axi_clk), // input aclk -.aresetn(aresetn), // input aresetn -.ap_start(app_start), // input ap_start -.ap_ready(), // output ap_ready -.ap_done(), // output ap_done -.ap_idle() // output ap_idle -);*/ - -//wire runExperiment; -//wire dualMode; -//wire[7:0] noOfConnections; -//wire[7:0] pkgWordCount; - -reg ap_start; -always@( posedge axi_clk) -begin - if (aresetn == 0) - ap_start = 0; - else - ap_start = 1; -end - -echo_server_application_ip myEchoServer ( - /* .ap_start(ap_start), // input wire ap_start - .ap_ready(), // output wire ap_ready - .ap_done(), // output wire ap_done - .ap_idle(), // output wire ap_idle*/ - .m_axis_close_connection_TVALID(axis_close_connection_TVALID), // output wire m_axis_close_connection_TVALID - .m_axis_close_connection_TREADY(axis_close_connection_TREADY), // input wire m_axis_close_connection_TREADY - .m_axis_close_connection_TDATA(axis_close_connection_TDATA), // output wire [15 : 0] m_axis_close_connection_TDATA - .m_axis_listen_port_TVALID(axis_listen_port_TVALID), // output wire m_axis_listen_port_TVALID - .m_axis_listen_port_TREADY(axis_listen_port_TREADY), // input wire m_axis_listen_port_TREADY - .m_axis_listen_port_TDATA(axis_listen_port_TDATA), // output wire [15 : 0] m_axis_listen_port_TDATA - .m_axis_open_connection_TVALID(axis_open_connection_TVALID), // output wire m_axis_open_connection_TVALID - .m_axis_open_connection_TREADY(axis_open_connection_TREADY), // input wire m_axis_open_connection_TREADY - .m_axis_open_connection_TDATA(axis_open_connection_TDATA), // output wire [47 : 0] m_axis_open_connection_TDATA - .m_axis_read_package_TVALID(axis_read_package_TVALID), // output wire m_axis_read_package_TVALID - .m_axis_read_package_TREADY(axis_read_package_TREADY), // input wire m_axis_read_package_TREADY - .m_axis_read_package_TDATA(axis_read_package_TDATA), // output wire [31 : 0] m_axis_read_package_TDATA - .m_axis_tx_data_TVALID(axis_tx_data_TVALID), // output wire m_axis_tx_data_TVALID - .m_axis_tx_data_TREADY(axis_tx_data_TREADY), // input wire m_axis_tx_data_TREADY - .m_axis_tx_data_TDATA(axis_tx_data_TDATA), // output wire [63 : 0] m_axis_tx_data_TDATA - .m_axis_tx_data_TKEEP(axis_tx_data_TKEEP), // output wire [7 : 0] m_axis_tx_data_TKEEP - .m_axis_tx_data_TLAST(axis_tx_data_TLAST), // output wire [0 : 0] m_axis_tx_data_TLAST - .m_axis_tx_metadata_TVALID(axis_tx_metadata_TVALID), // output wire m_axis_tx_metadata_TVALID - .m_axis_tx_metadata_TREADY(axis_tx_metadata_TREADY), // input wire m_axis_tx_metadata_TREADY - .m_axis_tx_metadata_TDATA(axis_tx_metadata_TDATA), // output wire [15 : 0] m_axis_tx_metadata_TDATA - .s_axis_listen_port_status_TVALID(axis_listen_port_status_TVALID), // input wire s_axis_listen_port_status_TVALID - .s_axis_listen_port_status_TREADY(axis_listen_port_status_TREADY), // output wire s_axis_listen_port_status_TREADY - .s_axis_listen_port_status_TDATA(axis_listen_port_status_TDATA), // input wire [7 : 0] s_axis_listen_port_status_TDATA - .s_axis_notifications_TVALID(axis_notifications_TVALID), // input wire s_axis_notifications_TVALID - .s_axis_notifications_TREADY(axis_notifications_TREADY), // output wire s_axis_notifications_TREADY - .s_axis_notifications_TDATA(axis_notifications_TDATA), // input wire [87 : 0] s_axis_notifications_TDATA - .s_axis_open_status_TVALID(axis_open_status_TVALID), // input wire s_axis_open_status_TVALID - .s_axis_open_status_TREADY(axis_open_status_TREADY), // output wire s_axis_open_status_TREADY - .s_axis_open_status_TDATA(axis_open_status_TDATA), // input wire [23 : 0] s_axis_open_status_TDATA - .s_axis_rx_data_TVALID(axis_rx_data_TVALID), // input wire s_axis_rx_data_TVALID - .s_axis_rx_data_TREADY(axis_rx_data_TREADY), // output wire s_axis_rx_data_TREADY - .s_axis_rx_data_TDATA(axis_rx_data_TDATA), // input wire [63 : 0] s_axis_rx_data_TDATA - .s_axis_rx_data_TKEEP(axis_rx_data_TKEEP), // input wire [7 : 0] s_axis_rx_data_TKEEP - .s_axis_rx_data_TLAST(axis_rx_data_TLAST), // input wire [0 : 0] s_axis_rx_data_TLAST - .s_axis_rx_metadata_TVALID(axis_rx_metadata_TVALID), // input wire s_axis_rx_metadata_TVALID - .s_axis_rx_metadata_TREADY(axis_rx_metadata_TREADY), // output wire s_axis_rx_metadata_TREADY - .s_axis_rx_metadata_TDATA(axis_rx_metadata_TDATA), // input wire [15 : 0] s_axis_rx_metadata_TDATA - .s_axis_tx_status_TVALID(axis_tx_status_TVALID), // input wire s_axis_tx_status_TVALID - .s_axis_tx_status_TREADY(axis_tx_status_TREADY), // output wire s_axis_tx_status_TREADY - .s_axis_tx_status_TDATA(axis_tx_status_TDATA), // input wire [23 : 0] s_axis_tx_status_TDATA - .aclk(axi_clk), // input wire aclk - .aresetn(aresetn) // input wire aresetn -); -/* -iperf_client_0 iperf_client_inst ( - .runExperiment_V(runExperiment), // input wire [0 : 0] runExperiment_V - .dualModeEn_V(dualMode), // input wire [0 : 0] dualModeEn_V - .useConn_V(noOfConnections), // input wire [7 : 0] useConn_V - .pkgWordCount_V(pkgWordCount), // input wire [7 : 0] pkgWordCount_V - .regIpAddress1_V(32'h01010114), // input wire [31 : 0] regIpAddress1_V - .m_axis_close_connection_TVALID(axis_close_connection_TVALID), // output wire m_axis_close_connection_TVALID - .m_axis_close_connection_TREADY(axis_close_connection_TREADY), // input wire m_axis_close_connection_TREADY - .m_axis_close_connection_TDATA(axis_close_connection_TDATA), // output wire [15 : 0] m_axis_close_connection_TDATA - .m_axis_listen_port_TVALID(axis_listen_port_TVALID), // output wire m_axis_listen_port_TVALID - .m_axis_listen_port_TREADY(axis_listen_port_TREADY), // input wire m_axis_listen_port_TREADY - .m_axis_listen_port_TDATA(axis_listen_port_TDATA), // output wire [15 : 0] m_axis_listen_port_TDATA - .m_axis_open_connection_TVALID(axis_open_connection_TVALID), // output wire m_axis_open_connection_TVALID - .m_axis_open_connection_TREADY(axis_open_connection_TREADY), // input wire m_axis_open_connection_TREADY - .m_axis_open_connection_TDATA(axis_open_connection_TDATA), // output wire [47 : 0] m_axis_open_connection_TDATA - .m_axis_read_package_TVALID(axis_read_package_TVALID), // output wire m_axis_read_package_TVALID - .m_axis_read_package_TREADY(axis_read_package_TREADY), // input wire m_axis_read_package_TREADY - .m_axis_read_package_TDATA(axis_read_package_TDATA), // output wire [31 : 0] m_axis_read_package_TDATA - .m_axis_tx_data_TVALID(axis_tx_data_TVALID), // output wire m_axis_tx_data_TVALID - .m_axis_tx_data_TREADY(axis_tx_data_TREADY), // input wire m_axis_tx_data_TREADY - .m_axis_tx_data_TDATA(axis_tx_data_TDATA), // output wire [63 : 0] m_axis_tx_data_TDATA - .m_axis_tx_data_TKEEP(axis_tx_data_TKEEP), // output wire [7 : 0] m_axis_tx_data_TKEEP - .m_axis_tx_data_TLAST(axis_tx_data_TLAST), // output wire [0 : 0] m_axis_tx_data_TLAST - .m_axis_tx_metadata_TVALID(axis_tx_metadata_TVALID), // output wire m_axis_tx_metadata_TVALID - .m_axis_tx_metadata_TREADY(axis_tx_metadata_TREADY), // input wire m_axis_tx_metadata_TREADY - .m_axis_tx_metadata_TDATA(axis_tx_metadata_TDATA), // output wire [15 : 0] m_axis_tx_metadata_TDATA - .s_axis_listen_port_status_TVALID(axis_listen_port_status_TVALID), // input wire s_axis_listen_port_status_TVALID - .s_axis_listen_port_status_TREADY(axis_listen_port_status_TREADY), // output wire s_axis_listen_port_status_TREADY - .s_axis_listen_port_status_TDATA(axis_listen_port_status_TDATA), // input wire [7 : 0] s_axis_listen_port_status_TDATA - .s_axis_notifications_TVALID(axis_notifications_TVALID), // input wire s_axis_notifications_TVALID - .s_axis_notifications_TREADY(axis_notifications_TREADY), // output wire s_axis_notifications_TREADY - .s_axis_notifications_TDATA(axis_notifications_TDATA), // input wire [87 : 0] s_axis_notifications_TDATA - .s_axis_open_status_TVALID(axis_open_status_TVALID), // input wire s_axis_open_status_TVALID - .s_axis_open_status_TREADY(axis_open_status_TREADY), // output wire s_axis_open_status_TREADY - .s_axis_open_status_TDATA(axis_open_status_TDATA), // input wire [23 : 0] s_axis_open_status_TDATA - .s_axis_rx_data_TVALID(axis_rx_data_TVALID), // input wire s_axis_rx_data_TVALID - .s_axis_rx_data_TREADY(axis_rx_data_TREADY), // output wire s_axis_rx_data_TREADY - .s_axis_rx_data_TDATA(axis_rx_data_TDATA), // input wire [63 : 0] s_axis_rx_data_TDATA - .s_axis_rx_data_TKEEP(axis_rx_data_TKEEP), // input wire [7 : 0] s_axis_rx_data_TKEEP - .s_axis_rx_data_TLAST(axis_rx_data_TLAST), // input wire [0 : 0] s_axis_rx_data_TLAST - .s_axis_rx_metadata_TVALID(axis_rx_metadata_TVALID), // input wire s_axis_rx_metadata_TVALID - .s_axis_rx_metadata_TREADY(axis_rx_metadata_TREADY), // output wire s_axis_rx_metadata_TREADY - .s_axis_rx_metadata_TDATA(axis_rx_metadata_TDATA), // input wire [15 : 0] s_axis_rx_metadata_TDATA - .s_axis_tx_status_TVALID(axis_tx_status_TVALID), // input wire s_axis_tx_status_TVALID - .s_axis_tx_status_TREADY(axis_tx_status_TREADY), // output wire s_axis_tx_status_TREADY - .s_axis_tx_status_TDATA(axis_tx_status_TDATA), // input wire [23 : 0] s_axis_tx_status_TDATA - .aclk(axi_clk), // input wire aclk - .aresetn(aresetn) // input wire aresetn -);*/ -/* -vio_ip myVIO ( - .clk(axi_clk), // input wire clk - .probe_in0(), // input wire [0 : 0] probe_in0 - .probe_out0(runExperiment), // output wire [0 : 0] probe_out0 - .probe_out1(dualMode), // output wire [0 : 0] probe_out1 - .probe_out2(noOfConnections), // output wire [7 : 0] probe_out2 - .probe_out3(pkgWordCount) // output wire [7 : 0] probe_out3 -);*/ - -udpLoopback_0 udpLoopback_inst ( - .lbPortOpenReplyIn_TVALID(mux2shim_portOpenReplyIn_V_V_TVALID), // input wire portOpenReplyIn_TVALID - .lbPortOpenReplyIn_TREADY(mux2shim_portOpenReplyIn_V_V_TREADY), // output wire portOpenReplyIn_TREADY - .lbPortOpenReplyIn_TDATA(mux2shim_portOpenReplyIn_V_V_TDATA), // input wire [7 : 0] portOpenReplyIn_TDATA - .lbRequestPortOpenOut_TVALID(shim2mux_requestPortOpenOut_V_TVALID), // output wire requestPortOpenOut_TVALID - .lbRequestPortOpenOut_TREADY(shim2mux_requestPortOpenOut_V_TREADY), // input wire requestPortOpenOut_TREADY - .lbRequestPortOpenOut_TDATA(shim2mux_requestPortOpenOut_V_TDATA), // output wire [15 : 0] requestPortOpenOut_TDATA - .lbRxDataIn_TVALID(mux2shimRxDataIn_TVALID), // input wire rxDataIn_TVALID - .lbRxDataIn_TREADY(mux2shimRxDataIn_TREADY), // output wire rxDataIn_TREADY - .lbRxDataIn_TDATA(mux2shimRxDataIn_TDATA), // input wire [63 : 0] rxDataIn_TDATA - .lbRxDataIn_TKEEP(mux2shimRxDataIn_TKEEP), // input wire [7 : 0] rxDataIn_TKEEP - .lbRxDataIn_TLAST(mux2shimRxDataIn_TLAST), // input wire [0 : 0] rxDataIn_TLAST - .lbRxMetadataIn_TVALID(mux2shimRxMetadataIn_V_TVALID), // input wire rxMetadataIn_TVALID - .lbRxMetadataIn_TREADY(mux2shimRxMetadataIn_V_TREADY), // output wire rxMetadataIn_TREADY - .lbRxMetadataIn_TDATA(mux2shimRxMetadataIn_V_TDATA), // input wire [95 : 0] rxMetadataIn_TDATA - .lbTxDataOut_TVALID(shim2mux_TVALID), // output wire txDataOut_TVALID - .lbTxDataOut_TREADY(shim2mux_TREADY), // input wire txDataOut_TREADY - .lbTxDataOut_TDATA(shim2mux_TDATA), // output wire [63 : 0] txDataOut_TDATA - .lbTxDataOut_TKEEP(shim2mux_TKEEP), // output wire [7 : 0] txDataOut_TKEEP - .lbTxDataOut_TLAST(shim2mux_TLAST), // output wire [0 : 0] txDataOut_TLAST - .lbTxLengthOut_TVALID(shim2muxTxLengthOut_V_V_TVALID), // output wire txLengthOut_TVALID - .lbTxLengthOut_TREADY(shim2muxTxLengthOut_V_V_TREADY), // input wire txLengthOut_TREADY - .lbTxLengthOut_TDATA(shim2muxTxLengthOut_V_V_TDATA), // output wire [15 : 0] txLengthOut_TDATA - .lbTxMetadataOut_TVALID(shim2muxTxMetadataOut_V_TVALID), // output wire txMetadataOut_TVALID - .lbTxMetadataOut_TREADY(shim2muxTxMetadataOut_V_TREADY), // input wire txMetadataOut_TREADY - .lbTxMetadataOut_TDATA(shim2muxTxMetadataOut_V_TDATA), // output wire [95 : 0] txMetadataOut_TDATA - .aclk(axi_clk), // input wire aclk - .aresetn(aresetn) // input wire aresetn -); - -//DRAM MEM interface - -//wire clk156_25; -//wire reset156_25_n; wire clk233; wire clk200, clk200_i; wire c0_init_calib_complete; wire c1_init_calib_complete; - -//toe stream interface signals -wire toeTX_s_axis_read_cmd_tvalid; -wire toeTX_s_axis_read_cmd_tready; -wire[71:0] toeTX_s_axis_read_cmd_tdata; -//read status -wire toeTX_m_axis_read_sts_tvalid; -wire toeTX_m_axis_read_sts_tready; -wire[7:0] toeTX_m_axis_read_sts_tdata; -//read stream -wire[63:0] toeTX_m_axis_read_tdata; -wire[7:0] toeTX_m_axis_read_tkeep; -wire toeTX_m_axis_read_tlast; -wire toeTX_m_axis_read_tvalid; -wire toeTX_m_axis_read_tready; - -//write commands -wire toeTX_s_axis_write_cmd_tvalid; -wire toeTX_s_axis_write_cmd_tready; -wire[71:0] toeTX_s_axis_write_cmd_tdata; -//write status -wire toeTX_m_axis_write_sts_tvalid; -wire toeTX_m_axis_write_sts_tready; -wire[31:0] toeTX_m_axis_write_sts_tdata; -//write stream -wire[63:0] toeTX_s_axis_write_tdata; -wire[7:0] toeTX_s_axis_write_tkeep; -wire toeTX_s_axis_write_tlast; -wire toeTX_s_axis_write_tvalid; -wire toeTX_s_axis_write_tready; - -//ht stream interface signals -wire ht_s_axis_read_cmd_tvalid; -wire ht_s_axis_read_cmd_tready; -wire[71:0] ht_s_axis_read_cmd_tdata; -//read status -wire ht_m_axis_read_sts_tvalid; -wire ht_m_axis_read_sts_tready; -wire[7:0] ht_m_axis_read_sts_tdata; -//read stream -wire[511:0] ht_m_axis_read_tdata; -wire[63:0] ht_m_axis_read_tkeep; -wire ht_m_axis_read_tlast; -wire ht_m_axis_read_tvalid; -wire ht_m_axis_read_tready; - -//write commands -wire ht_s_axis_write_cmd_tvalid; -wire ht_s_axis_write_cmd_tready; -wire[71:0] ht_s_axis_write_cmd_tdata; -//write status -wire ht_m_axis_write_sts_tvalid; -wire ht_m_axis_write_sts_tready; -wire[31:0] ht_m_axis_write_sts_tdata; -//write stream -wire[511:0] ht_s_axis_write_tdata; -wire[63:0] ht_s_axis_write_tkeep; -wire ht_s_axis_write_tlast; -wire ht_s_axis_write_tvalid; -wire ht_s_axis_write_tready; - -wire[511:0] ht_s_axis_write_tdata_x; -wire[63:0] ht_s_axis_write_tkeep_x; -wire ht_s_axis_write_tlast_x; -wire ht_s_axis_write_tvalid_x; -wire ht_s_axis_write_tready_x; - -//upd stream interface signals -wire upd_s_axis_read_cmd_tvalid; -wire upd_s_axis_read_cmd_tready; -wire[71:0] upd_s_axis_read_cmd_tdata; -//read status -wire upd_m_axis_read_sts_tvalid; -wire upd_m_axis_read_sts_tready; -wire[7:0] upd_m_axis_read_sts_tdata; -//read stream -wire[511:0] upd_m_axis_read_tdata; -wire[63:0] upd_m_axis_read_tkeep; -wire upd_m_axis_read_tlast; -wire upd_m_axis_read_tvalid; -wire upd_m_axis_read_tready; - -//write commands -wire upd_s_axis_write_cmd_tvalid; -wire upd_s_axis_write_cmd_tready; -wire[71:0] upd_s_axis_write_cmd_tdata; -//write status -wire upd_m_axis_write_sts_tvalid; -wire upd_m_axis_write_sts_tready; -wire[31:0] upd_m_axis_write_sts_tdata; -//write stream -wire[511:0] upd_s_axis_write_tdata; -wire[63:0] upd_s_axis_write_tkeep; -wire upd_s_axis_write_tlast; -wire upd_s_axis_write_tvalid; -wire upd_s_axis_write_tready; - -wire[511:0] upd_s_axis_write_tdata_x; -wire[63:0] upd_s_axis_write_tkeep_x; -wire upd_s_axis_write_tlast_x; -wire upd_s_axis_write_tvalid_x; -wire upd_s_axis_write_tready_x; - wire ddr3_calib_complete, init_calib_complete; -wire toeTX_compare_error, ht_compare_error, upd_compare_error; - -reg rst_n_r1, rst_n_r2, rst_n_r3; -//reg reset156_25_n_r1, reset156_25_n_r2, reset156_25_n_r3; - //registers for crossing clock domains (from 233MHz to 156.25MHz) reg c0_init_calib_complete_r1, c0_init_calib_complete_r2; reg c1_init_calib_complete_r1, c1_init_calib_complete_r2; -//localparam TOE_START_ADDR = 32'd0; -//localparam HT_START_ADDR = 32'd0; -//localparam UPD_START_ADDR = 32'd32; - - //- 212MHz differential clock for 1866Mbps DDR3 controller IBUFGDS #( .DIFF_TERM ("TRUE"), @@ -988,19 +719,8 @@ IBUF clk_212_bufg .O (sys_rst) ); - -//assign clk156_25 = axi_clk; -//assign clk200 = clk_ref_200; - /*always @(posedge axi_clk) begin - reset156_25_n_r1 <= perst_n & pok_dram & network_init; - reset156_25_n_r2 <= reset156_25_n_r1; - reset156_25_n_r3 <= reset156_25_n_r2; - end - - assign reset156_25_n = reset156_25_n_r3; - assign aresetn = reset156_25_n & network_init;*/ -always @(posedge axi_clk) +always @(posedge aclk) if (~aresetn) begin c0_init_calib_complete_r1 <= 1'b0; c0_init_calib_complete_r2 <= 1'b0; @@ -1016,184 +736,10 @@ always @(posedge axi_clk) assign ddr3_calib_complete = c0_init_calib_complete_r2 & c1_init_calib_complete_r2; assign init_calib_complete = ddr3_calib_complete; -/* - * TX Memory Signals - */ -// memory cmd streams -assign toeTX_s_axis_read_cmd_tvalid = axis_txread_cmd_TVALID; -assign axis_txread_cmd_TREADY = toeTX_s_axis_read_cmd_tready; -assign toeTX_s_axis_read_cmd_tdata = axis_txread_cmd_TDATA; -assign toeTX_s_axis_write_cmd_tvalid = axis_txwrite_cmd_TVALID; -assign axis_txwrite_cmd_TREADY = toeTX_s_axis_write_cmd_tready; -assign toeTX_s_axis_write_cmd_tdata = axis_txwrite_cmd_TDATA; -// memory sts streams -assign axis_txread_sts_TVALID = toeTX_m_axis_read_sts_tvalid; -assign toeTX_m_axis_read_sts_tready = 1'b1; -assign axis_txread_sts_TDATA = toeTX_m_axis_read_sts_tdata; -assign axis_txwrite_sts_TVALID = toeTX_m_axis_write_sts_tvalid; -assign toeTX_m_axis_write_sts_tready = axis_txwrite_sts_TREADY; -assign axis_txwrite_sts_TDATA = toeTX_m_axis_write_sts_tdata; -// memory data streams -assign axis_txread_data_TVALID = toeTX_m_axis_read_tvalid; -assign toeTX_m_axis_read_tready = axis_txread_data_TREADY; -assign axis_txread_data_TDATA = toeTX_m_axis_read_tdata; -assign axis_txread_data_TKEEP = toeTX_m_axis_read_tkeep; -assign axis_txread_data_TLAST = toeTX_m_axis_read_tlast; - -assign toeTX_s_axis_write_tvalid = axis_txwrite_data_TVALID; -assign axis_txwrite_data_TREADY = toeTX_s_axis_write_tready; -assign toeTX_s_axis_write_tdata = axis_txwrite_data_TDATA; -assign toeTX_s_axis_write_tkeep = axis_txwrite_data_TKEEP; -assign toeTX_s_axis_write_tlast = axis_txwrite_data_TLAST; - -wire toeRX_s_axis_read_cmd_tvalid; -wire toeRX_s_axis_read_cmd_tready; -wire[71:0] toeRX_s_axis_read_cmd_tdata; -//read status -wire toeRX_m_axis_read_sts_tvalid; -wire toeRX_m_axis_read_sts_tready; -wire[7:0] toeRX_m_axis_read_sts_tdata; -//read stream -wire[63:0] toeRX_m_axis_read_tdata; -wire[7:0] toeRX_m_axis_read_tkeep; -wire toeRX_m_axis_read_tlast; -wire toeRX_m_axis_read_tvalid; -wire toeRX_m_axis_read_tready; - -//write commands -wire toeRX_s_axis_write_cmd_tvalid; -wire toeRX_s_axis_write_cmd_tready; -wire[71:0] toeRX_s_axis_write_cmd_tdata; -//write status -wire toeRX_m_axis_write_sts_tvalid; -wire toeRX_m_axis_write_sts_tready; -wire[7:0] toeRX_m_axis_write_sts_tdata; -//write stream -wire[63:0] toeRX_s_axis_write_tdata; -wire[7:0] toeRX_s_axis_write_tkeep; -wire toeRX_s_axis_write_tlast; -wire toeRX_s_axis_write_tvalid; -wire toeRX_s_axis_write_tready; -wire toeRX_compare_error; -assign toeRX_compare_error = 1'b0; -/* RX Memory Signals - */ -// memory cmd streams -assign toeRX_s_axis_read_cmd_tvalid = axis_rxread_cmd_TVALID; -assign axis_rxread_cmd_TREADY = toeRX_s_axis_read_cmd_tready; -assign toeRX_s_axis_read_cmd_tdata = axis_rxread_cmd_TDATA; -assign toeRX_s_axis_write_cmd_tvalid = axis_rxwrite_cmd_TVALID; -assign axis_rxwrite_cmd_TREADY = toeRX_s_axis_write_cmd_tready; -assign toeRX_s_axis_write_cmd_tdata = axis_rxwrite_cmd_TDATA; -// memory sts streams -assign axis_rxread_sts_TVALID = toeRX_m_axis_read_sts_tvalid; -assign toeRX_m_axis_read_sts_tready = 1'b1; -assign axis_rxread_sts_TDATA = toeRX_m_axis_read_sts_tdata; -assign axis_rxwrite_sts_TVALID = toeRX_m_axis_write_sts_tvalid; -assign toeRX_m_axis_write_sts_tready = axis_rxwrite_sts_TREADY; -assign axis_rxwrite_sts_TDATA = toeRX_m_axis_write_sts_tdata; -// memory data streams -assign axis_rxread_data_TVALID = toeRX_m_axis_read_tvalid; -assign toeRX_m_axis_read_tready = axis_rxread_data_TREADY; -assign axis_rxread_data_TDATA = toeRX_m_axis_read_tdata; -assign axis_rxread_data_TKEEP = toeRX_m_axis_read_tkeep; -assign axis_rxread_data_TLAST = toeRX_m_axis_read_tlast; - -assign toeRX_s_axis_write_tvalid = axis_rxwrite_data_TVALID; -assign axis_rxwrite_data_TREADY = toeRX_s_axis_write_tready; -assign toeRX_s_axis_write_tdata = axis_rxwrite_data_TDATA; -assign toeRX_s_axis_write_tkeep = axis_rxwrite_data_TKEEP; -assign toeRX_s_axis_write_tlast = axis_rxwrite_data_TLAST; - -stream_tg #( - .DATA_WIDTH(512), - .KEEP_WIDTH(64), - .START_ADDR(0), - .START_DATA(8), - .BTT(23'd64), - .DRR(1'b0) -) -ht_stream_tg ( - .aclk(axi_clk), - .aresetn(ddr3_calib_complete), - .write_cmd(ht_s_axis_write_cmd_tdata), - .write_cmd_valid(ht_s_axis_write_cmd_tvalid), - .write_cmd_ready(ht_s_axis_write_cmd_tready), - .write_data(ht_s_axis_write_tdata), - .write_data_valid(ht_s_axis_write_tvalid), - .write_data_ready(ht_s_axis_write_tready), - .write_data_keep(ht_s_axis_write_tkeep), - .write_data_last(ht_s_axis_write_tlast), - .read_cmd(ht_s_axis_read_cmd_tdata), - .read_cmd_valid(ht_s_axis_read_cmd_tvalid), - .read_cmd_ready(ht_s_axis_read_cmd_tready), - .read_data(ht_m_axis_read_tdata), - .read_data_valid(ht_m_axis_read_tvalid), - .read_data_keep(ht_m_axis_read_tkeep), - .read_data_last(ht_m_axis_read_tlast), - .read_data_ready(ht_m_axis_read_tready), - .read_sts_data(ht_m_axis_read_sts_tdata), - .read_sts_valid(ht_m_axis_read_sts_tvalid), - .read_sts_ready(), - .write_sts_data(ht_m_axis_write_sts_tdata), - .write_sts_valid(ht_m_axis_write_sts_tvalid), - .write_sts_ready(), - .compare_error(ht_compare_error) -); - - -stream_tg #( - .DATA_WIDTH(512), - .KEEP_WIDTH(64), - .START_ADDR(128), - .START_DATA(32), - .BTT(23'd64), - .DRR(1'b0) -) -upd_stream_tg ( - .aclk(axi_clk), - .aresetn(ddr3_calib_complete), - .write_cmd(upd_s_axis_write_cmd_tdata), - .write_cmd_valid(upd_s_axis_write_cmd_tvalid), - .write_cmd_ready(upd_s_axis_write_cmd_tready), - .write_data(upd_s_axis_write_tdata), - .write_data_valid(upd_s_axis_write_tvalid), - .write_data_ready(upd_s_axis_write_tready), - .write_data_keep(upd_s_axis_write_tkeep), - .write_data_last(upd_s_axis_write_tlast), - .read_cmd(upd_s_axis_read_cmd_tdata), - .read_cmd_valid(upd_s_axis_read_cmd_tvalid), - .read_cmd_ready(upd_s_axis_read_cmd_tready), - .read_data(upd_m_axis_read_tdata), - .read_data_valid(upd_m_axis_read_tvalid), - .read_data_keep(upd_m_axis_read_tkeep), - .read_data_last(upd_m_axis_read_tlast), - .read_data_ready(upd_m_axis_read_tready), - .read_sts_data(upd_m_axis_read_sts_tdata), - .read_sts_valid(upd_m_axis_read_sts_tvalid), - .read_sts_ready(), - .write_sts_data(upd_m_axis_write_sts_tdata), - .write_sts_valid(upd_m_axis_write_sts_tvalid), - .write_sts_ready(), - .compare_error(upd_compare_error) -); - -assign ht_m_axis_read_sts_tready = 1'b1; -assign ht_m_axis_write_sts_tready = 1'b1; - -assign upd_m_axis_read_sts_tready = 1'b1; -assign upd_m_axis_write_sts_tready = 1'b1; - -mem_inf #( - .C0_SIMULATION("FALSE"), - .C1_SIMULATION("FALSE"), - .C0_SIM_BYPASS_INIT_CAL("OFF"), - .C1_SIM_BYPASS_INIT_CAL("OFF") -) -mem_inf_inst( -.clk156_25(axi_clk), +mem_inf mem_inf_inst( +.clk156_25(aclk), //.reset233_n(reset233_n), //active low reset signal for 233MHz clock domain .reset156_25_n(ddr3_calib_complete), .clk212(clk233), @@ -1245,190 +791,67 @@ mem_inf_inst( .c1_ui_clk(), .c1_init_calib_complete(c1_init_calib_complete), -//toe stream interface signals -.toeTX_s_axis_read_cmd_tvalid(toeTX_s_axis_read_cmd_tvalid), -.toeTX_s_axis_read_cmd_tready(toeTX_s_axis_read_cmd_tready), -.toeTX_s_axis_read_cmd_tdata(toeTX_s_axis_read_cmd_tdata), -//read status -.toeTX_m_axis_read_sts_tvalid(toeTX_m_axis_read_sts_tvalid), -.toeTX_m_axis_read_sts_tready(toeTX_m_axis_read_sts_tready), -.toeTX_m_axis_read_sts_tdata(toeTX_m_axis_read_sts_tdata), -//read stream -.toeTX_m_axis_read_tdata(toeTX_m_axis_read_tdata), -.toeTX_m_axis_read_tkeep(toeTX_m_axis_read_tkeep), -.toeTX_m_axis_read_tlast(toeTX_m_axis_read_tlast), -.toeTX_m_axis_read_tvalid(toeTX_m_axis_read_tvalid), -.toeTX_m_axis_read_tready(toeTX_m_axis_read_tready), - -//write commands -.toeTX_s_axis_write_cmd_tvalid(toeTX_s_axis_write_cmd_tvalid), -.toeTX_s_axis_write_cmd_tready(toeTX_s_axis_write_cmd_tready), -.toeTX_s_axis_write_cmd_tdata(toeTX_s_axis_write_cmd_tdata), -//write status -.toeTX_m_axis_write_sts_tvalid(toeTX_m_axis_write_sts_tvalid), -.toeTX_m_axis_write_sts_tready(toeTX_m_axis_write_sts_tready), -.toeTX_m_axis_write_sts_tdata(toeTX_m_axis_write_sts_tdata), -//write stream -.toeTX_s_axis_write_tdata(toeTX_s_axis_write_tdata), -.toeTX_s_axis_write_tkeep(toeTX_s_axis_write_tkeep), -.toeTX_s_axis_write_tlast(toeTX_s_axis_write_tlast), -.toeTX_s_axis_write_tvalid(toeTX_s_axis_write_tvalid), -.toeTX_s_axis_write_tready(toeTX_s_axis_write_tready), - -.toeRX_s_axis_read_cmd_tvalid(toeRX_s_axis_read_cmd_tvalid), -.toeRX_s_axis_read_cmd_tready(toeRX_s_axis_read_cmd_tready), -.toeRX_s_axis_read_cmd_tdata(toeRX_s_axis_read_cmd_tdata), -//read status -.toeRX_m_axis_read_sts_tvalid(toeRX_m_axis_read_sts_tvalid), -.toeRX_m_axis_read_sts_tready(toeRX_m_axis_read_sts_tready), -.toeRX_m_axis_read_sts_tdata(toeRX_m_axis_read_sts_tdata), -//read stream -.toeRX_m_axis_read_tdata(toeRX_m_axis_read_tdata), -.toeRX_m_axis_read_tkeep(toeRX_m_axis_read_tkeep), -.toeRX_m_axis_read_tlast(toeRX_m_axis_read_tlast), -.toeRX_m_axis_read_tvalid(toeRX_m_axis_read_tvalid), -.toeRX_m_axis_read_tready(toeRX_m_axis_read_tready), - -//write commands -.toeRX_s_axis_write_cmd_tvalid(toeRX_s_axis_write_cmd_tvalid), -.toeRX_s_axis_write_cmd_tready(toeRX_s_axis_write_cmd_tready), -.toeRX_s_axis_write_cmd_tdata(toeRX_s_axis_write_cmd_tdata), -//write status -.toeRX_m_axis_write_sts_tvalid(toeRX_m_axis_write_sts_tvalid), -.toeRX_m_axis_write_sts_tready(toeRX_m_axis_write_sts_tready), -.toeRX_m_axis_write_sts_tdata(toeRX_m_axis_write_sts_tdata), -//write stream -.toeRX_s_axis_write_tdata(toeRX_s_axis_write_tdata), -.toeRX_s_axis_write_tkeep(toeRX_s_axis_write_tkeep), -.toeRX_s_axis_write_tlast(toeRX_s_axis_write_tlast), -.toeRX_s_axis_write_tvalid(toeRX_s_axis_write_tvalid), -.toeRX_s_axis_write_tready(toeRX_s_axis_write_tready), - -//ht stream interface signals -.ht_s_axis_read_cmd_tvalid(ht_s_axis_read_cmd_tvalid), -.ht_s_axis_read_cmd_tready(ht_s_axis_read_cmd_tready), -.ht_s_axis_read_cmd_tdata(ht_s_axis_read_cmd_tdata), -//read status -.ht_m_axis_read_sts_tvalid(ht_m_axis_read_sts_tvalid), -.ht_m_axis_read_sts_tready(ht_m_axis_read_sts_tready), -.ht_m_axis_read_sts_tdata(ht_m_axis_read_sts_tdata), -//read stream -.ht_m_axis_read_tdata(ht_m_axis_read_tdata), -.ht_m_axis_read_tkeep(ht_m_axis_read_tkeep), -.ht_m_axis_read_tlast(ht_m_axis_read_tlast), -.ht_m_axis_read_tvalid(ht_m_axis_read_tvalid), -.ht_m_axis_read_tready(ht_m_axis_read_tready), - -//write commands -.ht_s_axis_write_cmd_tvalid(ht_s_axis_write_cmd_tvalid), -.ht_s_axis_write_cmd_tready(ht_s_axis_write_cmd_tready), -.ht_s_axis_write_cmd_tdata(ht_s_axis_write_cmd_tdata), -//write status -.ht_m_axis_write_sts_tvalid(ht_m_axis_write_sts_tvalid), -.ht_m_axis_write_sts_tready(ht_m_axis_write_sts_tready), -.ht_m_axis_write_sts_tdata(ht_m_axis_write_sts_tdata), -//write stream -.ht_s_axis_write_tdata(ht_s_axis_write_tdata), -.ht_s_axis_write_tkeep(ht_s_axis_write_tkeep), -.ht_s_axis_write_tlast(ht_s_axis_write_tlast), -.ht_s_axis_write_tvalid(ht_s_axis_write_tvalid), -.ht_s_axis_write_tready(ht_s_axis_write_tready), - -//upd stream interface signals -.upd_s_axis_read_cmd_tvalid(upd_s_axis_read_cmd_tvalid), -.upd_s_axis_read_cmd_tready(upd_s_axis_read_cmd_tready), -.upd_s_axis_read_cmd_tdata(upd_s_axis_read_cmd_tdata), -//read status -.upd_m_axis_read_sts_tvalid(upd_m_axis_read_sts_tvalid), -.upd_m_axis_read_sts_tready(upd_m_axis_read_sts_tready), -.upd_m_axis_read_sts_tdata(upd_m_axis_read_sts_tdata), -//read stream -.upd_m_axis_read_tdata(upd_m_axis_read_tdata), -.upd_m_axis_read_tkeep(upd_m_axis_read_tkeep), -.upd_m_axis_read_tlast(upd_m_axis_read_tlast), -.upd_m_axis_read_tvalid(upd_m_axis_read_tvalid), -.upd_m_axis_read_tready(upd_m_axis_read_tready), - -//write commands -.upd_s_axis_write_cmd_tvalid(upd_s_axis_write_cmd_tvalid), -.upd_s_axis_write_cmd_tready(upd_s_axis_write_cmd_tready), -.upd_s_axis_write_cmd_tdata(upd_s_axis_write_cmd_tdata), -//write status -.upd_m_axis_write_sts_tvalid(upd_m_axis_write_sts_tvalid), -.upd_m_axis_write_sts_tready(upd_m_axis_write_sts_tready), -.upd_m_axis_write_sts_tdata(upd_m_axis_write_sts_tdata), -//write stream -.upd_s_axis_write_tdata(upd_s_axis_write_tdata), -.upd_s_axis_write_tkeep(upd_s_axis_write_tkeep), -.upd_s_axis_write_tlast(upd_s_axis_write_tlast), -.upd_s_axis_write_tvalid(upd_s_axis_write_tvalid), -.upd_s_axis_write_tready(upd_s_axis_write_tready) -); - -/*assign usr_led[0] = init_calib_complete; -assign usr_led[1] = perst_n & pok_dram; -assign usr_led[2] = app_start; -assign usr_led[5:3] = 0;*/ -/* -always@ (posedge axi_clk) -begin - if (toeRX_s_axis_write_cmd_tvalid == 1) - wrCmdCounter = wrCmdCounter + 1; - -end - -always@ (posedge axi_clk) -begin - if (toeRX_s_axis_read_cmd_tvalid == 1) - rdCmdCounter = rdCmdCounter + 1; - -end - -always@ (posedge axi_clk) -begin - if (axis_read_package_TVALID == 1) - rdAppCounter = rdAppCounter + 1; - -end*/ - -/*dataIla rxWrIla ( - .clk(axi_clk), // input wire clk - .probe0(axis_rxwrite_data_TREADY), // input wire [0:0] probe0 - .probe1(axis_rxwrite_data_TVALID), // input wire [0:0] probe1 - .probe2(axis_rxwrite_data_TLAST), // input wire [0:0] probe2 - .probe3(wrCmdCounter) -); - -cmdIla rxWrCmdIla ( - .clk(axi_clk), // input wire clk - .probe0(axis_rxwrite_cmd_TDATA), // input wire [71:0] probe0 - .probe1(axis_rxwrite_cmd_TVALID), // input wire [0:0] probe1 - .probe2(axis_rxwrite_cmd_TREADY), // input wire [0:0] probe2 - .probe3(wrCmdCounter) +//memory 0 read commands +.s_axis_mem0_read_cmd_tvalid(axis_rxread_cmd_tvalid), +.s_axis_mem0_read_cmd_tready(axis_rxread_cmd_tready), +.s_axis_mem0_read_cmd_tdata(axis_rxread_cmd_tdata), +//memory 0 read status +.m_axis_mem0_read_sts_tvalid(), +.m_axis_mem0_read_sts_tready(1'b1), +.m_axis_mem0_read_sts_tdata(), +//memory 0 read stream +.m_axis_mem0_read_tvalid(axis_rxread_data_tvalid), +.m_axis_mem0_read_tready(axis_rxread_data_tready), +.m_axis_mem0_read_tdata(axis_rxread_data_tdata), +.m_axis_mem0_read_tkeep(axis_rxread_data_tkeep), +.m_axis_mem0_read_tlast(axis_rxread_data_tlast), + +//memory 0 write commands +.s_axis_mem0_write_cmd_tvalid(axis_rxwrite_cmd_tvalid), +.s_axis_mem0_write_cmd_tready(axis_rxwrite_cmd_tready), +.s_axis_mem0_write_cmd_tdata(axis_rxwrite_cmd_tdata), +//memory 0 write status +.m_axis_mem0_write_sts_tvalid(axis_rxwrite_sts_tvalid), +.m_axis_mem0_write_sts_tready(axis_rxwrite_sts_tready), +.m_axis_mem0_write_sts_tdata(axis_rxwrite_sts_tdata), +//memory 0 write stream +.s_axis_mem0_write_tvalid(axis_rxwrite_data_tvalid), +.s_axis_mem0_write_tready(axis_rxwrite_data_tready), +.s_axis_mem0_write_tdata(axis_rxwrite_data_tdata), +.s_axis_mem0_write_tkeep(axis_rxwrite_data_tkeep), +.s_axis_mem0_write_tlast(axis_rxwrite_data_tlast), + +//memory 1 read commands +.s_axis_mem1_read_cmd_tvalid(axis_txread_cmd_tvalid), +.s_axis_mem1_read_cmd_tready(axis_txread_cmd_tready), +.s_axis_mem1_read_cmd_tdata(axis_txread_cmd_tdata), +//memory 1 read status +.m_axis_mem1_read_sts_tvalid(), +.m_axis_mem1_read_sts_tready(1'b1), +.m_axis_mem1_read_sts_tdata(), +//memory 1 read stream +.m_axis_mem1_read_tvalid(axis_txread_data_tvalid), +.m_axis_mem1_read_tready(axis_txread_data_tready), +.m_axis_mem1_read_tdata(axis_txread_data_tdata), +.m_axis_mem1_read_tkeep(axis_txread_data_tkeep), +.m_axis_mem1_read_tlast(axis_txread_data_tlast), + +//memory 1 write commands +.s_axis_mem1_write_cmd_tvalid(axis_txwrite_cmd_tvalid), +.s_axis_mem1_write_cmd_tready(axis_txwrite_cmd_tready), +.s_axis_mem1_write_cmd_tdata(axis_txwrite_cmd_tdata), +//memory 1 write status +.m_axis_mem1_write_sts_tvalid(axis_txwrite_sts_tvalid), +.m_axis_mem1_write_sts_tready(axis_txwrite_sts_tready), +.m_axis_mem1_write_sts_tdata(axis_txwrite_sts_tdata), +//memory 1 write stream +.s_axis_mem1_write_tvalid(axis_txwrite_data_tvalid), +.s_axis_mem1_write_tready(axis_txwrite_data_tready), +.s_axis_mem1_write_tdata(axis_txwrite_data_tdata), +.s_axis_mem1_write_tkeep(axis_txwrite_data_tkeep), +.s_axis_mem1_write_tlast(axis_txwrite_data_tlast) ); -stsIla rxWrStatusIla ( - .clk(axi_clk), // input wire clk - .probe0(axis_rxwrite_sts_TDATA), // input wire [7:0] probe0 - .probe1(1'b0), // input wire [0:0] probe1 - .probe2(axis_rxwrite_sts_TVALID) // input wire [0:0] probe2 -);*/ -/* -sessionIla sessionProbe ( - .clk(axi_clk), // input wire clk - .probe0(regSessionCount), // input wire [15:0] probe0 - .probe1(relSessionCount) // input wire [15:0] probe1 -); - -slupIla slupProbe ( - .clk(axi_clk), // input wire clk - .probe0(upd_req_TVALID_out), // input wire [0:0] probe0 - .probe1(upd_req_TREADY_out), // input wire [0:0] probe1 - .probe2(upd_req_TDATA_out), // input wire [0:0] probe2 - .probe3(upd_rsp_TVALID_out), // input wire [0:0] probe3 - .probe4(upd_rsp_TREADY_out) // input wire [0:0] probe4 -);*/ - endmodule `default_nettype wire