diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h index 2a187b4a12..f9da0df15d 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file partition_stm32u595xx.h * @author MCD Application Team - * @brief CMSIS STM32U599xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U595xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h index 627156cc38..36e09bbb10 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h @@ -1,8 +1,8 @@ /** ****************************************************************************** - * @file partition_stm32u5f9xx.h + * @file partition_stm32u5f7xx.h * @author MCD Application Team - * @brief CMSIS STM32U5F9xx Device Initial Setup for Secure / Non-Secure Zones + * @brief CMSIS STM32U5F7xx Device Initial Setup for Secure / Non-Secure Zones * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. * * This file contains: diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h index 723478ad75..515f70e902 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h @@ -26361,11 +26361,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h index f460e275c0..7e18d0f3b7 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g7xx.h @@ -27335,11 +27335,11 @@ typedef struct */ /******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ ((INSTANCE) == ADC2_NS) || \ ((INSTANCE) == ADC2_S) || \ - ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_NS) || \ ((INSTANCE) == ADC4_S)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h index 5519775501..52dd767b45 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -66,14 +66,14 @@ /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ - /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ - /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 Devices STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ + /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ - /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q Devices */ + /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ - /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Device */ - /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Device */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -89,11 +89,11 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number 1.3.0 + * @brief CMSIS Device version number 1.3.1 */ #define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32U5_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html index 1083f827a1..afffc85ad5 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html +++ b/system/Drivers/CMSIS/Device/ST/STM32U5xx/Release_Notes.html @@ -30,11 +30,25 @@

Release Notes for  STM32U5xx C

Update History

- +

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

    +
  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h” file
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices:
    • Add “stm32u5f9xx.h”, “stm32u5g9xx.h”, “stm32u5f7xx.h” and “stm32u5g7xx.h” files
      • @@ -42,7 +56,7 @@

      Main Changes

    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -51,7 +65,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

  • Support of stm32u535xx and stm32u545xx devices: @@ -104,7 +118,7 @@

    Main Changes

  • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
-

Backward Compatibility

+

Backward Compatibility

  • N/A
@@ -113,7 +127,7 @@

Backward Compatibility

-

Main Changes

+

Main Changes

  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
      @@ -143,7 +157,7 @@

      Main Changes

      -

      Main Changes

      +

      Main Changes

      • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
      • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
        • @@ -155,7 +169,7 @@

        Main Changes

        -

        Main Changes

        +

        Main Changes

        • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
        diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index 5d25504345..80132be290 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.7.3 * STM32L5: 1.0.5 * STM32MP1: 1.6.0 - * STM32U5: 1.3.0 + * STM32U5: 1.3.1 * STM32WB: 1.12.0 * STM32WL: 1.2.0 diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h index 60cc15ca4a..d52c9a44c4 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_adc.h @@ -2127,10 +2127,36 @@ __LL_ADC_CONVERT_DATA_RESOLUTION((__ADCx__), (__DATA__),\ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \ __ADC_DATA__, \ __ADC_RESOLUTION__) \ -__LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ - (__ADC_DATA__), \ +__LL_ADC_CALC_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ (__ADC_RESOLUTION__)) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) + * in differential ended mode. + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __ADCx__ ADC instance + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref ADC_RESOLUTION_14B + * @arg @ref ADC_RESOLUTION_12B + * @arg @ref ADC_RESOLUTION_10B + * @arg @ref ADC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__ADCx__, __VREFANALOG_VOLTAGE__, \ + __ADC_DATA__, \ + __ADC_RESOLUTION__) \ +__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__ADCx__), (__VREFANALOG_VOLTAGE__), \ + (__ADC_DATA__), \ + (__ADC_RESOLUTION__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h index 8d97c40f7a..a6970bfd12 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h +++ b/system/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_adc.h @@ -2684,10 +2684,37 @@ single-ended and differential modes. */ #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__,\ __ADC_DATA__, \ __ADC_RESOLUTION__) \ -((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__) \ +((__ADC_DATA__) * (int32_t)(__VREFANALOG_VOLTAGE__) \ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) \ ) +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value) in + * differential ended mode. + * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. + * @note ADC data from ADC data register is unsigned and centered around + * middle code in. Converted voltage can be positive or negative + * depending on differential input voltages. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (unit: digital value). + * @param __ADC_INSTANCE__ ADC instance + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_14B + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__ADC_INSTANCE__, __VREFANALOG_VOLTAGE__, \ + __ADC_DATA__, \ + __ADC_RESOLUTION__) \ +((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__) \ + / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_INSTANCE__, __ADC_RESOLUTION__)) - (int32_t)(__VREFANALOG_VOLTAGE__)) + /** * @brief Helper macro to calculate analog reference voltage (Vref+) * (unit: mVolt) from ADC conversion data of internal voltage @@ -2895,8 +2922,8 @@ single-ended and differential modes. */ * use a different data register outside of ADC instance scope * (common data register). This macro manages this register difference, * only ADC instance has to be set as parameter. - * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr - * CDR RDATA_MST LL_ADC_DMA_GetRegAddr + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr * @param ADCx ADC instance * @param RegisterValue This parameter can be one of the following values: @@ -2980,7 +3007,7 @@ __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR CKMODE LL_ADC_SetCommonClock + * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n * CCR PRESC LL_ADC_SetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3006,7 +3033,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin /** * @brief Get parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR CKMODE LL_ADC_GetCommonClock + * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n * CCR PRESC LL_ADC_GetCommonClock * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3053,8 +3080,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_C * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n * CCR VBATEN LL_ADC_SetCommonPathInternalChAdd * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3083,8 +3110,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem - * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n * CCR VBATEN LL_ADC_SetCommonPathInternalChRem * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3123,8 +3150,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * This check can be done with function @ref LL_ADC_IsEnabled() for each * ADC instance or by using helper macro helper macro * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh - * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n * CCR VBATEN LL_ADC_SetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3146,8 +3173,8 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_CO * @note One or several values can be selected. * Example: (LL_ADC_PATH_INTERNAL_VREFINT | * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh - * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n * CCR VBATEN LL_ADC_GetCommonPathInternalCh * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -3272,7 +3299,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, ui * ADC state: * ADC must be enabled, without calibration on going, without conversion * on going on group regular. - * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor + * @rmtoll CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor\n * CALFACT2 LINCALFACT LL_ADC_SetCalibrationLinearFactor * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: @@ -3302,7 +3329,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32 * @note Calibration factors are set by hardware after performing * a calibration run using function @ref LL_ADC_StartCalibration(). * @note On STM32U5, this feature is available on ADC instances: ADC1, ADC2. - * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor + * @rmtoll CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor\n * CALFACT2 LINCALFACT LL_ADC_GetCalibrationLinearFactor * @param ADCx ADC instance (on STM32U5, feature available on ADC instances: ADC1, ADC2) * @param LinearityWord This parameter can be one of the following values: @@ -3564,17 +3591,17 @@ __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) * on either groups regular or injected. * @note On STM32U5, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset - * OFR1 OFFSET1 LL_ADC_SetOffset - * OFR1 OFFSET1_EN LL_ADC_SetOffset - * OFR2 OFFSET2_CH LL_ADC_SetOffset - * OFR2 OFFSET2 LL_ADC_SetOffset - * OFR2 OFFSET2_EN LL_ADC_SetOffset - * OFR3 OFFSET3_CH LL_ADC_SetOffset - * OFR3 OFFSET3 LL_ADC_SetOffset - * OFR3 OFFSET3_EN LL_ADC_SetOffset - * OFR4 OFFSET4_CH LL_ADC_SetOffset - * OFR4 OFFSET4 LL_ADC_SetOffset + * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n + * OFR1 OFFSET1 LL_ADC_SetOffset\n + * OFR1 OFFSET1_EN LL_ADC_SetOffset\n + * OFR2 OFFSET2_CH LL_ADC_SetOffset\n + * OFR2 OFFSET2 LL_ADC_SetOffset\n + * OFR2 OFFSET2_EN LL_ADC_SetOffset\n + * OFR3 OFFSET3_CH LL_ADC_SetOffset\n + * OFR3 OFFSET3 LL_ADC_SetOffset\n + * OFR3 OFFSET3_EN LL_ADC_SetOffset\n + * OFR4 OFFSET4_CH LL_ADC_SetOffset\n + * OFR4 OFFSET4 LL_ADC_SetOffset\n * OFR4 OFFSET4_EN LL_ADC_SetOffset * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3645,9 +3672,9 @@ __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint3 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). * @note On STM32U5, some fast channels are available: fast analog inputs * coming from GPIO pads (ADC_IN0..5). - * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel - * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel - * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel + * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n + * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n + * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3706,9 +3733,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32 * @note Caution: Offset format is dependent to ADC resolution: * offset has to be left-aligned on bit 11, the LSB (right bits) * are set to 0. - * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel - * OFR2 OFFSET2 LL_ADC_GetOffsetLevel - * OFR3 OFFSET3 LL_ADC_GetOffsetLevel + * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n + * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n + * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n * OFR4 OFFSET4 LL_ADC_GetOffsetLevel * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3732,9 +3759,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign - * OFR2 OFFSETPOS LL_ADC_SetOffsetSign - * OFR3 OFFSETPOS LL_ADC_SetOffsetSign + * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_SetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3757,9 +3784,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, u /** * @brief Get for the ADC selected offset number 1, 2, 3 or 4: * offset sign if positive or negative. - * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign - * OFR2 OFFSETPOS LL_ADC_GetOffsetSign - * OFR3 OFFSETPOS LL_ADC_GetOffsetSign + * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n + * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n * OFR4 OFFSETPOS LL_ADC_GetOffsetSign * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3781,9 +3808,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t /** * @brief Set Signed saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation - * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation - * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation + * @rmtoll OFR1 SSAT LL_ADC_SetOffsetSignedSaturation\n + * OFR2 SSAT LL_ADC_SetOffsetSignedSaturation\n + * OFR3 SSAT LL_ADC_SetOffsetSignedSaturation\n * OFR4 SSAT LL_ADC_SetOffsetSignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3806,9 +3833,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_ /** * @brief Get Signed saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation - * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation - * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation + * @rmtoll OFR1 SSAT LL_ADC_GetOffsetSignedSaturation\n + * OFR2 SSAT LL_ADC_GetOffsetSignedSaturation\n + * OFR3 SSAT LL_ADC_GetOffsetSignedSaturation\n * OFR4 SSAT LL_ADC_GetOffsetSignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3829,9 +3856,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(const ADC_TypeDef *ADC /** * @brief Set Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation - * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation - * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation + * @rmtoll OFR1 USAT LL_ADC_SetOffsetUnsignedSaturation\n + * OFR2 USAT LL_ADC_SetOffsetUnsignedSaturation\n + * OFR3 USAT LL_ADC_SetOffsetUnsignedSaturation\n * OFR4 USAT LL_ADC_SetOffsetUnsignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3854,9 +3881,9 @@ __STATIC_INLINE void LL_ADC_SetOffsetUnsignedSaturation(ADC_TypeDef *ADCx, uint3 /** * @brief Get Unsigned saturation for the ADC selected offset number 1, 2, 3 or 4: * signed offset saturation if enabled or disabled. - * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation - * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation - * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation + * @rmtoll OFR1 USAT LL_ADC_GetOffsetUnsignedSaturation\n + * OFR2 USAT LL_ADC_GetOffsetUnsignedSaturation\n + * OFR3 USAT LL_ADC_GetOffsetUnsignedSaturation\n * OFR4 USAT LL_ADC_GetOffsetUnsignedSaturation * @param ADCx ADC instance * @param Offsety This parameter can be one of the following values: @@ -3886,7 +3913,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOffsetUnsignedSaturation(const ADC_TypeDef *A * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation + * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n * CFGR2 GCOMP LL_ADC_SetGainCompensation * @param ADCx ADC instance * @param GainCompensation This parameter can be: @@ -3902,7 +3929,7 @@ __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t Gain /** * @brief Get the ADC gain compensation value - * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation + * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n * CFGR2 GCOMP LL_ADC_GetGainCompensation * @param ADCx ADC instance * @retval Returned value can be: @@ -3947,8 +3974,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx) * ADC must be disabled or enabled without conversion on going * on group regular. * @note Applicable only on ADC4 instance - * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels - * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels + * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n + * SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels * @param ADCx ADC instance * @param SamplingTimeY This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 @@ -3981,8 +4008,8 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of * this STM32 series. - * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels - * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels + * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n + * SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels * @param ADCx ADC instance (ADC4 for this device) * @param SamplingTimeY This parameter can be one of the following values: * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 @@ -4023,7 +4050,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource + * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n * CFGR EXTEN LL_ADC_REG_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -4073,7 +4100,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource + * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n * CFGR EXTEN LL_ADC_REG_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4250,7 +4277,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode + * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode * @param ADCx ADC instance * @param SamplingMode This parameter can be one of the following values: @@ -4266,7 +4293,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t Samp /** * @brief Get the ADC sampling mode - * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode + * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4540,7 +4567,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont + * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont * @param ADCx ADC instance * @param SeqDiscont This parameter can be one of the following values: @@ -4564,7 +4591,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @brief Get ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. - * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont + * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -4603,21 +4630,21 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks - * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks - * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks - * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks - * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks + * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -4717,21 +4744,21 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks - * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks - * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks - * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks - * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks + * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -4880,24 +4907,24 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -4964,24 +4991,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -5048,24 +5075,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Ch * on group regular. * @note One or several values can be selected. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem * @param ADCx ADC instance * @param Channel This parameter can be a combination of the following values: @@ -5130,24 +5157,24 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * on group regular. * @note One or several values can be retrieved. * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels - * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels * @param ADCx ADC instance * @retval Returned value can be a combination of the following values: @@ -5215,6 +5242,26 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx * @note This function set the the value for the channel preselection register * corresponding to ADC channel to be selected. * @note Caution: This is not valid for ADC4. + * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n + * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n + * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n + * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n + * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n + * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n + * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * @param ADCx ADC instance. * @param Channel This parameter can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 @@ -5255,29 +5302,28 @@ __STATIC_INLINE void LL_ADC_SetChannelPreselection(ADC_TypeDef *ADCx, uint32_t C * @note This function set the the value for the channel preselection register * corresponding to ADC channel to be selected. * @note Caution: This is not valid for ADC4. + * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0\n + * PCSEL PCSEL1 LL_ADC_CHANNEL_1\n + * PCSEL PCSEL2 LL_ADC_CHANNEL_2\n + * PCSEL PCSEL3 LL_ADC_CHANNEL_3\n + * PCSEL PCSEL4 LL_ADC_CHANNEL_4\n + * PCSEL PCSEL5 LL_ADC_CHANNEL_5\n + * PCSEL PCSEL6 LL_ADC_CHANNEL_6\n + * PCSEL PCSEL7 LL_ADC_CHANNEL_7\n + * PCSEL PCSEL8 LL_ADC_CHANNEL_8\n + * PCSEL PCSEL9 LL_ADC_CHANNEL_9\n + * PCSEL PCSEL10 LL_ADC_CHANNEL_10\n + * PCSEL PCSEL11 LL_ADC_CHANNEL_11\n + * PCSEL PCSEL12 LL_ADC_CHANNEL_12\n + * PCSEL PCSEL13 LL_ADC_CHANNEL_13\n + * PCSEL PCSEL14 LL_ADC_CHANNEL_14\n + * PCSEL PCSEL15 LL_ADC_CHANNEL_15\n + * PCSEL PCSEL16 LL_ADC_CHANNEL_16\n + * PCSEL PCSEL17 LL_ADC_CHANNEL_17\n + * PCSEL PCSEL18 LL_ADC_CHANNEL_18\n + * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * @param ADCx ADC instance. - * * @retval Returned decimal value that can correspend to one or multiple channels: - * @rmtoll PCSEL PCSEL0 LL_ADC_CHANNEL_0 - * PCSEL PCSEL1 LL_ADC_CHANNEL_1 - * PCSEL PCSEL2 LL_ADC_CHANNEL_2 - * PCSEL PCSEL3 LL_ADC_CHANNEL_3 - * PCSEL PCSEL4 LL_ADC_CHANNEL_4 - * PCSEL PCSEL5 LL_ADC_CHANNEL_5 - * PCSEL PCSEL6 LL_ADC_CHANNEL_6 - * PCSEL PCSEL7 LL_ADC_CHANNEL_7 - * PCSEL PCSEL8 LL_ADC_CHANNEL_8 - * PCSEL PCSEL9 LL_ADC_CHANNEL_9 - * PCSEL PCSEL10 LL_ADC_CHANNEL_10 - * PCSEL PCSEL11 LL_ADC_CHANNEL_11 - * PCSEL PCSEL12 LL_ADC_CHANNEL_12 - * PCSEL PCSEL13 LL_ADC_CHANNEL_13 - * PCSEL PCSEL14 LL_ADC_CHANNEL_14 - * PCSEL PCSEL15 LL_ADC_CHANNEL_15 - * PCSEL PCSEL16 LL_ADC_CHANNEL_16 - * PCSEL PCSEL17 LL_ADC_CHANNEL_17 - * PCSEL PCSEL18 LL_ADC_CHANNEL_18 - * PCSEL PCSEL19 LL_ADC_CHANNEL_19 * * @note User helper macro @ref __LL_ADC_DECIMAL_NB_TO_CHANNEL(). */ @@ -5364,7 +5410,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetLPModeAutonomousDPD(const ADC_TypeDef *ADCx) * ADC4 is put on hold during one or two ADC4 clock cycles to avoid noise on Vref+. * ADC state: * ADC must be disabled. - * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection + * @rmtoll PWRR VREFPROT LL_ADC_SetVrefProtection\n * PWRR VREFSECSMP LL_ADC_SetVrefProtection * @param ADCx ADC instance * @param VrefProtection This parameter can be one of the following values: @@ -5380,7 +5426,7 @@ __STATIC_INLINE void LL_ADC_SetVrefProtection(ADC_TypeDef *ADCx, uint32_t VrefPr /** * @brief ADC VREF protection when multiple ADCs are working simultaneously - * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection + * @rmtoll PWRR VREFPROT LL_ADC_GetVrefProtection\n * PWRR VREFSECSMP LL_ADC_GetVrefProtection * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5499,7 +5545,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer * @param ADCx ADC instance * @param DMATransfer This parameter can be one of the following values: @@ -5533,7 +5579,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * (overrun flag and interruption if enabled). * @note To configure DMA source address (peripheral address), * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5609,7 +5655,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -5652,7 +5698,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -5839,9 +5885,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -5912,9 +5958,9 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * - To get the channel number in decimal format: * process the returned value with the helper macro * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks - * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks - * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks + * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -6043,12 +6089,12 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx) * ADC state: * ADC must not be disabled. Can be enabled with or without conversion * on going on either groups regular or injected. - * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext - * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext - * JSQR JL LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext - * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext + * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n + * JSQR JL LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n + * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext * @param ADCx ADC instance * @param TriggerSource This parameter can be one of the following values: @@ -6290,24 +6336,24 @@ __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx, * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime - * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime - * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime + * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: @@ -6400,24 +6446,24 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * - 10.5 ADC clock cycles at ADC resolution 10 bits * - 8.5 ADC clock cycles at ADC resolution 8 bits * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime - * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime - * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime + * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime * @param ADCx ADC instance * @param Channel This parameter can be one of the following values: @@ -6650,11 +6696,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, ui * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels - * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels - * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels - * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels - * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels + * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -6818,11 +6864,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels - * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels - * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels - * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels - * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels + * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n + * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7016,11 +7062,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx * ADC state: * ADC must be disabled or enabled without conversion on going * on either ADC groups regular or injected. - * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds - * TR2 HT2 LL_ADC_SetAnalogWDThresholds - * TR3 HT3 LL_ADC_SetAnalogWDThresholds - * TR1 LT1 LL_ADC_SetAnalogWDThresholds - * TR2 LT2 LL_ADC_SetAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n * TR3 LT3 LL_ADC_SetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7084,11 +7130,11 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @note In case of ADC resolution different of 12 bits, * analog watchdog thresholds data require a specific shift. * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds - * TR2 HT2 LL_ADC_GetAnalogWDThresholds - * TR3 HT3 LL_ADC_GetAnalogWDThresholds - * TR1 LT1 LL_ADC_GetAnalogWDThresholds - * TR2 LT2 LL_ADC_GetAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n + * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n + * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n + * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n * TR3 LT3 LL_ADC_GetAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7186,11 +7232,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, u * ADC state: * ADC must be disabled or enabled without conversion on going * on group regular. - * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds - * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds - * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds - * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds - * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds + * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n + * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n + * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n + * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds * @param ADCx ADC instance * @param AWDy This parameter can be one of the following values: @@ -7325,8 +7371,8 @@ __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef * * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope - * CFGR2 JOVSE LL_ADC_SetOverSamplingScope + * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_SetOverSamplingScope * @param ADCx ADC instance * @param OvsScope This parameter can be one of the following values: @@ -7358,8 +7404,8 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * the oversampling on ADC group regular is either * temporary stopped and continued, or resumed from start * (oversampler buffer reset). - * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope - * CFGR2 JOVSE LL_ADC_GetOverSamplingScope + * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n + * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n * CFGR2 ROVSM LL_ADC_GetOverSamplingScope * @param ADCx ADC instance * @retval Returned value can be one of the following values: @@ -7437,7 +7483,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) * ADC state: * ADC must be disabled or enabled without conversion on going * on either groups regular or injected. - * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift + * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift * @param ADCx ADC instance * @param Ratio For ADC instance ADC1, ADC2: This parameter can be in the range from 1 to 1024. @@ -7956,8 +8002,8 @@ __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) * @note On this STM32 series, setting of this feature is conditioned to * ADC state: * ADC must be ADC disabled. - * @rmtoll CR ADCAL LL_ADC_StartCalibration - * CR ADCALDIF LL_ADC_StartCalibration + * @rmtoll CR ADCAL LL_ADC_StartCalibration\n + * CR ADCALDIF LL_ADC_StartCalibration\n * CR ADCALLIN LL_ADC_StartCalibration * @param ADCx ADC instance * @param CalibrationMode This parameter can be one of the following values: @@ -8170,7 +8216,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) * transfer by DMA, because this function can do the same * by getting multimode conversion data of ADC master or ADC slave * separately). - * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32 + * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32 * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) @@ -8265,9 +8311,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *A * all ADC configurations: all ADC resolutions and * all oversampling increased data width (for devices * with feature oversampling). - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData32 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData32 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8291,9 +8337,9 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData16 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData16 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData16\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData16\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData16\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData16 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8317,9 +8363,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData14 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData14 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData14\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData14\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData14\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData14 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8343,9 +8389,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData12 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData12 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8369,9 +8415,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData10 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData10 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: @@ -8395,9 +8441,9 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx * @note For devices with feature oversampling: Oversampling * can increase data width, function for extended range * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8 - * JDR2 JDATA LL_ADC_INJ_ReadConversionData8 - * JDR3 JDATA LL_ADC_INJ_ReadConversionData8 + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 * @param ADCx ADC instance * @param Rank This parameter can be one of the following values: diff --git a/system/Drivers/STM32U5xx_HAL_Driver/README.md b/system/Drivers/STM32U5xx_HAL_Driver/README.md index 717e8e7478..9d77735a7a 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32U5xx_HAL_Driver/README.md @@ -1,21 +1,22 @@ # STM32CubeU5 HAL Driver MCU Component +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32u5xx_hal_driver.svg?color=brightgreen) + ## Overview -**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. +**STM32Cube** is a STMicroelectronics original initiative aimed at making life easier for developers by reducing effort, time and cost. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform, delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product - * The STM32 HAL-LL drivers : an abstraction drivers layer, the API ensuring maximized portability across the STM32 portfolio - * The BSP Drivers of each evaluation or demonstration board provided by this STM32 series - * A consistent set of middlewares components such as ThreadX, FileX, USBX, NetDuoX, OpenBootloader, USBPD, trustedfirmware, mbed-crypto, Network Library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration, or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as ThreadX, FileX, USBX, NetDuoX, OpenBootloader, USBPD, trustedfirmware, mbed-crypto, Network Library... + * A full set of software projects (basic examples, applications, and demonstrations) for each board, each project developed in three flavors using three toolchains (EWARM, MDK-ARM, and STM32CubeIDE). * A new LPBAM utility which is a software helper that assists STM32U5 users in the elaboration of LPBAM scenarios. - * A development with three Toolchains and Compilers (IAR Embedded Workbench for ARM (EWARM), RealView Microcontroller Development Kit (MDK-ARM), and STM32CubeIDE). Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package** : all STM32Cube software modules of one STM32 series are present (Drivers, Middlewares, Projects, Utilities) in the repo (usual name **STM32Cubexx**, xx corresponding to the STM32 series) - * The **MCU component** : progressively from June 2021, each STM32Cube software module being part of the STM32Cube MCU Package, are delivered as an individual repo, allowing the user to select and get only the required software functions. + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. ## Description @@ -34,6 +35,4 @@ The full **STM32CubeU5** MCU package is available [here](https://github.com/STMi ## Troubleshooting -If you have any issue with the **Software content** of this repo, you can [file an issue on Github](https://github.com/STMicroelectronics/stm32u5xx_hal_driver/issues/new/choose). - -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). \ No newline at end of file +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html index dd2ec3808e..d335e141ee 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32U5xx_HAL_Driver/Release_Notes.html @@ -40,16 +40,53 @@

        Purpose

        Update History

        - +

        Main Changes

          +
        • HAL and LL drivers Maintenance Release for STM32U5XX devices
          • +
        • Update ADC HAL and LL drivers to fix known defects and add implementation enhancements
          • +
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
          • +
        +

        HAL Drivers updates

        +
          +
        • HAL ADC driver +
            +
          • Add new Helper macro for differential mode raw data to voltage conversion
            • +
          • +
        • HAL ADC_EX driver +
            +
          • Enhance calibration procedure implementation
            • +
          • +
        +

        LL Drivers updates

        +
          +
        • LL ADC driver +
            +
          • Add new Helper macro for differential mode raw data to voltage conversion
            • +
          • +
        +

        Known Limitations

        +
          +
        • N/A
          • +
        +

        Backward compatibility

        +
          +
        • N/A
          • +
        +
        +
        +
        + +
        +

        Main Changes

        +
        • HAL and LL drivers official Release for STM32U5F7xx/STM32U5G7xx, STM32U5F9xx/STM32U5G9xx, STM32U535xx/STM32U545xx, STM32U575xx/STM32U585xx, STM32U595xx/STM32U5A5xx and STM32U599xx/STM32U5A9xx devices
        • Add 2 new HAL drivers : GFXTIM and JPEG highlighting the graphics aspect of STM32U5F7/STM32U5G7/STM32U5F9/STM32U5G9 devices
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
        • General updates to fix known defects and implementation enhancements
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • HAL CRYP driver
            @@ -87,7 +124,7 @@

            HAL Drivers updates

          • Add IS_TIM_CCX_CHANNEL define
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL PWR driver
            @@ -132,11 +169,11 @@

            LL Drivers updates

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -145,12 +182,12 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Official Release for STM32U535xx / STM32U545xx, STM32U575xx / STM32U585xx, STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices.
        • Update STM32U545xx_User_Manual, STM32U585xx_User_Manual and STM32U5A9xx_User_Manual CHM User Manuals
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • HAL ADC driver
            @@ -303,7 +340,7 @@

            HAL Drivers updates

          • Add HAL_HCD_HC_SetHubInfo and HAL_HCD_HC_ClearHubInfo macros
        -

        LL Drivers updates

        +

        LL Drivers updates

        • LL ADC driver
            @@ -345,11 +382,11 @@

            LL Drivers updates

        Note: HAL/LL Backward compatibility ensured by legacy defines.

        -

        Known Limitations

        +

        Known Limitations

        • N/A
        -

        Backward compatibility

        +

        Backward compatibility

        • N/A
        @@ -358,7 +395,7 @@

        Backward compatibility

        -

        Main Changes

        +

        Main Changes

        • HAL and LL drivers Maintenance Release for STM32U575xx / STM32U585xx devices and new support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
        • Add New LTDC, GFXMMU, DSI, GPU2D HAL drivers highlighting the graphics aspect of STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
          • @@ -367,7 +404,7 @@

          Main Changes

        • General updates to fix known defects and implementation enhancements
        • The HAL and LL drivers provided within this package are MISRA-C, MCU ASTYLE and CodeSonar compliant, and have been reviewed with a static analysis tool to eliminate possible run-time errors
        -

        HAL Drivers updates

        +

        HAL Drivers updates

        • All the HAL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
        • HAL ADC driver @@ -505,7 +542,7 @@

          HAL Drivers updates

        • Rework HAL_USART_DMAResume() function in order to use DMA instead of USART to resume data transfer
      -

      LL Drivers updates

      +

      LL Drivers updates

      • All the LL drivers are updated to support both STM32U575/STM32U585 and STM32U595/STM32U5A5/STM32U599/STM32U5A9 devices
      • LL ADC driver @@ -576,11 +613,11 @@

        LL Drivers updates

    Backward compatibility ensured by legacy defines

    -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -589,11 +626,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • Patch release V1.0.2 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL DAC driver
        @@ -605,11 +642,11 @@

        LL Drivers updates

    • Backward compatibility ensured by legacy defines
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -618,11 +655,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • Patch release V1.0.1 of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    HAL Drivers updates

    +

    HAL Drivers updates

    • HAL ADC driver
        @@ -660,18 +697,18 @@

        HAL Drivers updates

      • Fix setting Flash latency from MSIRange in Oscillator Configuration
    -

    LL Drivers updates

    +

    LL Drivers updates

    • LL I2C driver
      • Add LL_I2C_EnableFastModePlus, LL_I2C_DisableFastModePlus and LL_I2C_IsEnabledFastModePlus APIs
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    -

    Backward compatibility

    +

    Backward compatibility

    • N/A
    @@ -680,11 +717,11 @@

    Backward compatibility

    -

    Main Changes

    +

    Main Changes

    • First official release of HAL and LL drivers for STM32U575xx / STM32U585xx devices
    -

    Known Limitations

    +

    Known Limitations

    • N/A
    diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c index cabce48acb..9c640570c5 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c @@ -52,10 +52,10 @@ * @{ */ /** - * @brief STM32U5xx HAL Driver version number 1.3.0 + * @brief STM32U5xx HAL Driver version number 1.4.0 */ #define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */ +#define __STM32U5xx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ #define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ diff --git a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c index 471e5d9cf9..c9a1397da0 100644 --- a/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c +++ b/system/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_adc_ex.c @@ -210,8 +210,11 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t if (tmp_hal_status == HAL_OK) { + /* Use a Data Memory Barrier instruction to avoid synchronization issues when accessing ADC registers */ MODIFY_REG(hadc->Instance->CR, ADC_CR_CALINDEX, 0x9UL << ADC_CR_CALINDEX_Pos); - MODIFY_REG(hadc->Instance->CALFACT2, 0x00FF0000UL, 0x00020000UL); + __DMB(); + MODIFY_REG(hadc->Instance->CALFACT2, 0xFFFFFF00UL, 0x03021100UL); + __DMB(); SET_BIT(hadc->Instance->CALFACT, ADC_CALFACT_LATCH_COEF); tmp_hal_status = ADC_Disable(hadc); diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 0b3ddb1b68..5abbc1daf2 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -16,7 +16,7 @@ * STM32L4: 1.13.4 * STM32L5: 1.0.5 * STM32MP1: 1.6.0 - * STM32U5: 1.3.0 + * STM32U5: 1.4.0 * STM32WB: 1.14.0 * STM32WL: 1.3.0