net: dsa: rtl8367: add chip detection

drivers/net/dsa/rtl8367s_mdio.c

@@ -21,10 +21,17 @@
 #include <linux/of_gpio.h>
 
 #include "rtl8367s_mdio.h"
-//#include  "./rtl8367c/include/rtk_switch.h"
-//#include  "./rtl8367c/include/port.h"
-//#include  "./rtl8367c/include/vlan.h"
-//#include  "./rtl8367c/include/rtl8367c_asicdrv_port.h"
+
+/*
+DTS-properties:
+
+"compatible" = "realtek,rtk-gsw"
+"realtek,reset-pin" =<gpio>
+"realtek,mdio" = <mdio phandle>
+
+optional:
+realtek,port_map="wllll"
+*/
 
 struct rtk_gsw {
 	struct device           *dev;
@@ -64,8 +71,204 @@ unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsig
 
 	return 0;
 }
+#define MDC_MDIO_PHY_ID		29  /* PHY ID 0 or 29 */
+#define MDC_MDIO_WRITE(preamableLength, phyID, regID, data) mii_mgr_write(phyID, regID, data)
+#define MDC_MDIO_READ(preamableLength, phyID, regID, pData) mii_mgr_read(phyID, regID, pData)
+
+//MDC_MDIO_OPERATION is defined in phy code via makefile
+rtk_int32 smi_read(rtk_uint32 mAddrs, rtk_uint32 *rData)
+{
+    if(mAddrs > 0xFFFF)
+        return RT_ERR_INPUT;
+
+    if(rData == NULL)
+        return RT_ERR_NULL_POINTER;
+
+    /* Lock (empty function in phy driver) */
+    //rtlglue_drvMutexLock();
+
+    /* Write address control code to register 31 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
+
+    /* Write address to register 23 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);
+
+    /* Write read control code to register 21 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_READ_OP);
+
+    /* Read data from register 25 */
+    MDC_MDIO_READ(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_READ_REG, rData);
+
+    /* Unlock (empty function in phy driver) */
+    //rtlglue_drvMutexUnlock();
+
+    return RT_ERR_OK;
+}
+
+rtk_int32 smi_write(rtk_uint32 mAddrs, rtk_uint32 rData)
+{
+    if(mAddrs > 0xFFFF)
+        return RT_ERR_INPUT;
+
+    if(rData > 0xFFFF)
+        return RT_ERR_INPUT;
+
+    /* Lock (empty function in phy driver) */
+    //rtlglue_drvMutexLock();
+
+    /* Write address control code to register 31 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL0_REG, MDC_MDIO_ADDR_OP);
+
+    /* Write address to register 23 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_ADDRESS_REG, mAddrs);
+
+    /* Write data to register 24 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_DATA_WRITE_REG, rData);
+
+    /* Write data control code to register 21 */
+    MDC_MDIO_WRITE(MDC_MDIO_PREAMBLE_LEN, MDC_MDIO_PHY_ID, MDC_MDIO_CTRL1_REG, MDC_MDIO_WRITE_OP);
+
+    /* Unlock (empty function in phy driver) */
+    //rtlglue_drvMutexUnlock();
+
+    return RT_ERR_OK;
+
+}
+
+
+
+/* Function Name:
+ *      rtl8367c_setAsicReg
+ * Description:
+ *      Set content of asic register
+ * Input:
+ *      reg     - register's address
+ *      value   - Value setting to register
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK       - Success
+ *      RT_ERR_SMI      - SMI access error
+ * Note:
+ *      The value will be set to ASIC mapping address only and it is always return RT_ERR_OK while setting un-mapping address registers
+ */
+ret_t rtl8367c_setAsicReg(rtk_uint32 reg, rtk_uint32 value)
+{
+    ret_t retVal;
+
+    retVal = smi_write(reg, value);
+    if(retVal != RT_ERR_OK)
+        return RT_ERR_SMI;
+
+    return RT_ERR_OK;
+}
+/* Function Name:
+ *      rtl8367c_getAsicReg
+ * Description:
+ *      Get content of asic register
+ * Input:
+ *      reg     - register's address
+ *      value   - Value setting to register
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK       - Success
+ *      RT_ERR_SMI      - SMI access error
+ * Note:
+ *      Value 0x0000 will be returned for ASIC un-mapping address
+ */
+ret_t rtl8367c_getAsicReg(rtk_uint32 reg, rtk_uint32 *pValue)
+{
+
+    rtk_uint32 regData;
+    ret_t retVal;
+
+    retVal = smi_read(reg, &regData);
+    if(retVal != RT_ERR_OK)
+        return RT_ERR_SMI;
+
+    *pValue = regData;
+
+    return RT_ERR_OK;
+}
 
-static int rtk_switch_init(void) { return 0; }
+
+/* Function Name:
+ *      rtk_switch_probe
+ * Description:
+ *      Probe switch
+ * Input:
+ *      None
+ * Output:
+ *      None
+ * Return:
+ *      RT_ERR_OK       - Switch probed
+ *      RT_ERR_FAILED   - Switch Unprobed.
+ * Note:
+ *
+ */
+rtk_api_ret_t rtk_switch_probe(switch_chip_t *pSwitchChip)
+{
+	rtk_uint32 retVal;
+	rtk_uint32 data, regValue;
+
+	if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)
+		return retVal;
+
+	if((retVal = rtl8367c_getAsicReg(0x1300, &data)) != RT_ERR_OK)
+		return retVal;
+
+	if((retVal = rtl8367c_getAsicReg(0x1301, &regValue)) != RT_ERR_OK)
+		return retVal;
+
+	if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)
+		return retVal;
+
+	printk(KERN_ALERT "DEBUG: Passed %s %d chip: 0x%x\n",__FUNCTION__,__LINE__,data); //0x6367 on r64 v0.1
+
+	switch (data)
+	{
+		case 0x0276:
+		case 0x0597:
+		case 0x6367:
+			*pSwitchChip = CHIP_RTL8367C;
+			break;
+		case 0x0652:
+		case 0x6368:
+			*pSwitchChip = CHIP_RTL8370B;
+			break;
+		case 0x0801:
+		case 0x6511:
+			if( (regValue & 0x00F0) == 0x0080)
+			{
+				*pSwitchChip = CHIP_RTL8363SC_VB;
+			}
+			else
+			{
+				*pSwitchChip = CHIP_RTL8364B;
+			}
+			break;
+		default:
+			return RT_ERR_FAILED;
+	}
+
+	return RT_ERR_OK;
+}
+
+rtk_api_ret_t rtk_switch_init(void)
+{
+	rtk_uint32  retVal;
+	//rtl8367c_rma_t rmaCfg;
+	switch_chip_t   switchChip;
+
+	/* probe switch */
+	if ((retVal = rtk_switch_probe(&switchChip)) != RT_ERR_OK)
+		return retVal;
+
+	//some more missing here...
+
+	return 0;
+}
 
 static int rtl8367s_hw_reset(void)
 {
@@ -259,7 +462,7 @@ static int rtk_gsw_probe(struct platform_device *pdev)
 
 	//init default vlan or init swocnfig
 	if(!of_property_read_string(pdev->dev.of_node,
-						"mediatek,port_map", &pm)) {
+						"realtek,port_map", &pm)) {
 		if (!strcasecmp(pm, "wllll"))
 			rtl8367s_vlan_config(1);
 		else