some debug for pcie hang

Booting Linux on physical CPU 0x0000000000 [0x412fd050]
Linux version 5.16.0-rc8-next-20220105-next2 (frank@frank-G5-U20) (aarch64-linux-gnu-gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0, GNU ld (GNU Binutils for Ubuntu) 2.34) #2
Machine model: Bananapi-R2 Pro (RK3568) DDR4 V00 Board
earlycon: uart8250 at MMIO32 0x00000000fe660000 (options '')
printk: bootconsole [uart8250] enabled
efi: UEFI not found.
NUMA: No NUMA configuration found
NUMA: Faking a node at [mem 0x0000000000a00000-0x000000007fffffff]
NUMA: NODE_DATA [mem 0x7fbb6e40-0x7fbb8fff]
Zone ranges:
  DMA      [mem 0x0000000000a00000-0x000000007fffffff]
  DMA32    empty
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0000000000a00000-0x000000007fffffff]
Initmem setup node 0 [mem 0x0000000000a00000-0x000000007fffffff]
On node 0, zone DMA: 2560 pages in unavailable ranges
psci: probing for conduit method from DT.
psci: PSCIv1.1 detected in firmware.
psci: Using standard PSCI v0.2 function IDs
psci: MIGRATE_INFO_TYPE not supported.
psci: SMC Calling Convention v1.2
percpu: Embedded 26 pages/cpu s68376 r8192 d29928 u106496
Detected VIPT I-cache on CPU0
CPU features: detected: GIC system register CPU interface
CPU features: detected: Virtualization Host Extensions
CPU features: detected: ARM errata 1165522, 1319367, or 1530923
alternatives: patching kernel code
Fallback order for Node 0: 0
Built 1 zonelists, mobility grouping on.  Total pages: 513576
Policy zone: DMA
Kernel command line: console=ttyS2,1500000n8 earlycon=uart8250,mmio32,0xfe660000 earlyprintk
Unknown kernel command line parameters "earlyprintk", will be passed to user space.
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 2001940K/2086912K available (9408K kernel code, 1918K rwdata, 3752K rodata, 2368K init, 499K bss, 84972K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
trace event string verifier disabled
rcu: Preemptible hierarchical RCU implementation.
rcu:    RCU event tracing is enabled.
rcu:    RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4.
        Trampoline variant of Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
GICv3: GIC: Using split EOI/Deactivate mode
GICv3: 320 SPIs implemented
GICv3: 0 Extended SPIs implemented
GICv3: Distributor has no Range Selector support
GICv3: MBI range [296:319]
GICv3: Using MBI frame 0x00000000fd410000
Root IRQ handler: gic_handle_irq
GICv3: 16 PPIs implemented
GICv3: CPU0: found redistributor 0 region 0:0x00000000fd460000
/interrupt-controller@fd400000/interrupt-controller@fd440000: no regs?
ITS: No ITS available, not enabling LPIs
random: get_random_bytes called from start_kernel+0x4d4/0x6bc with crng_init=0
arch_timer: cp15 timer(s) running at 24.00MHz (phys).
clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
Console: colour dummy device 80x25
Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
cblist_init_generic: Setting adjustable number of callback queues.
cblist_init_generic: Setting shift to 2 and lim to 1.
rcu: Hierarchical SRCU implementation.
interrupt-controller@fd440000: unable to locate ITS domain
interrupt-controller@fd440000: Unable to locate ITS domain
EFI services will not be available.
smp: Bringing up secondary CPUs ...
Detected VIPT I-cache on CPU1
GICv3: CPU1: found redistributor 100 region 0:0x00000000fd480000
CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
Detected VIPT I-cache on CPU2
GICv3: CPU2: found redistributor 200 region 0:0x00000000fd4a0000
CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
Detected VIPT I-cache on CPU3
GICv3: CPU3: found redistributor 300 region 0:0x00000000fd4c0000
CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
smp: Brought up 1 node, 4 CPUs
SMP: Total of 4 processors activated.
CPU features: detected: 32-bit EL0 Support
CPU features: detected: Data cache clean to the PoU not required for I/D coherence
CPU features: detected: Common not Private translations
CPU features: detected: CRC32 instructions
CPU features: detected: RCpc load-acquire (LDAPR)
CPU features: detected: LSE atomic instructions
CPU features: detected: Privileged Access Never
CPU features: detected: RAS Extension Support
CPU features: detected: Speculative Store Bypassing Safe (SSBS)
CPU: All CPU(s) started at EL2
devtmpfs: initialized
KASLR disabled due to lack of seed
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
pinctrl core: initialized pinctrl subsystem
DMI not present or invalid.
NET: Registered PF_NETLINK/PF_ROUTE protocol family
DMA: preallocated 256 KiB GFP_KERNEL pool for atomic allocations
DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
DMA: preallocated 256 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
audit: initializing netlink subsys (disabled)
audit: type=2000 audit(0.064:1): state=initialized audit_enabled=0 res=1
thermal_sys: Registered thermal governor 'step_wise'
cpuidle: using governor menu
hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
ASID allocator initialised with 65536 entries
rockchip-gpio fdd60000.gpio: probed /pinctrl/gpio@fdd60000
rockchip-gpio fe740000.gpio: probed /pinctrl/gpio@fe740000
rockchip-gpio fe750000.gpio: probed /pinctrl/gpio@fe750000
rockchip-gpio fe760000.gpio: probed /pinctrl/gpio@fe760000
rockchip-gpio fe770000.gpio: probed /pinctrl/gpio@fe770000
ACPI: Interpreter disabled.
iommu: Default domain type: Translated
iommu: DMA domain TLB invalidation policy: strict mode
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
PTP clock support registered
power_supply_init_attrs: Property 37 skipped because it is missing from power_supply_attrs
clocksource: Switched to clocksource arch_sys_counter
pnp: PnP ACPI: disabled
NET: Registered PF_INET protocol family
IP idents hash table entries: 32768 (order: 6, 262144 bytes, linear)
tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
TCP: Hash tables configured (established 16384 bind 16384)
UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
NET: Registered PF_UNIX/PF_LOCAL protocol family
PCI: CLS 0 bytes, default 64
Trying to unpack rootfs image as initramfs...
hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
workingset: timestamp_bits=42 max_order=19 bucket_order=0
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 249)
io scheduler mq-deadline registered
io scheduler kyber registered
rockchip-snps-pcie3-phy fe8c0000.phy: failed to find rockchip,pipe_grf regmap
DEBUG: Passed dw_pcie_host_init 320
rockchip-dw-pcie 3c0400000.pcie: host bridge /pcie@fe270000 ranges:
rockchip-dw-pcie 3c0400000.pcie:       IO 0x037f700000..0x037f7fffff -> 0x00bf700000
rockchip-dw-pcie 3c0400000.pcie:      MEM 0x0340000000..0x037f6fffff -> 0x0080000000
DEBUG: Passed dw_pcie_host_init 324
DEBUG: Passed dw_pcie_host_init 326
DEBUG: Passed dw_pcie_host_init 334
DEBUG: Passed dw_pcie_host_init 337
DEBUG: Passed dw_pcie_host_init 341
DEBUG: Passed dw_pcie_host_init 347
DEBUG: Passed dw_pcie_host_init 352
DEBUG: Passed dw_pcie_host_init 359
DEBUG: Passed dw_pcie_host_init 400
DEBUG: Passed dw_pcie_iatu_detect 670
DEBUG: Passed dw_pcie_iatu_unroll_enabled 592
DEBUG: Passed dw_pcie_iatu_unroll_enabled 594
DEBUG: Passed dw_pcie_iatu_detect 673
DEBUG: Passed dw_pcie_iatu_detect 676
DEBUG: Passed dw_pcie_iatu_detect 683
DEBUG: Passed dw_pcie_iatu_detect 686
DEBUG: Passed dw_pcie_iatu_detect 688
DEBUG: Passed dw_pcie_iatu_detect 692
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 605
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 607 max_region:8
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 618 max_region:8
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 629
DEBUG: Passed dw_pcie_iatu_detect 694
DEBUG: Passed dw_pcie_iatu_detect 698
rockchip-dw-pcie 3c0400000.pcie: iATU unroll: enabled
DEBUG: Passed dw_pcie_iatu_detect 701
rockchip-dw-pcie 3c0400000.pcie: Detected iATU regions: 8 outbound, 8 inbound
DEBUG: Passed dw_pcie_iatu_detect 704
DEBUG: Passed dw_pcie_host_init 402
DEBUG: Passed dw_pcie_host_init 404
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
DEBUG: Passed dw_pcie_host_init 410
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x1 linkup:0 ltssm:1 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0400000.pcie: Phy link never came up
DEBUG: Passed dw_pcie_host_init 413
DEBUG: Passed dw_pcie_host_init 415
rockchip-dw-pcie 3c0400000.pcie: PCI host bridge to bus 0001:10
pci_bus 0001:10: root bus resource [bus 10-1f]
pci_bus 0001:10: root bus resource [io  0x0000-0xfffff] (bus address [0xbf700000-0xbf7fffff])
pci_bus 0001:10: root bus resource [mem 0x340000000-0x37f6fffff] (bus address [0x80000000-0xbf6fffff])
pci 0001:10:00.0: [1d87:3566] type 01 class 0x060400
pci 0001:10:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
pci 0001:10:00.0: supports D1 D2
pci 0001:10:00.0: PME# supported from D0 D1 D3hot
pci 0001:10:00.0: Primary bus is hard wired to 0
pci 0001:10:00.0: bridge configuration invalid ([bus 01-ff]), reconfiguring
rockchip-dw-pcie 3c0400000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
pci_bus 0001:11: busn_res: [bus 11-1f] end is updated to 11
pci 0001:10:00.0: BAR 6: assigned [mem 0x340000000-0x34000ffff pref]
pci 0001:10:00.0: PCI bridge to [bus 11]
DEBUG: Passed dw_pcie_host_init 417
DEBUG: Passed dw_pcie_host_init 320
rockchip-dw-pcie 3c0800000.pcie: host bridge /pcie@fe280000 ranges:
rockchip-dw-pcie 3c0800000.pcie:       IO 0x03bf700000..0x03bf7fffff -> 0x00ff700000
rockchip-dw-pcie 3c0800000.pcie:      MEM 0x0380000000..0x03bf6fffff -> 0x00c0000000
DEBUG: Passed dw_pcie_host_init 324
DEBUG: Passed dw_pcie_host_init 326
DEBUG: Passed dw_pcie_host_init 334
DEBUG: Passed dw_pcie_host_init 337
DEBUG: Passed dw_pcie_host_init 341
DEBUG: Passed dw_pcie_host_init 347
DEBUG: Passed dw_pcie_host_init 352
DEBUG: Passed dw_pcie_host_init 359
DEBUG: Passed dw_pcie_host_init 400
DEBUG: Passed dw_pcie_iatu_detect 670
DEBUG: Passed dw_pcie_iatu_unroll_enabled 592
DEBUG: Passed dw_pcie_iatu_unroll_enabled 594
DEBUG: Passed dw_pcie_iatu_detect 673
DEBUG: Passed dw_pcie_iatu_detect 676
DEBUG: Passed dw_pcie_iatu_detect 683
DEBUG: Passed dw_pcie_iatu_detect 686
DEBUG: Passed dw_pcie_iatu_detect 688
DEBUG: Passed dw_pcie_iatu_detect 692
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 605
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 607 max_region:8
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 611
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 618 max_region:8
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 622
DEBUG: Passed dw_pcie_iatu_detect_regions_unroll 629
DEBUG: Passed dw_pcie_iatu_detect 694
DEBUG: Passed dw_pcie_iatu_detect 698
rockchip-dw-pcie 3c0800000.pcie: iATU unroll: enabled
DEBUG: Passed dw_pcie_iatu_detect 701
rockchip-dw-pcie 3c0800000.pcie: Detected iATU regions: 8 outbound, 8 inbound
DEBUG: Passed dw_pcie_iatu_detect 704
DEBUG: Passed dw_pcie_host_init 402
DEBUG: Passed dw_pcie_host_init 404
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
DEBUG: Passed dw_pcie_host_init 410
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x1 linkup:0 ltssm:1 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
Freeing initrd memory: 26140K
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
rockchip-dw-pcie 3c0800000.pcie: Phy link never came up
DEBUG: Passed dw_pcie_host_init 413
DEBUG: Passed dw_pcie_host_init 415
rockchip-dw-pcie 3c0800000.pcie: PCI host bridge to bus 0002:20
pci_bus 0002:20: root bus resource [bus 20-2f]
pci_bus 0002:20: root bus resource [io  0x100000-0x1fffff] (bus address [0xff700000-0xff7fffff])
pci_bus 0002:20: root bus resource [mem 0x380000000-0x3bf6fffff] (bus address [0xc0000000-0xff6fffff])
pci 0002:20:00.0: [1d87:3566] type 01 class 0x060400
pci 0002:20:00.0: reg 0x10: [mem 0x00000000-0x3fffffff]
pci 0002:20:00.0: reg 0x14: [mem 0x00000000-0x3fffffff]
pci 0002:20:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
pci 0002:20:00.0: supports D1 D2
pci 0002:20:00.0: PME# supported from D0 D1 D3hot
pci 0002:20:00.0: Primary bus is hard wired to 0
pci 0002:20:00.0: bridge configuration invalid ([bus 01-ff]), reconfiguring
rockchip-dw-pcie 3c0800000.pcie: DEBUG: Passed rockchip_pcie_link_up 81 val:0x0 linkup:0 ltssm:0 (PCIE_L0S_ENTRY:0x11)
pci_bus 0002:21: busn_res: [bus 21-2f] end is updated to 21
pci 0002:20:00.0: BAR 0: no space for [mem size 0x40000000]
pci 0002:20:00.0: BAR 0: failed to assign [mem size 0x40000000]
pci 0002:20:00.0: BAR 1: no space for [mem size 0x40000000]
pci 0002:20:00.0: BAR 1: failed to assign [mem size 0x40000000]
pci 0002:20:00.0: BAR 6: assigned [mem 0x380000000-0x38000ffff pref]
pci 0002:20:00.0: PCI bridge to [bus 21]
DEBUG: Passed dw_pcie_host_init 417
Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
printk: console [ttyS2] disabled
fe660000.serial: ttyS2 at MMIO 0xfe660000 (irq = 28, base_baud = 1500000) is a 16550A
printk: console [ttyS2] enabled
printk: console [ttyS2] enabled
printk: bootconsole [uart8250] disabled
printk: bootconsole [uart8250] disabled
cacheinfo: Unable to detect cache hierarchy for CPU 0
brd: module loaded
loop: module loaded
ahci fc800000.sata: supply ahci not found, using dummy regulator
ahci fc800000.sata: supply phy not found, using dummy regulator
ahci fc800000.sata: supply target not found, using dummy regulator
ahci fc800000.sata: forcing port_map 0x0 -> 0x1
ahci fc800000.sata: AHCI 0001.0300 32 slots 1 ports 6 Gbps 0x1 impl platform mode
ahci fc800000.sata: flags: ncq sntf pm led clo only pmp fbs pio slum part ccc apst
ahci fc800000.sata: port 0 is not capable of FBS
scsi host0: ahci
ata1: SATA max UDMA/133 mmio [mem 0xfc800000-0xfc800fff] port 0x100 irq 18
rk_gmac-dwmac fe010000.ethernet: IRQ eth_lpi not found
rk_gmac-dwmac fe010000.ethernet: no regulator found
rk_gmac-dwmac fe010000.ethernet: clock input or output? (output).
rk_gmac-dwmac fe010000.ethernet: TX delay(0x4f).
rk_gmac-dwmac fe010000.ethernet: RX delay(0x26).
rk_gmac-dwmac fe010000.ethernet: integrated PHY? (no).
rk_gmac-dwmac fe010000.ethernet: init for RGMII
rk_gmac-dwmac fe010000.ethernet: User ID: 0x30, Synopsys ID: 0x51
rk_gmac-dwmac fe010000.ethernet:        DWMAC4/5
rk_gmac-dwmac fe010000.ethernet: DMA HW capability register supported
rk_gmac-dwmac fe010000.ethernet: RX Checksum Offload Engine supported
rk_gmac-dwmac fe010000.ethernet: TX Checksum insertion supported
rk_gmac-dwmac fe010000.ethernet: Wake-Up On Lan supported
rk_gmac-dwmac fe010000.ethernet: TSO supported
rk_gmac-dwmac fe010000.ethernet: Enable RX Mitigation via HW Watchdog Timer
rk_gmac-dwmac fe010000.ethernet: device MAC address ce:31:d3:ea:9f:ad
rk_gmac-dwmac fe010000.ethernet: Enabled RFS Flow TC (entries=10)
rk_gmac-dwmac fe010000.ethernet: TSO feature enabled
rk_gmac-dwmac fe010000.ethernet: Using 32 bits DMA width
rk_gmac-dwmac fe2a0000.ethernet: IRQ eth_lpi not found
rk_gmac-dwmac fe2a0000.ethernet: no regulator found
rk_gmac-dwmac fe2a0000.ethernet: clock input or output? (input).
rk_gmac-dwmac fe2a0000.ethernet: TX delay(0x3c).
rk_gmac-dwmac fe2a0000.ethernet: RX delay(0x2f).
rk_gmac-dwmac fe2a0000.ethernet: integrated PHY? (no).
rk_gmac-dwmac fe2a0000.ethernet: clock input from PHY
rk_gmac-dwmac fe2a0000.ethernet: init for RGMII
rk_gmac-dwmac fe2a0000.ethernet: User ID: 0x30, Synopsys ID: 0x51
rk_gmac-dwmac fe2a0000.ethernet:        DWMAC4/5
rk_gmac-dwmac fe2a0000.ethernet: DMA HW capability register supported
rk_gmac-dwmac fe2a0000.ethernet: RX Checksum Offload Engine supported
rk_gmac-dwmac fe2a0000.ethernet: TX Checksum insertion supported
rk_gmac-dwmac fe2a0000.ethernet: Wake-Up On Lan supported
rk_gmac-dwmac fe2a0000.ethernet: TSO supported
rk_gmac-dwmac fe2a0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
rk_gmac-dwmac fe2a0000.ethernet: Enabled RFS Flow TC (entries=10)
rk_gmac-dwmac fe2a0000.ethernet: TSO feature enabled
rk_gmac-dwmac fe2a0000.ethernet: Using 32 bits DMA width
ata1: SATA link down (SStatus 0 SControl 300)
ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
ehci-pci: EHCI PCI platform driver
ehci-platform: EHCI generic platform driver
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci-pci: OHCI PCI platform driver
ohci-platform: OHCI generic platform driver
xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
xhci-hcd xhci-hcd.0.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000000002010010
xhci-hcd xhci-hcd.0.auto: irq 19, io mem 0xfcc00000
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 3
xhci-hcd xhci-hcd.1.auto: hcc params 0x0220fe64 hci version 0x110 quirks 0x0000000002010010
xhci-hcd xhci-hcd.1.auto: irq 20, io mem 0xfd000000
hub 3-0:1.0: USB hub found
hub 3-0:1.0: 1 port detected
xhci-hcd xhci-hcd.1.auto: xHCI Host Controller
xhci-hcd xhci-hcd.1.auto: new USB bus registered, assigned bus number 4
xhci-hcd xhci-hcd.1.auto: Host supports USB 3.0 SuperSpeed
usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
hub 4-0:1.0: USB hub found
hub 4-0:1.0: 1 port detected
usbcore: registered new interface driver usb-storage
i2c_dev: i2c /dev entries driver
rk808 0-0020: chip id: 0x8090
random: fast init done
rk808-regulator rk808-regulator: there is no dvs0 gpio
rk808-regulator rk808-regulator: there is no dvs1 gpio
rk808-rtc rk808-rtc: registered as rtc0
rk808-rtc rk808-rtc: setting system clock to 2017-08-05T09:23:48 UTC (1501925028)
rtc-hym8563 3-0051: could not init device, -6
rockchip-thermal fe710000.tsadc: Missing tshut mode property, using default (gpio)
rockchip-thermal fe710000.tsadc: Missing tshut-polarity property, using default (low)
sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
Synopsys Designware Multimedia Card Interface Driver
sdhci-pltfm: SDHCI platform and OF driver helper
dwmmc_rockchip fe2b0000.mmc: IDMAC supports 32-bit address mode.
dwmmc_rockchip fe2b0000.mmc: Using internal DMA controller.
dwmmc_rockchip fe2b0000.mmc: Version ID is 270a
SMCCC: SOC_ID: ARCH_SOC_ID not implemented, skipping ....
dwmmc_rockchip fe2b0000.mmc: DW MMC controller at irq 24,32 bit host data width,256 deep fifo
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver
dwmmc_rockchip fe2b0000.mmc: Got CD GPIO
NET: Registered PF_INET6 protocol family
Segment Routing with IPv6
In-situ OAM (IOAM) with IPv6
sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
NET: Registered PF_PACKET protocol family
registered taskstats version 1
mmc_host mmc0: Bus speed (slot 0) = 375000Hz (slot req 400000Hz, actual 375000HZ div = 0)
mmc1: SDHCI controller on fe310000.mmc [fe310000.mmc] using ADMA
mmc1: new HS200 MMC card at address 0001
mmcblk1: mmc1:0001 SPeMMC 14.5 GiB
mmcblk1boot0: mmc1:0001 SPeMMC 4.00 MiB
mmcblk1boot1: mmc1:0001 SPeMMC 4.00 MiB
mmcblk1rpmb: mmc1:0001 SPeMMC 4.00 MiB, chardev (248:0)
mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 100000000Hz, actual 50000000HZ div = 0)
dwmmc_rockchip fe2b0000.mmc: Successfully tuned phase to 354
mmc0: new ultra high speed SDR50 SDXC card at address aaaa
mmcblk0: mmc0:aaaa SL64G 59.5 GiB
 mmcblk0: p1 p2 p3
DEBUG: Passed rtl8367s_hw_reset 2240 do reset!
DEBUG: Passed rtk_switch_probe 2154 chip: 0x6367
RTL8367RB Switch Init Successfully !!!
DEBUG: Passed init_gsw 2358 rgmii+rgmii
d0
Freeing unused kernel memory: 2368K
Run /init as init process
Starting syslogd: OK
Starting klogd: OK
Running sysctl: OK
Populating /dev using udev: udevd[104]: starting version 3.2.9
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
random: udevd: uninitialized urandom read (16 bytes read)
udevd[105]: starting eudev-3.2.9
done
Saving random seed: OK
Starting network: OK
Starting dhcpcd...
dhcpcd-9.4.0 starting
dev: loaded udev
forked to background, child pid 149
no interfaces have a carrier
rk_gmac-dwmac fe010000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
dwmac4: Master AXI performs any burst length
rk_gmac-dwmac fe010000.ethernet eth0: No Safety Features support found
rk_gmac-dwmac fe010000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
rk_gmac-dwmac fe010000.ethernet eth0: registered PTP clock
rk_gmac-dwmac fe010000.ethernet eth0: configuring for fixed/rgmii link mode
rk_gmac-dwmac fe010000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
rk_gmac-dwmac fe2a0000.ethernet eth1: PHY [stmmac-0:00] driver [RTL8211F Gigabit Ethernet] (irq=POLL)
rk_gmac-dwmac fe2a0000.ethernet eth1: Register MEM_TYPE_PAGE_POOL RxQ-0
dwmac4: Master AXI performs any burst length
rk_gmac-dwmac fe2a0000.ethernet eth1: No Safety Features support found
rk_gmac-dwmac fe2a0000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported
rk_gmac-dwmac fe2a0000.ethernet eth1: registered PTP clock
rk_gmac-dwmac fe2a0000.ethernet eth1: configuring for phy/rgmii link mode
IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
random: crng init done
random: 5 urandom warning(s) missed due to ratelimiting
ssh-keygen: generating new host keys: RSA rk_gmac-dwmac fe2a0000.ethernet eth1: Link is Up - 1Gbps/Full - flow control rx/tx
IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes read

drivers/pci/controller/dwc/pcie-designware-host.c

@@ -317,46 +317,46 @@ int dw_pcie_host_init(struct pcie_port *pp)
 		if (IS_ERR(pci->dbi_base))
 			return PTR_ERR(pci->dbi_base);
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	bridge = devm_pci_alloc_host_bridge(dev, 0);
 	if (!bridge)
 		return -ENOMEM;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	pp->bridge = bridge;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	/* Get the I/O range from DT */
 	win = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
 	if (win) {
 		pp->io_size = resource_size(win->res);
 		pp->io_bus_addr = win->res->start - win->offset;
 		pp->io_base = pci_pio_to_address(win->res->start);
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (pci->link_gen < 1)
 		pci->link_gen = of_pci_get_max_link_speed(np);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	/* Set default bus ops */
 	bridge->ops = &dw_pcie_ops;
 	bridge->child_ops = &dw_child_pcie_ops;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (pp->ops->host_init) {
 		ret = pp->ops->host_init(pp);
 		if (ret)
 			return ret;
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (pci_msi_enabled()) {
 		pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
 				     of_property_read_bool(np, "msi-parent") ||
 				     of_property_read_bool(np, "msi-map"));
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		if (!pp->num_vectors) {
 			pp->num_vectors = MSI_DEF_NUM_VECTORS;
 		} else if (pp->num_vectors > MAX_MSI_IRQS) {
 			dev_err(dev, "Invalid number of vectors\n");
 			return -EINVAL;
 		}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		if (pp->ops->msi_host_init) {
 			ret = pp->ops->msi_host_init(pp);
 			if (ret < 0)
@@ -370,9 +370,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
 						return pp->msi_irq;
 				}
 			}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 			pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 			ret = dw_pcie_allocate_domains(pp);
 			if (ret)
 				return ret;
@@ -397,23 +397,24 @@ int dw_pcie_host_init(struct pcie_port *pp)
 			}
 		}
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	dw_pcie_iatu_detect(pci);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	dw_pcie_setup_rc(pp);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (!dw_pcie_link_up(pci) && pci->ops && pci->ops->start_link) {
 		ret = pci->ops->start_link(pci);
 		if (ret)
 			goto err_free_msi;
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	/* Ignore errors, the link may come up later */
 	dw_pcie_wait_for_link(pci);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	bridge->sysdata = pp;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	ret = pci_host_probe(bridge);
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (!ret)
 		return 0;
 

drivers/pci/controller/dwc/pcie-designware.c

@@ -589,8 +589,9 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
 static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
 {
 	u32 val;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (val == 0xffffffff)
 		return 1;
 
@@ -601,30 +602,31 @@ static void dw_pcie_iatu_detect_regions_unroll(struct dw_pcie *pci)
 {
 	int max_region, i, ob = 0, ib = 0;
 	u32 val;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	max_region = min((int)pci->atu_size / 512, 256);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d max_region:%d\n",__FUNCTION__,__LINE__,max_region);
 	for (i = 0; i < max_region; i++) {
 		dw_pcie_writel_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
 					0x11110000);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		val = dw_pcie_readl_ob_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
 		if (val == 0x11110000)
 			ob++;
 		else
 			break;
 	}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d max_region:%d \n",__FUNCTION__,__LINE__,max_region);
 	for (i = 0; i < max_region; i++) {
 		dw_pcie_writel_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET,
 					0x11110000);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		val = dw_pcie_readl_ib_unroll(pci, i, PCIE_ATU_UNR_LOWER_TARGET);
 		if (val == 0x11110000)
 			ib++;
 		else
 			break;
 	}
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	pci->num_ib_windows = ib;
 	pci->num_ob_windows = ob;
 }
@@ -665,34 +667,41 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
 {
 	struct device *dev = pci->dev;
 	struct platform_device *pdev = to_platform_device(dev);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	if (pci->version >= 0x480A || (!pci->version &&
 				       dw_pcie_iatu_unroll_enabled(pci))) {
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		pci->iatu_unroll_enabled = true;
 		if (!pci->atu_base) {
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 			struct resource *res =
 				platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
 			if (res) {
 				pci->atu_size = resource_size(res);
 				pci->atu_base = devm_ioremap_resource(dev, res);
 			}
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 			if (!pci->atu_base || IS_ERR(pci->atu_base))
 				pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		}
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		if (!pci->atu_size)
 			/* Pick a minimal default, enough for 8 in and 8 out windows */
 			pci->atu_size = SZ_4K;
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 		dw_pcie_iatu_detect_regions_unroll(pci);
-	} else
-		dw_pcie_iatu_detect_regions(pci);
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
+	} else{
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
+		dw_pcie_iatu_detect_regions(pci);}
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	dev_info(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
 		"enabled" : "disabled");
-
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 	dev_info(pci->dev, "Detected iATU regions: %u outbound, %u inbound",
 		 pci->num_ob_windows, pci->num_ib_windows);
+printk(KERN_ALERT "DEBUG: Passed %s %d \n",__FUNCTION__,__LINE__);
 }
 
 void dw_pcie_setup(struct dw_pcie *pci)