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net: dsa: add rgmii/sgmii functions
traffic now works, but all ports routed to eth0
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frank-w committed Nov 13, 2021
1 parent c795ca3 commit e9ec03c13f235a810e08f9797a0e826b994a8743
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Showing 2 changed files with 154 additions and 2 deletions.
@@ -1384,8 +1384,143 @@ rtk_api_ret_t rtk_port_phyEnableAll_set(rtk_enable_t enable)

}

rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay) {return 0;}
rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state) {return 0;}
rtk_api_ret_t rtk_port_rgmiiDelayExt_set(rtk_port_t port, rtk_data_t txDelay, rtk_data_t rxDelay)
{
rtk_api_ret_t retVal;
rtk_uint32 regAddr, regData;

/* Check initialization state */
RTK_CHK_INIT_STATE();

/* Check Port Valid */
RTK_CHK_PORT_IS_EXT(port);

if ((txDelay > 1) || (rxDelay > 7))
return RT_ERR_INPUT;

if(port == EXT_PORT0)
regAddr = RTL8367C_REG_EXT1_RGMXF;
else if(port == EXT_PORT1)
regAddr = RTL8367C_REG_EXT2_RGMXF;
else
return RT_ERR_INPUT;

if ((retVal = rtl8367c_getAsicReg(regAddr, &regData)) != RT_ERR_OK)
return retVal;

regData = (regData & 0xFFF0) | ((txDelay << 3) & 0x0008) | (rxDelay & 0x0007);

if ((retVal = rtl8367c_setAsicReg(regAddr, regData)) != RT_ERR_OK)
return retVal;

return RT_ERR_OK;
}

ret_t rtl8367c_setSgmiiNway(rtk_uint32 ext_id, rtk_uint32 state)
{
rtk_uint32 retVal, regValue, type, running = 0, retVal2;

if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0249)) != RT_ERR_OK)
return retVal;

if((retVal = rtl8367c_getAsicReg(0x1300, &regValue)) != RT_ERR_OK)
return retVal;

if((retVal = rtl8367c_setAsicReg(0x13C2, 0x0000)) != RT_ERR_OK)
return retVal;

switch (regValue)
{
case 0x0276:
case 0x0597:
case 0x6367:
type = 0;
break;
case 0x0652:
case 0x6368:
type = 1;
break;
case 0x0801:
case 0x6511:
type = 2;
break;
default:
return RT_ERR_FAILED;
}

if(type == 0)
{
if (1 == ext_id)
{
if ((retVal = rtl8367c_getAsicRegBit(0x130c, 5, &running))!=RT_ERR_OK)
return retVal;

if(running == 1)
{
if ((retVal = rtl8367c_setAsicRegBit(0x130c, 5, 0))!=RT_ERR_OK)
return retVal;
}

retVal = rtl8367c_setAsicReg(0x6601, 0x0002);

if(retVal == RT_ERR_OK)
retVal = rtl8367c_setAsicReg(0x6600, 0x0080);

if(retVal == RT_ERR_OK)
retVal = rtl8367c_getAsicReg(0x6602, &regValue);

if(retVal == RT_ERR_OK)
{
if(state)
regValue |= 0x0200;
else
regValue &= ~0x0200;

regValue |= 0x0100;
}

if(retVal == RT_ERR_OK)
retVal = rtl8367c_setAsicReg(0x6602, regValue);

if(retVal == RT_ERR_OK)
retVal = rtl8367c_setAsicReg(0x6601, 0x0002);

if(retVal == RT_ERR_OK)
retVal = rtl8367c_setAsicReg(0x6600, 0x00C0);

if(running == 1)
{
if ((retVal2 = rtl8367c_setAsicRegBit(0x130c, 5, 1))!=RT_ERR_OK)
return retVal2;
}

if(retVal != RT_ERR_OK)
return retVal;
}
else
return RT_ERR_PORT_ID;
}
return RT_ERR_OK;
}

rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state)
{
rtk_uint32 ext_id;

/* Check initialization state */
RTK_CHK_INIT_STATE();

/* Check Port Valid */
if(rtk_switch_isSgmiiPort(port) != RT_ERR_OK)
return RT_ERR_PORT_ID;

if(state >= RTK_ENABLE_END)
return RT_ERR_INPUT;

ext_id = port - 15;
return rtl8367c_setSgmiiNway(ext_id, (rtk_uint32)state);
}


static void set_rtl8367s_sgmii(void)
{
@@ -87,6 +87,9 @@ typedef unsigned int rtk_uint32;
#define RTL8367C_SELECT_GMII_1_OFFSET 4
#define RTL8367C_SELECT_GMII_2_MASK 0xF

#define RTL8367C_REG_EXT2_RGMXF 0x13c5


#define SGMII_INIT_SIZE 1183
rtk_uint8 Sgmii_Init[SGMII_INIT_SIZE] = {
0x02,0x03,0x81,0xE4,0xF5,0xA8,0xD2,0xAF,
@@ -889,6 +892,20 @@ rtk_api_ret_t rtk_switch_isHsgPort(rtk_port_t logicalPort)
return RT_ERR_FAILED;
}

rtk_api_ret_t rtk_switch_isSgmiiPort(rtk_port_t logicalPort)
{
if(init_state != INIT_COMPLETED)
return RT_ERR_NOT_INIT;

if(logicalPort >= RTK_SWITCH_PORT_NUM)
return RT_ERR_FAILED;

if( ((0x01 << logicalPort) & halCtrl->sg_logical_portmask) != 0)
return RT_ERR_OK;
else
return RT_ERR_FAILED;
}

rtk_uint32 rtk_switch_port_L2P_get(rtk_port_t logicalPort)
{
if(init_state != INIT_COMPLETED)

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