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net: dsa: rtl8367: add rtk_vlan_init
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@frank-w
frank-w committed Nov 14, 2021
1 parent 077c18d commit ebb051a52704d976a63e3ab56a00f541b9d376b1
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Showing 2 changed files with 174 additions and 1 deletion.
126 drivers/net/dsa/rtl8367s_mdio.c
View file
@@ -1082,6 +1082,60 @@ ret_t rtl8367c_setAsicVlanMemberConfig(rtk_uint32 index, rtl8367c_vlanconfiguser

return RT_ERR_OK;
}

ret_t rtl8367c_setAsicVlanEgressTagMode(rtk_uint32 port, rtl8367c_egtagmode tagMode)
{
if(port > RTL8367C_PORTIDMAX)
return RT_ERR_PORT_ID;

if(tagMode >= EG_TAG_MODE_END)
return RT_ERR_INPUT;

return rtl8367c_setAsicRegBits(RTL8367C_PORT_MISC_CFG_REG(port), RTL8367C_VLAN_EGRESS_MODE_MASK, tagMode);
}

ret_t rtl8367c_setAsicVlanPortBasedVID(rtk_uint32 port, rtk_uint32 index, rtk_uint32 pri)
{
rtk_uint32 regAddr, bit_mask;
ret_t retVal;

if(port > RTL8367C_PORTIDMAX)
return RT_ERR_PORT_ID;

if(index > RTL8367C_CVIDXMAX)
return RT_ERR_VLAN_ENTRY_NOT_FOUND;

if(pri > RTL8367C_PRIMAX)
return RT_ERR_QOS_INT_PRIORITY;

regAddr = RTL8367C_VLAN_PVID_CTRL_REG(port);
bit_mask = RTL8367C_PORT_VIDX_MASK(port);
retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, index);
if(retVal != RT_ERR_OK)
return retVal;

regAddr = RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port);
bit_mask = RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port);
retVal = rtl8367c_setAsicRegBits(regAddr, bit_mask, pri);
if(retVal != RT_ERR_OK)
return retVal;

return RT_ERR_OK;
}

ret_t rtl8367c_setAsicVlanIngressFilter(rtk_uint32 port, rtk_uint32 enabled)
{
if(port > RTL8367C_PORTIDMAX)
return RT_ERR_PORT_ID;

return rtl8367c_setAsicRegBit(RTL8367C_VLAN_INGRESS_REG, port, enabled);
}

ret_t rtl8367c_setAsicVlanFilter(rtk_uint32 enabled)
{
return rtl8367c_setAsicRegBit(RTL8367C_REG_VLAN_CTRL, RTL8367C_VLAN_CTRL_OFFSET, enabled);
}

//============================================= RTK functions ==========================================================

rtk_api_ret_t rtk_port_macForceLinkExt_set(rtk_port_t port, rtk_mode_ext_t mode, rtk_port_mac_ability_t *pPortability)
@@ -1367,7 +1421,77 @@ rtk_api_ret_t rtk_port_sgmiiNway_set(rtk_port_t port, rtk_enable_t state)
// ============================================ RTK VLAN functions ==========================================================
rtk_api_ret_t rtk_vlan_reset(void) {return 0;}

rtk_api_ret_t rtk_vlan_init(void) {return 0;}
rtk_api_ret_t rtk_vlan_init(void)
{
rtk_api_ret_t retVal;
rtk_uint32 i;
rtl8367c_user_vlan4kentry vlan4K;
rtl8367c_vlanconfiguser vlanMC;

/* Check initialization state */
RTK_CHK_INIT_STATE();

/* Clean Database */
memset(vlan_mbrCfgVid, 0x00, sizeof(rtk_vlan_t) * RTL8367C_CVIDXNO);
memset(vlan_mbrCfgUsage, 0x00, sizeof(vlan_mbrCfgType_t) * RTL8367C_CVIDXNO);

/* clean 32 VLAN member configuration */
for (i = 0; i <= RTL8367C_CVIDXMAX; i++)
{
vlanMC.evid = 0;
vlanMC.mbr = 0;
vlanMC.fid_msti = 0;
vlanMC.envlanpol = 0;
vlanMC.meteridx = 0;
vlanMC.vbpen = 0;
vlanMC.vbpri = 0;
if ((retVal = rtl8367c_setAsicVlanMemberConfig(i, &vlanMC)) != RT_ERR_OK)
return retVal;
}

/* Set a default VLAN with vid 1 to 4K table for all ports */
memset(&vlan4K, 0, sizeof(rtl8367c_user_vlan4kentry));
vlan4K.vid = 1;
vlan4K.mbr = RTK_PHY_PORTMASK_ALL;
vlan4K.untag = RTK_PHY_PORTMASK_ALL;
vlan4K.fid_msti = 0;
if ((retVal = rtl8367c_setAsicVlan4kEntry(&vlan4K)) != RT_ERR_OK)
return retVal;

/* Also set the default VLAN to 32 member configuration index 0 */
memset(&vlanMC, 0, sizeof(rtl8367c_vlanconfiguser));
vlanMC.evid = 1;
vlanMC.mbr = RTK_PHY_PORTMASK_ALL;
vlanMC.fid_msti = 0;
if ((retVal = rtl8367c_setAsicVlanMemberConfig(0, &vlanMC)) != RT_ERR_OK)
return retVal;

/* Set all ports PVID to default VLAN and tag-mode to original */
RTK_SCAN_ALL_PHY_PORTMASK(i)
{
if ((retVal = rtl8367c_setAsicVlanPortBasedVID(i, 0, 0)) != RT_ERR_OK)
return retVal;
if ((retVal = rtl8367c_setAsicVlanEgressTagMode(i, EG_TAG_MODE_ORI)) != RT_ERR_OK)
return retVal;
}

/* Updata Databse */
vlan_mbrCfgUsage[0] = MBRCFG_USED_BY_VLAN;
vlan_mbrCfgVid[0] = 1;

/* Enable Ingress filter */
RTK_SCAN_ALL_PHY_PORTMASK(i)
{
if ((retVal = rtl8367c_setAsicVlanIngressFilter(i, ENABLED)) != RT_ERR_OK)
return retVal;
}

/* enable VLAN */
if ((retVal = rtl8367c_setAsicVlanFilter(ENABLED)) != RT_ERR_OK)
return retVal;

return RT_ERR_OK;
}

rtk_api_ret_t rtk_vlan_portPvid_set(rtk_port_t port, rtk_vlan_t pvid, rtk_pri_t priority) {return 0;}

49 drivers/net/dsa/rtl8367s_mdio.h
View file
@@ -90,6 +90,8 @@ typedef unsigned int rtk_uint32;

#define RTL8367C_REG_EXT2_RGMXF 0x13c5

#define RTL8367C_PORTNO 11
#define RTL8367C_PORTIDMAX (RTL8367C_PORTNO-1)
#define RTL8367C_FIDMAX 0xF
#define RTL8367C_VIDMAX 0xFFF
#define RTL8367C_EVIDMAX 0x1FFF
@@ -99,6 +101,34 @@ typedef unsigned int rtk_uint32;
#define RTL8367C_VLAN_4KTABLE_LEN (3)
#define RTL8367C_VLAN_MBRCFG_LEN (4)

#define RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x30
#define RTL8367C_VLAN_EGRESS_MODE_MASK RTL8367C_PORT0_MISC_CFG_VLAN_EGRESS_MODE_MASK

#define RTL8367C_REG_VLAN_PVID_CTRL0 0x0700
#define RTL8367C_VLAN_PVID_CTRL_BASE RTL8367C_REG_VLAN_PVID_CTRL0
#define RTL8367C_VLAN_PVID_CTRL_REG(port) (RTL8367C_VLAN_PVID_CTRL_BASE + (port >> 1))

#define RTL8367C_PORT0_VIDX_MASK 0x1F
#define RTL8367C_PORT_VIDX_OFFSET(port) ((port &1)<<3)
#define RTL8367C_PORT_VIDX_MASK(port) (RTL8367C_PORT0_VIDX_MASK << RTL8367C_PORT_VIDX_OFFSET(port))

#define RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0 0x0851
#define RTL8367C_VLAN_PORTBASED_PRIORITY_BASE RTL8367C_REG_VLAN_PORTBASED_PRIORITY_CTRL0
#define RTL8367C_VLAN_PORTBASED_PRIORITY_REG(port) (RTL8367C_VLAN_PORTBASED_PRIORITY_BASE + (port >> 2))
#define RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port) ((port & 0x3) << 2)
#define RTL8367C_VLAN_PORTBASED_PRIORITY_MASK(port) (0x7 << RTL8367C_VLAN_PORTBASED_PRIORITY_OFFSET(port))

#define RTL8367C_REG_VLAN_INGRESS 0x07a9
#define RTL8367C_VLAN_INGRESS_REG RTL8367C_REG_VLAN_INGRESS

#define RTL8367C_REG_VLAN_CTRL 0x07a8
#define RTL8367C_VLAN_CTRL_OFFSET 0

#define RTL8367C_REG_PORT0_MISC_CFG 0x000e
#define RTL8367C_PORT_MISC_CFG_BASE RTL8367C_REG_PORT0_MISC_CFG
#define RTL8367C_PORT_MISC_CFG_REG(port) (RTL8367C_PORT_MISC_CFG_BASE + (port << 5))


#define RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0 0x0728
#define RTL8367C_VLAN_MEMBER_CONFIGURATION_BASE RTL8367C_REG_VLAN_MEMBER_CONFIGURATION0_CTRL0
#define RTL8367C_REG_TABLE_ACCESS_ADDR 0x0501
@@ -824,6 +854,15 @@ typedef enum vlan_mbrCfgType_e
static rtk_vlan_t vlan_mbrCfgVid[RTL8367C_CVIDXNO];
static vlan_mbrCfgType_t vlan_mbrCfgUsage[RTL8367C_CVIDXNO];

typedef enum
{
EG_TAG_MODE_ORI = 0,
EG_TAG_MODE_KEEP,
EG_TAG_MODE_PRI_TAG,
EG_TAG_MODE_REAL_KEEP,
EG_TAG_MODE_END
} rtl8367c_egtagmode;

rtk_api_ret_t rtk_vlan_reset(void);

rtk_api_ret_t rtk_vlan_init(void);
@@ -845,9 +884,18 @@ rtk_api_ret_t rtk_switch_logicalPortCheck(rtk_port_t logicalPort)

return RT_ERR_OK;
}
rtk_uint32 rtk_switch_phyPortMask_get(void)
{
if(init_state != INIT_COMPLETED)
return 0x00; /* No port in portmask */

return (halCtrl->phy_portmask);
}
#define RTK_SCAN_ALL_LOG_PORT(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( rtk_switch_logicalPortCheck(__port__) == RT_ERR_OK)
#define RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__) (((__portmask__).bits[0] & (0x00000001 << __port__)) ? 1 : 0)
#define RTK_PORTMASK_SCAN(__portmask__, __port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if(RTK_PORTMASK_IS_PORT_SET(__portmask__, __port__))
#define RTK_PHY_PORTMASK_ALL (rtk_switch_phyPortMask_get())
#define RTK_SCAN_ALL_PHY_PORTMASK(__port__) for(__port__ = 0; __port__ < RTK_SWITCH_PORT_NUM; __port__++) if( (rtk_switch_phyPortMask_get() & (0x00000001 << __port__)))

rtk_api_ret_t rtk_switch_isExtPort(rtk_port_t logicalPort)
{
@@ -1020,6 +1068,7 @@ rtk_uint32 rtk_switch_maxMeterId_get(void)
} \
}while(0)
*/

#define RTK_MAX_METER_ID (rtk_switch_maxMeterId_get())

#endif /* __RTL8367_MDIO_H */

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