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  0x08\n  latency time =                0x00\n  header type =                 0x01\n  BIST =                        0x00\n  base address 0 =              0x28200004\n  base address 1 =              0x00000000\n  primary bus number =          0x00\n  secondary bus number =        0x01\n  subordinate bus number =      0x01\n  secondary latency timer =     0x00\n  IO base =                     0xf1\n  IO limit =                    0x01\n  secondary status =            0x0000\n  memory base =                 0x2830\n  memory limit =                0x2830\n  prefetch memory base =        0xfff1\n  prefetch memory limit =       0x0001\n  prefetch memory base upper =  0x00000000\n  prefetch memory limit upper = 0x00000000\n  IO base upper 16 bits =       0x0000\n  IO limit upper 16 bits =      0x0000\n  expansion ROM base address =  0x00000000\n  interrupt line =              0x00\n  interrupt pin =               0x01\n  bridge control =              0x0000\n\nFound PCI device 01.00.00:\n  vendor ID =                   0x1cc1\n  device ID =                   0x5766\n  command register ID =         0x0006\n  status register =             0x0010\n  revision ID =                 0x01\n  class code =                  0x01 (Mass storage controller)\n  sub class code =              0x08\n  programming interface =       0x02\n  cache line =                  0x08\n  latency time =                0x00\n  header type =                 0x00\n  BIST =                        0x00\n  base address 0 =              0x28300004\n  base address 1 =              0x00000000\n  base address 2 =              0x00000000\n  base address 3 =              0x00000000\n  base address 4 =              0x00000000\n  base address 5 =              0x28304000\n  cardBus CIS pointer =         0x00000000\n  sub system vendor ID =        0x1cc1\n  sub system ID =               0x5766\n  expansion ROM base address =  0x00000000\n  interrupt line =              0x00\n  interrupt pin =               0x01\n  min Grant =                   0x00\n  max Latency =                 0x00\nBPI-R4> nvme scan\nBPI-R4> nvme info\nDevice 0: Vendor: 0x1cc1 Rev: VC0S036H Prod: 2M232LAJ8HNT\n            Type: Hard Disk\n            Capacity: 476940.0 MB = 465.7 GB (976773168 x 512)\nBPI-R4> pci 0\nScanning PCI devices on bus 0\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\n00.00.00   0x14c3     0x7988     Bridge device           0x04\nBPI-R4> pci 1\nScanning PCI devices on bus 1\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\n01.00.00   0x1cc1     0x5766     Mass storage controller 0x08\nBPI-R4> pci 2\nScanning PCI devices on bus 2\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\nBPI-R4> pci 3\nScanning PCI devices on bus 3\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\nBPI-R4>","shortMessageHtmlLink":"arm: dts: enable pcie in sd dts too"}},{"before":"67aef5bf5f6cc48a646406146dc2409eb2fe15de","after":"d0faf4425360d7dd10927ab57693245216b8873f","ref":"refs/heads/2024-01-bpi-r3mini","pushedAt":"2024-04-03T12:44:12.000Z","pushType":"push","commitsCount":4,"pusher":{"login":"frank-w","name":"Frank Wunderlich","path":"/frank-w","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/6653828?s=80&v=4"},"commit":{"message":"arm: dts: enable pcie in sd dts too\n\ndisable pcie2 (key-b) to have access to nvme\n\nBPI-R4> usb start\nstarting USB...\nBus xhci@11200000: xhci-mtk xhci@11200000: hcd: 0x0000000011200000, ippc: 0x0000000011203e00\nxhci-mtk xhci@11200000: ports disabled mask: u3p-0x0, u2p-0x0\nxhci-mtk xhci@11200000: u2p:1, u3p:1\nRegister 200010f NbrPorts 2\nStarting the controller\nUSB XHCI 1.10\nscanning bus xhci@11200000 for devices... 5 USB Device(s) found\n       scanning usb for storage devices... 1 Storage Device(s) found\nBPI-R4> fatload usb 0:1 $loadaddr uboot_2024-01/bpi-r4_pcie_sam.bin\n698984 bytes read in 63 ms (10.6 MiB/s)\nBPI-R4> go $loadaddr\n-## Starting application at 0x46000000 ...\n\nU-Boot 2024.01-bpi-r3mini-00041-g30636fc11e8b-dirty (Apr 03 2024 - 14:33:56 +0200)\n\nCPU:   MediaTek MT7988\nModel: mt7988-rfb\nDRAM:  4 GiB\nCore:  50 devices, 19 uclasses, devicetree: separate\nMMC:   mmc@11230000: 0\nLoading Environment from nowhere... OK\nIn:    serial@11000000\nOut:   serial@11000000\nErr:   serial@11000000\nNet:\nWarning: ethernet@15100000 (eth0) using random MAC address - ea:5a:fa:b3:56:90\neth0: ethernet@15100000\nBPI-R4> pci enum\ndrivers/pci/pcie_mediatek_gen3.c:mtk_pcie_startup_port[262] detected a card\nset trans table 0: 0x28200000 0x28200000, 0x7e00000\ndrivers/pci/pcie_mediatek_gen3.c:mtk_pcie_startup_port[262] detected a card\nset trans table 0: 0x30200000 0x30200000, 0x7e00000\ndrivers/pci/pcie_mediatek_gen3.c:mtk_pcie_startup_port[262] detected a card\nset trans table 0: 0x38200000 0x38200000, 0x7e00000\nBPI-R4> pci list\n\nFound PCI device 00.00.00:\n  vendor ID =                   0x14c3\n  device ID =                   0x7988\n  command register ID =         0x0006\n  status register =             0x0010\n  revision ID =                 0x01\n  class code =                  0x06 (Bridge device)\n  sub class code =              0x04\n  programming interface =       0x00\n  cache line =                  0x08\n  latency time =                0x00\n  header type =                 0x01\n  BIST =                        0x00\n  base address 0 =              0x28200004\n  base address 1 =              0x00000000\n  primary bus number =          0x00\n  secondary bus number =        0x01\n  subordinate bus number =      0x01\n  secondary latency timer =     0x00\n  IO base =                     0xf1\n  IO limit =                    0x01\n  secondary status =            0x0000\n  memory base =                 0x2830\n  memory limit =                0x2830\n  prefetch memory base =        0xfff1\n  prefetch memory limit =       0x0001\n  prefetch memory base upper =  0x00000000\n  prefetch memory limit upper = 0x00000000\n  IO base upper 16 bits =       0x0000\n  IO limit upper 16 bits =      0x0000\n  expansion ROM base address =  0x00000000\n  interrupt line =              0x00\n  interrupt pin =               0x01\n  bridge control =              0x0000\n\nFound PCI device 01.00.00:\n  vendor ID =                   0x1cc1\n  device ID =                   0x5766\n  command register ID =         0x0006\n  status register =             0x0010\n  revision ID =                 0x01\n  class code =                  0x01 (Mass storage controller)\n  sub class code =              0x08\n  programming interface =       0x02\n  cache line =                  0x08\n  latency time =                0x00\n  header type =                 0x00\n  BIST =                        0x00\n  base address 0 =              0x28300004\n  base address 1 =              0x00000000\n  base address 2 =              0x00000000\n  base address 3 =              0x00000000\n  base address 4 =              0x00000000\n  base address 5 =              0x28304000\n  cardBus CIS pointer =         0x00000000\n  sub system vendor ID =        0x1cc1\n  sub system ID =               0x5766\n  expansion ROM base address =  0x00000000\n  interrupt line =              0x00\n  interrupt pin =               0x01\n  min Grant =                   0x00\n  max Latency =                 0x00\nBPI-R4> nvme scan\nBPI-R4> nvme info\nDevice 0: Vendor: 0x1cc1 Rev: VC0S036H Prod: 2M232LAJ8HNT\n            Type: Hard Disk\n            Capacity: 476940.0 MB = 465.7 GB (976773168 x 512)\nBPI-R4> pci 0\nScanning PCI devices on bus 0\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\n00.00.00   0x14c3     0x7988     Bridge device           0x04\nBPI-R4> pci 1\nScanning PCI devices on bus 1\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\n01.00.00   0x1cc1     0x5766     Mass storage controller 0x08\nBPI-R4> pci 2\nScanning PCI devices on bus 2\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\nBPI-R4> pci 3\nScanning PCI devices on bus 3\nBusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n_____________________________________________________________\nBPI-R4>","shortMessageHtmlLink":"arm: dts: enable pcie in sd dts too"}},{"before":null,"after":"1a77c35dd64e0ce75c53341e7392d9d764324129","ref":"refs/heads/2024-04-bpi-r3mini","pushedAt":"2024-04-03T12:10:05.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"frank-w","name":"Frank Wunderlich","path":"/frank-w","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/6653828?s=80&v=4"},"commit":{"message":"en8811h: replace air_mii_cl45_{read,write} by phy_{read,write}_mmd\n\nand use the function defined in include/eth_phy.h\n\nair_mii_cl45_read  -> phy_read_mmd\nair_mii_cl45_write -> phy_write_mmd\n\nsuggested by eric","shortMessageHtmlLink":"en8811h: replace air_mii_cl45_{read,write} by phy_{read,write}_mmd"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEOD4YigA","startCursor":null,"endCursor":null}},"title":"Activity · frank-w/u-boot"}