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Import device-tree files from Linux 5.17
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Sponsored by:   Beckhoff Automation GmbH & Co. KG
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evadot committed Aug 10, 2022
2 parents 8cc087a + b7d8b56 commit e67e856
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4 changes: 3 additions & 1 deletion sys/contrib/device-tree/Bindings/Makefile
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Expand Up @@ -65,7 +65,9 @@ DT_DOCS = $(patsubst $(srctree)/%,%,$(shell $(find_all_cmd)))
override DTC_FLAGS := \
-Wno-avoid_unnecessary_addr_size \
-Wno-graph_child_address \
-Wno-interrupt_provider
-Wno-interrupt_provider \
-Wno-unique_unit_address \
-Wunique_unit_address_if_enabled

# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
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27 changes: 25 additions & 2 deletions sys/contrib/device-tree/Bindings/arm/apple.yaml
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Expand Up @@ -12,12 +12,19 @@ maintainers:
description: |
ARM platforms using SoCs designed by Apple Inc., branded "Apple Silicon".
This currently includes devices based on the "M1" SoC, starting with the
three Mac models released in late 2020:
This currently includes devices based on the "M1" SoC:
- Mac mini (M1, 2020)
- MacBook Pro (13-inch, M1, 2020)
- MacBook Air (M1, 2020)
- iMac (24-inch, M1, 2021)
And devices based on the "M1 Pro" and "M1 Max" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021)
- MacBook Pro (14-inch, M1 Max, 2021)
- MacBook Pro (16-inch, M1 Pro, 2021)
- MacBook Pro (16-inch, M1 Max, 2021)
The compatible property should follow this format:
Expand Down Expand Up @@ -56,8 +63,24 @@ properties:
- apple,j274 # Mac mini (M1, 2020)
- apple,j293 # MacBook Pro (13-inch, M1, 2020)
- apple,j313 # MacBook Air (M1, 2020)
- apple,j456 # iMac (24-inch, 4x USB-C, M1, 2021)
- apple,j457 # iMac (24-inch, 2x USB-C, M1, 2021)
- const: apple,t8103
- const: apple,arm-platform
- description: Apple M1 Pro SoC based platforms
items:
- enum:
- apple,j314s # MacBook Pro (14-inch, M1 Pro, 2021)
- apple,j316s # MacBook Pro (16-inch, M1 Pro, 2021)
- const: apple,t6000
- const: apple,arm-platform
- description: Apple M1 Max SoC based platforms
items:
- enum:
- apple,j314c # MacBook Pro (14-inch, M1 Max, 2021)
- apple,j316c # MacBook Pro (16-inch, M1 Max, 2021)
- const: apple,t6001
- const: apple,arm-platform

additionalProperties: true

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134 changes: 134 additions & 0 deletions sys/contrib/device-tree/Bindings/arm/apple/apple,pmgr.yaml
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@@ -0,0 +1,134 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apple/apple,pmgr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple SoC Power Manager (PMGR)

maintainers:
- Hector Martin <marcan@marcan.st>

description: |
Apple SoCs include PMGR blocks responsible for power management,
which can control various clocks, resets, power states, and
performance features. This node represents the PMGR as a syscon,
with sub-nodes representing individual features.
properties:
$nodename:
pattern: "^power-management@[0-9a-f]+$"

compatible:
items:
- enum:
- apple,t8103-pmgr
- apple,t6000-pmgr
- const: apple,pmgr
- const: syscon
- const: simple-mfd

reg:
maxItems: 1

"#address-cells":
const: 1

"#size-cells":
const: 1

patternProperties:
"power-controller@[0-9a-f]+$":
description:
The individual power management domains within this controller
type: object
$ref: /power/apple,pmgr-pwrstate.yaml#

required:
- compatible
- reg

additionalProperties: false

examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
power-management@23b700000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3b700000 0x0 0x14000>;
ps_sio: power-controller@1c0 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x1c0 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "sio";
apple,always-on;
};
ps_uart_p: power-controller@220 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x220 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart_p";
power-domains = <&ps_sio>;
};
ps_uart0: power-controller@270 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x270 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "uart0";
power-domains = <&ps_uart_p>;
};
};
power-management@23d280000 {
compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x2 0x3d280000 0x0 0xc000>;
ps_aop_filter: power-controller@4000 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4000 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_filter";
};
ps_aop_base: power-controller@4010 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4010 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_base";
power-domains = <&ps_aop_filter>;
};
ps_aop_shim: power-controller@4038 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4038 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_shim";
power-domains = <&ps_aop_base>;
};
ps_aop_uart0: power-controller@4048 {
compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
reg = <0x4048 8>;
#power-domain-cells = <0>;
#reset-cells = <0>;
label = "aop_uart0";
power-domains = <&ps_aop_shim>;
};
};
};
10 changes: 0 additions & 10 deletions sys/contrib/device-tree/Bindings/arm/arm,cci-400.yaml
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Expand Up @@ -166,16 +166,6 @@ examples:
};
};
dma0: dma@3000000 {
/* compatible = "arm,pl330", "arm,primecell"; */
cci-control-port = <&cci_control0>;
reg = <0x0 0x3000000 0x0 0x1000>;
interrupts = <10>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
cci@2c090000 {
compatible = "arm,cci-400";
#address-cells = <1>;
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37 changes: 37 additions & 0 deletions sys/contrib/device-tree/Bindings/arm/aspeed/aspeed,sbc.yaml
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@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
# Copyright 2021 Joel Stanley, IBM Corp.
%YAML 1.2
---
$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: ASPEED Secure Boot Controller

maintainers:
- Joel Stanley <joel@jms.id.au>
- Andrew Jeffery <andrew@aj.id.au>

description: |
The ASPEED SoCs have a register bank for interacting with the secure boot
controller.
properties:
compatible:
items:
- const: aspeed,ast2600-sbc

reg:
maxItems: 1

required:
- compatible
- reg

additionalProperties: false

examples:
- |
sbc: secure-boot-controller@1e6f2000 {
compatible = "aspeed,ast2600-sbc";
reg = <0x1e6f2000 0x1000>;
};
3 changes: 2 additions & 1 deletion sys/contrib/device-tree/Bindings/arm/atmel-at91.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,8 @@ title: Atmel AT91 device tree bindings.

maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
- Ludovic Desroches <ludovic.desroches@microchip.com>
- Claudiu Beznea <claudiu.beznea@microchip.com>
- Nicolas Ferre <nicolas.ferre@microchip.com>

description: |
Boards with a SoC of the Atmel AT91 or SMART family shall have the following
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1 change: 1 addition & 0 deletions sys/contrib/device-tree/Bindings/arm/bcm/brcm,bcm4908.yaml
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Expand Up @@ -29,6 +29,7 @@ properties:
items:
- enum:
- asus,gt-ac5300
- netgear,raxe500
- const: brcm,bcm4908

- description: BCM49408 based boards
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8 changes: 8 additions & 0 deletions sys/contrib/device-tree/Bindings/arm/cpus.yaml
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Expand Up @@ -137,6 +137,9 @@ properties:
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
Expand All @@ -145,8 +148,12 @@ properties:
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
- arm,cortex-x2
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
- arm,neoverse-v1
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
Expand Down Expand Up @@ -174,6 +181,7 @@ properties:
- qcom,kryo560
- qcom,kryo570
- qcom,kryo685
- qcom,kryo780
- qcom,scorpion

enable-method:
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,12 @@ properties:
compatible:
const: linaro,optee-tz

interrupts:
maxItems: 1
description: |
This interrupt which is used to signal an event by the secure world
software is expected to be edge-triggered.
method:
enum: [smc, hvc]
description: |
Expand All @@ -42,10 +48,12 @@ additionalProperties: false

examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
};
};
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ Required properties:
- compatible: Should contain a chip-specific compatible string,
Chip-specific strings are of the form "fsl,<chip>-dcfg",
The following <chip>s are known to be supported:
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a

- reg : should contain base address and length of DCFG memory-mapped registers

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