Fix typos - remove duplicate "the".

PR:	bin/154928
Submitted by:	Eitan Adler <lists at eitanadler.com>
MFC after: 	3 days

bin/df/df.c

@@ -125,7 +125,7 @@ main(int argc, char *argv[])
 				/* FALLTHROUGH */
 		case 'P':
 			/*
-			 * POSIX specifically discusses the the behavior of
+			 * POSIX specifically discusses the behavior of
 			 * both -k and -P. It states that the blocksize should
 			 * be set to 1024. Thus, if this occurs, simply break
 			 * rather than clobbering the old blocksize.

bin/sh/expand.c

@@ -959,7 +959,7 @@ varvalue(char *name, int quoted, int subtype, int flag)
 
 
 /*
- * Record the the fact that we have to scan this region of the
+ * Record the fact that we have to scan this region of the
  * string for IFS characters.
  */
 

lib/libc/arm/gen/modf.c

@@ -86,7 +86,7 @@ modf(val, iptr)
 	 * If you look at the math involved for a few seconds, it's
 	 * plain to see that the integral part is the input, with the
 	 * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed,
-	 * the the fractional part is the part with the rest of the
+	 * the fractional part is the part with the rest of the
 	 * bits zeroed.  Just zeroing the high bits to get the
 	 * fractional part would yield a fraction in need of
 	 * normalization.  Therefore, we take the easy way out, and

lib/libc/ia64/gen/modf.c

@@ -85,7 +85,7 @@ modf(val, iptr)
 	 * If you look at the math involved for a few seconds, it's
 	 * plain to see that the integral part is the input, with the
 	 * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed,
-	 * the the fractional part is the part with the rest of the
+	 * the fractional part is the part with the rest of the
 	 * bits zeroed.  Just zeroing the high bits to get the
 	 * fractional part would yield a fraction in need of
 	 * normalization.  Therefore, we take the easy way out, and

lib/libc/mips/gen/modf.c

@@ -86,7 +86,7 @@ modf(val, iptr)
 	 * If you look at the math involved for a few seconds, it's
 	 * plain to see that the integral part is the input, with the
 	 * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed,
-	 * the the fractional part is the part with the rest of the
+	 * the fractional part is the part with the rest of the
 	 * bits zeroed.  Just zeroing the high bits to get the
 	 * fractional part would yield a fraction in need of
 	 * normalization.  Therefore, we take the easy way out, and

lib/libc/powerpc/gen/modf.c

@@ -86,7 +86,7 @@ modf(val, iptr)
 	 * If you look at the math involved for a few seconds, it's
 	 * plain to see that the integral part is the input, with the
 	 * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed,
-	 * the the fractional part is the part with the rest of the
+	 * the fractional part is the part with the rest of the
 	 * bits zeroed.  Just zeroing the high bits to get the
 	 * fractional part would yield a fraction in need of
 	 * normalization.  Therefore, we take the easy way out, and

lib/libc/powerpc64/gen/modf.c

@@ -86,7 +86,7 @@ modf(val, iptr)
 	 * If you look at the math involved for a few seconds, it's
 	 * plain to see that the integral part is the input, with the
 	 * low (DBL_FRACBITS - (exponent - DBL_EXP_BIAS)) bits zeroed,
-	 * the the fractional part is the part with the rest of the
+	 * the fractional part is the part with the rest of the
 	 * bits zeroed.  Just zeroing the high bits to get the
 	 * fractional part would yield a fraction in need of
 	 * normalization.  Therefore, we take the easy way out, and

lib/libpkg/version.c

@@ -76,7 +76,7 @@ split_version(const char *pkgname, const char **endname, unsigned long *epoch, u
     if (pkgname == NULL)
 	errx(2, "%s: Passed NULL pkgname.", __func__);
 
-    /* Look for the last '-' the the pkgname */
+    /* Look for the last '-' the pkgname */
     ch = strrchr(pkgname, '-');
     /* Cheat if we are just passed a version, not a valid package name */
     versionstr = ch ? ch + 1 : pkgname;

lib/libstand/environment.c

@@ -59,7 +59,7 @@ env_getenv(const char *name)
  * Some notes:
  *
  * If the EV_VOLATILE flag is set, a copy of the variable is made.
- * If EV_DYNAMIC is set, the the variable has been allocated with
+ * If EV_DYNAMIC is set, the variable has been allocated with
  * malloc and ownership transferred to the environment.
  * If (value) is NULL, the variable is set but has no value.
  */

lib/msun/src/s_cbrt.c

@@ -94,7 +94,7 @@ cbrt(double x)
      * 2 23-bit ulps larger).  With rounding towards zero, the error bound
      * would be ~5/6 instead of ~4/6.  With a maximum error of 2 23-bit ulps
      * in the rounded t, the infinite-precision error in the Newton
-     * approximation barely affects third digit in the the final error
+     * approximation barely affects third digit in the final error
      * 0.667; the error in the rounded t can be up to about 3 23-bit ulps
      * before the final error is larger than 0.667 ulps.
      */

sys/amd64/amd64/trap.c

@@ -235,7 +235,7 @@ trap(struct trapframe *frame)
 	 * A trap can occur while DTrace executes a probe. Before
 	 * executing the probe, DTrace blocks re-scheduling and sets
 	 * a flag in it's per-cpu flags to indicate that it doesn't
-	 * want to fault. On returning from the the probe, the no-fault
+	 * want to fault. On returning from the probe, the no-fault
 	 * flag is cleared and finally re-scheduling is enabled.
 	 *
 	 * If the DTrace kernel module has registered a trap handler,

sys/arm/xscale/i80321/iq80321.c

@@ -139,7 +139,7 @@ iq80321_attach(device_t dev)
 		    device_get_name(dev));
 
 	/*
-	 * We have mapped the the PCI I/O windows in the early
+	 * We have mapped the PCI I/O windows in the early
 	 * bootstrap phase.
 	 */
 	sc->sc_iow_vaddr = IQ80321_IOW_VBASE;

sys/boot/ficl/words.c

@@ -1293,7 +1293,7 @@ static void ifCoIm(FICL_VM *pVM)
 ** compiles an "else"...
 ** 1) Compile a branch and a patch address; the address gets patched
 **    by "endif" to point past the "else" code.
-** 2) Pop the the "if" patch address
+** 2) Pop the "if" patch address
 ** 3) Patch the "if" branch to point to the current compile address.
 ** 4) Push the "else" patch address. ("endif" patches this to jump past 
 **    the "else" code.

sys/cam/cam_xpt.c

@@ -317,7 +317,7 @@ xpt_schedule_dev_allocq(struct cam_eb *bus, struct cam_ed *dev)
 		CAMQ_GET_PRIO(&dev->drvq))) == 0)) {
 		/*
 		 * The priority of a device waiting for CCB resources
-		 * is that of the the highest priority peripheral driver
+		 * is that of the highest priority peripheral driver
 		 * enqueued.
 		 */
 		retval = xpt_schedule_dev(&bus->sim->devq->alloc_queue,
@@ -340,7 +340,7 @@ xpt_schedule_dev_sendq(struct cam_eb *bus, struct cam_ed *dev)
 	    (cam_ccbq_frozen_top(&dev->ccbq) == 0)) {
 		/*
 		 * The priority of a device waiting for controller
-		 * resources is that of the the highest priority CCB
+		 * resources is that of the highest priority CCB
 		 * enqueued.
 		 */
 		retval =

sys/cam/scsi/scsi_sa.c

@@ -2654,7 +2654,7 @@ sagetparams(struct cam_periph *periph, sa_params params_to_get,
 			struct scsi_dev_conf_page *cp = &ntcs->dconf;
 			/*
 			 * We don't really know whether this device supports
-			 * Data Compression if the the algorithm field is
+			 * Data Compression if the algorithm field is
 			 * zero. Just say we do.
 			 */
 			*comp_supported = TRUE;

sys/cddl/dev/dtrace/amd64/dtrace_subr.c

@@ -487,7 +487,7 @@ dtrace_trap(struct trapframe *frame, u_int type)
 	 * A trap can occur while DTrace executes a probe. Before
 	 * executing the probe, DTrace blocks re-scheduling and sets
 	 * a flag in it's per-cpu flags to indicate that it doesn't
-	 * want to fault. On returning from the the probe, the no-fault
+	 * want to fault. On returning from the probe, the no-fault
 	 * flag is cleared and finally re-scheduling is enabled.
 	 *
 	 * Check if DTrace has enabled 'no-fault' mode:

sys/cddl/dev/dtrace/i386/dtrace_subr.c

@@ -487,7 +487,7 @@ dtrace_trap(struct trapframe *frame, u_int type)
 	 * A trap can occur while DTrace executes a probe. Before
 	 * executing the probe, DTrace blocks re-scheduling and sets
 	 * a flag in it's per-cpu flags to indicate that it doesn't
-	 * want to fault. On returning from the the probe, the no-fault
+	 * want to fault. On returning from the probe, the no-fault
 	 * flag is cleared and finally re-scheduling is enabled.
 	 *
 	 * Check if DTrace has enabled 'no-fault' mode:

sys/compat/ndis/subr_ntoskrnl.c

@@ -3355,7 +3355,7 @@ KeSetEvent(nt_kevent *kevent, uint32_t increment, uint8_t kwait)
 		 * setting the state to signalled since we're supposed
 		 * to automatically clear synchronization events anyway).
 		 *
-		 * If it's a notification event, or the the first
+		 * If it's a notification event, or the first
 		 * waiter is doing a WAITTYPE_ALL wait, go through
 		 * the full wait satisfaction process.
 		 */

sys/dev/advansys/adwcam.c

@@ -1,5 +1,5 @@
 /*-
- * CAM SCSI interface for the the Advanced Systems Inc.
+ * CAM SCSI interface for the Advanced Systems Inc.
  * Second Generation SCSI controllers.
  *
  * Product specific probe and attach routines can be found in:

sys/dev/aic7xxx/aic79xx_osm.h

@@ -103,7 +103,7 @@
  * The number of dma segments supported.  The sequencer can handle any number
  * of physically contiguous S/G entrys.  To reduce the driver's memory
  * consumption, we limit the number supported to be sufficient to handle
- * the largest mapping supported by the the legacy kernel MAXPHYS setting of
+ * the largest mapping supported by the legacy kernel MAXPHYS setting of
  * 128K.  This can be increased once some testing is done.  Assuming the
  * transfer is as fragmented as possible and unaligned, this turns out to
  * be the number of paged sized transfers in MAXPHYS plus an extra element

sys/dev/aic7xxx/aic7xxx_osm.h

@@ -115,7 +115,7 @@ extern devclass_t ahc_devclass;
  * The number of dma segments supported.  The sequencer can handle any number
  * of physically contiguous S/G entrys.  To reduce the driver's memory
  * consumption, we limit the number supported to be sufficient to handle
- * the largest mapping supported by the the legacy kernel MAXPHYS setting of
+ * the largest mapping supported by the legacy kernel MAXPHYS setting of
  * 128K.  This can be increased once some testing is done.  Assuming the
  * be the number of paged sized transfers in MAXPHYS plus an extra element
  * to handle any unaligned residual.  The sequencer fetches SG elements

sys/dev/asr/i2omsg.h

@@ -183,7 +183,7 @@ PRAGMA_PACK_PUSH
 #define	   I2O_VERSION_OFFSET_SGL_TRL_OFFSET_MASK      0xF0
 
 /*   Defines for the Message Flags Field. */
-/*   Please Note the the FAIL bit is only set in the Transport Fail Message. */
+/*   Please Note the FAIL bit is only set in the Transport Fail Message. */
 #define	   I2O_MESSAGE_FLAGS_STATIC		       0x01
 #define	   I2O_MESSAGE_FLAGS_64BIT_CONTEXT	       0x02
 #define	   I2O_MESSAGE_FLAGS_MULTIPLE		       0x10

sys/dev/bktr/bktr_card.c

@@ -570,7 +570,7 @@ static int locate_eeprom_address( bktr_ptr_t bktr) {
  *
  * However some makes of card (eg Hauppauge) come with a configuration eeprom
  * which tells us the make of the card. Most eeproms also tell us the
- * tuner type and other features of the the cards.
+ * tuner type and other features of the cards.
  *
  * The current probe code works as follows
  * A) If the card uses a Bt878/879:

sys/dev/ctau/ctau.c

@@ -1734,7 +1734,7 @@ ct_board_opt_t ct_board_opt_dflt = {
 	0,			/* board control register 2 */
 	{			/* DMA priority control register */
 		PCR_PRIO_ROTATE,
-		0,		/* all channels share the the bus hold */
+		0,		/* all channels share the bus hold */
 		0,		/* hold the bus until all transfers done */
 	},
 	CFG_A,			/* E1/G.703 config: two independent channels */

sys/dev/ctau/ctddk.h

@@ -206,7 +206,7 @@ typedef struct {
 typedef struct {
 	unsigned prio : 3;	/* priority of channels */
 	unsigned noshare : 1;	/* 1 - chan holds the bus until end of data */
-				/* 0 - all channels share the the bus hold */
+				/* 0 - all channels share the bus hold */
 	unsigned release : 1;	/* 1 - release the bus between transfers */
 				/* 0 - hold the bus until all transfers done */
 } ct_pcr_t;

sys/dev/cxgb/cxgb_main.c

@@ -1908,7 +1908,7 @@ cxgb_uninit_synchronized(struct port_info *pi)
 	/*
 	 * Clear this port's bit from the open device map, and then drain all
 	 * the tasks that can access/manipulate this port's port_info or ifp.
-	 * We disable this port's interrupts here and so the the slow/ext
+	 * We disable this port's interrupts here and so the slow/ext
 	 * interrupt tasks won't be enqueued.  The tick task will continue to
 	 * be enqueued every second but the runs after this drain will not see
 	 * this port in the open device map.
@@ -2858,7 +2858,7 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
 		u64 buf[32];
 
 		/*
-		 * Use these to avoid modifying len/addr in the the return
+		 * Use these to avoid modifying len/addr in the return
 		 * struct
 		 */
 		uint32_t len = t->len, addr = t->addr;

sys/dev/drm/mach64_dma.c

@@ -173,7 +173,7 @@ static int mach64_ring_idle(drm_mach64_private_t *dev_priv)
 }
 
 /**
- * Reset the the ring buffer descriptors.
+ * Reset the ring buffer descriptors.
  *
  * \sa mach64_do_engine_reset()
  */

sys/dev/drm/r300_reg.h

@@ -353,7 +353,7 @@ __FBSDID("$FreeBSD$");
 #       define R300_PVS_CNTL_1_PROGRAM_START_SHIFT   0
 #       define R300_PVS_CNTL_1_POS_END_SHIFT         10
 #       define R300_PVS_CNTL_1_PROGRAM_END_SHIFT     20
-/* Addresses are relative the the vertex program parameters area. */
+/* Addresses are relative the vertex program parameters area. */
 #define R300_VAP_PVS_CNTL_2                 0x22D4
 #       define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
 #       define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT  16

sys/dev/e1000/e1000_82575.c

@@ -1986,7 +1986,7 @@ static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
  *  e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
  *  @hw: pointer to the HW structure
  *
- *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
+ *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
  *  the values found in the EEPROM.  This addresses an issue in which these
  *  bits are not restored from EEPROM after reset.
  **/

sys/dev/e1000/e1000_ich8lan.c

@@ -3218,7 +3218,7 @@ static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
  *  @hw: pointer to the HW structure
  *
  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
- *  register, so the the bus width is hard coded.
+ *  register, so the bus width is hard coded.
  **/
 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
 {

sys/dev/ep/if_epreg.h

@@ -113,7 +113,7 @@
 /**************************************************************************
  *									  *
  * These are the registers for the 3Com 3c509 and their bit patterns when *
- * applicable.  They have been taken out the the "EtherLink III Parallel  *
+ * applicable.  They have been taken out the "EtherLink III Parallel  *
  * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
  * from 3com.								  *
  *									  *

sys/dev/fdc/fdc.c

@@ -1261,7 +1261,7 @@ fdmisccmd(struct fd_data *fd, u_int cmd, void *data)
 
 	/*
 	 * Set up a bio request for fdstrategy().  bio_offset is faked
-	 * so that fdstrategy() will seek to the the requested
+	 * so that fdstrategy() will seek to the requested
 	 * cylinder, and use the desired head.
 	 */
 	bp->bio_cmd = cmd;

sys/dev/ixgb/ixgb_ee.c

@@ -325,7 +325,7 @@ ixgb_wait_eeprom_command(struct ixgb_hw *hw)
  * hw - Struct containing variables accessed by shared code
  *
  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  * valid.
  *
  * Returns:

sys/dev/malo/if_malohal.h

@@ -133,7 +133,7 @@ struct malo_hal_hwstats {
 /*
  * Set Antenna Configuration (legacy operation).
  *
- * The RX antenna can be selected using the the bitmask
+ * The RX antenna can be selected using the bitmask
  * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
  * (diversity?XXX)
  */

sys/dev/mwl/mwlhal.h

@@ -291,7 +291,7 @@ int	mwl_hal_setradio(struct mwl_hal *mh, int onoff, MWL_HAL_PREAMBLE preamble);
 /*
  * Set Antenna Configuration (legacy operation).
  *
- * The RX antenna can be selected using the the bitmask
+ * The RX antenna can be selected using the bitmask
  * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
  * (diversity?XXX)
  */

sys/dev/nxge/xgehal/xgehal-device.c

@@ -4418,7 +4418,7 @@ xge_hal_device_status(xge_hal_device_t *hldev, u64 *hw_status)
 #ifndef XGE_HAL_HERC_EMULATION
 	/*
 	 * Andrew: in PCI 33 mode, the P_PLL is not used, and therefore,
-	 * the the P_PLL_LOCK bit in the adapter_status register will
+	 * the P_PLL_LOCK bit in the adapter_status register will
 	 * not be asserted.
 	 */
 	if (!(tmp64 & XGE_HAL_ADAPTER_STATUS_P_PLL_LOCK) &&

sys/dev/nxge/xgehal/xgehal-ring-fp.c

@@ -801,7 +801,7 @@ xge_hal_ring_dtr_free(xge_hal_channel_h channelh, xge_hal_dtr_h dtrh)
  * xge_hal_ring_is_next_dtr_completed - Check if the next dtr is completed
  * @channelh: Channel handle.
  *
- * Checks if the the _next_ completed descriptor is in host memory
+ * Checks if the _next_ completed descriptor is in host memory
  *
  * Returns: XGE_HAL_OK - success.
  * XGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors

sys/dev/random/randomdev_soft.c

@@ -347,7 +347,7 @@ random_yarrow_write(void *buf, int count)
 
 	/*
 	 * Break the input up into HARVESTSIZE chunks. The writer has too
-	 * much control here, so "estimate" the the entropy as zero.
+	 * much control here, so "estimate" the entropy as zero.
 	 */
 	for (i = 0; i < count; i += HARVESTSIZE) {
 		chunk = HARVESTSIZE;

sys/dev/sound/pci/es137x.c

@@ -584,7 +584,7 @@ eschan1370_setspeed(kobj_t obj, void *data, uint32_t speed)
 		/*
 		 * DAC1 does not support continuous rate settings.
 		 * Pick the nearest and use it since FEEDER_RATE will
-		 * do the the proper conversion for us.
+		 * do the proper conversion for us.
 		 */
 		es->ctrl &= ~CTRL_WTSRSEL;
 		if (speed < 8268) {

sys/dev/sym/sym_fw1.h

@@ -262,7 +262,7 @@ static const struct SYM_FWA_SCR SYM_FWA_SCR = {
 	 *  The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 
 	 *  is a critical path. If it is partially executed, it then 
 	 *  may happen that the job address is not yet in the DSA 
-	 *  and the the next queue position points to the next JOB.
+	 *  and the next queue position points to the next JOB.
 	 */
 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
 	/*

sys/dev/sym/sym_fw2.h

@@ -252,7 +252,7 @@ static const struct SYM_FWA_SCR SYM_FWA_SCR = {
 	 *  The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS 
 	 *  is a critical path. If it is partially executed, it then 
 	 *  may happen that the job address is not yet in the DSA 
-	 *  and the the next queue position points to the next JOB.
+	 *  and the next queue position points to the next JOB.
 	 */
 	SCR_LOAD_ABS (dsa, 4),
 		PADDR_B (startpos),

sys/dev/uart/uart_dev_ns8250.c

@@ -693,7 +693,7 @@ ns8250_bus_probe(struct uart_softc *sc)
 	/*
 	 * We should have a sufficiently clean "pipe" to determine the
 	 * size of the FIFOs. We send as much characters as is reasonable
-	 * and wait for the the overflow bit in the LSR register to be
+	 * and wait for the overflow bit in the LSR register to be
 	 * asserted, counting the characters as we send them. Based on
 	 * that count we know the FIFO size.
 	 */