Do not remove ExtMods with no ports by default (#888)

chipsalliance · Sep 14, 2018 · 860e684 · 860e684
1 parent b8a2dee
commit 860e684
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Showing 2 changed files with 39 additions and 3 deletions.
diff --git a/src/main/scala/firrtl/transforms/DeadCodeElimination.scala b/src/main/scala/firrtl/transforms/DeadCodeElimination.scala
@@ -178,7 +178,8 @@ class DeadCodeElimination extends Transform {
                              deadNodes: collection.Set[LogicNode],
                              moduleMap: collection.Map[String, DefModule],
                              renames: RenameMap,
-                             topName: String)
+                             topName: String,
+                             doTouchExtMods: Set[String])
                             (mod: DefModule): Option[DefModule] = {
     // For log-level debug
     def deleteMsg(decl: IsDeclaration): String = {
@@ -257,7 +258,7 @@ class DeadCodeElimination extends Transform {
           Some(Module(info, name, portsx, bodyx))
         }
       case ext: ExtModule =>
-        if (portsx.isEmpty) {
+        if (portsx.isEmpty && doTouchExtMods.contains(ext.name)) {
           logger.debug(deleteMsg(mod))
           None
         }
@@ -308,7 +309,7 @@ class DeadCodeElimination extends Transform {
     // current status of the modulesxMap is used to either delete instances or update their types
     val modulesxMap = mutable.HashMap.empty[String, DefModule]
     topoSortedModules.foreach { case mod =>
-      deleteDeadCode(moduleDeps(mod.name), deadNodes, modulesxMap, renames, c.main)(mod) match {
+      deleteDeadCode(moduleDeps(mod.name), deadNodes, modulesxMap, renames, c.main, doTouchExtMods)(mod) match {
         case Some(m) => modulesxMap += m.name -> m
         case None => renames.delete(ModuleName(mod.name, CircuitName(c.main)))
       }

diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
@@ -8,6 +8,7 @@ import firrtl.passes._
 import firrtl.transforms._
 import firrtl.annotations._
 import firrtl.passes.memlib.SimpleTransform
+import FirrtlCheckers._
 
 import java.io.File
 import java.nio.file.Paths
@@ -320,6 +321,40 @@ class DCETests extends FirrtlFlatSpec {
         """.stripMargin
     exec(input, input)
   }
+  "extmodules with no ports" should "NOT be deleted by default" in {
+    val input =
+      """circuit Top :
+        |  extmodule BlackBox :
+        |    defname = BlackBox
+        |  module Top :
+        |    input x : UInt<1>
+        |    output y : UInt<1>
+        |    inst blackBox of BlackBox
+        |    y <= x
+        |""".stripMargin
+    exec(input, input)
+  }
+  "extmodules with no ports marked optimizable" should "be deleted" in {
+    val input =
+      """circuit Top :
+        |  extmodule BlackBox :
+        |    defname = BlackBox
+        |  module Top :
+        |    input x : UInt<1>
+        |    output y : UInt<1>
+        |    inst blackBox of BlackBox
+        |    y <= x
+        |""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<1>
+        |    output y : UInt<1>
+        |    y <= x
+        |""".stripMargin
+    val doTouchAnno = OptimizableExtModuleAnnotation(ModuleName("BlackBox", CircuitName("Top")))
+    exec(input, check, Seq(doTouchAnno))
+  }
   // bar.z is not used and thus is dead code, but foo.z is used so this code isn't eliminated
   "Module deduplication" should "should be preserved despite unused output of ONE instance" in {
     val input =