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how con a rocket chip be generated for FPGAs? #1594
i have used the chisel generator to create a rocket chip, but the top modules is called "TestHarness". additionally i found "DPI-C" stuff in the generated verilog code. this makes it look like i have created a rocket-chip for simulations only.
how can i create a rocket chip that is ready to be put on a FPGA?
thank you very much in advance!
so just using the stuff on this repository it is not possible to generate anything that can be used on actual hardware? are you telling me all that fancy chisel is not able to produce anything that is actually usable?
i have already checked the links but these makefiles/generators or whatever always fail due to being outdated.
i would love nothing more than getting verilog code that can be synthesized. why is that so hard?
No, that's incorrect. Chisel produces Verilog. You can do whatever you want with that Verilog.
You can generate Verilog from this repository that forms the basis for what you need for an FPGA or an ASIC by running
However, there are a number of other steps that you have to go through for any FPGA mapping or tape-out, like defining a periphery for your FPGA or ASIC, replacing memories with technology specific ones, etc. Those steps are handled by the repositories that I mentioned above for specific FPGAs. The referenced repositories use this repository as a submodule.
thank you very much for the response.
yes, i understand that these repositories are supposed to ease the process, but i always have problems that make me doubt the correct functionality of my result.
i created the verilog code with the command you mentioned and got among others the file: "freechips.rocketchip.system.DefaultFPGAConfig.v". i have no idea what exactly DefaultFPGAConfig means but gave me the impression that there are other configs available. i also noticed a TestHarness in the code that sounds like it does not belong on an FPGA.
let me rephrase my problem: what should i do to adapt the rocket chip for a specific board? i assume you have to work with those .scala files right? or is there an option to get the rocket chip with some AXI interfaces that i can connect to memory?
Someone else may be able to provide a better explanation... but, here goes:
The actual Rocket Chip SoC is in module
When you want to move to an FPGA the periphery has to be matched to some FPGA fabric periphery. Your FPGA fabric may speak PCIe, so you need to do a conversion from AXI to PCIe or avoid the conversion to AXI and go directly from TileLink to PCIe. This is only an example... This is where the existing "super repositories" I mentioned come in. Things like freedom, fpga-zynq, or firesim. These have predefined configurations for specific FPGAs: Arty, ZC707, Zedboard, ZC706, Amazon AWS ec2 f1 (small and large) for specific versions of Rocket Chip. All those repositories are encapsulated and self-starting. I only have experience with fpga-zynq due to the FPGAs I have access to, but that's literally: "type
Alternatively, you can take the
You need to define a shell that converts
This is up to you. You can follow along with how fpga-shells works or go your own way with it. You can use the Verilog directly and write a VHDL wrapper for your FPGA. Entirely up to you, your workflow, etc.
Take a look at the
The best guidance on this is to either align with the Freedom repositories that target Arty and ZC707 boards or to use Firesim and migrate to an AWS worflow. Alternatively, you can write your own FPGA shell for whatever board you want to use and build up your own infrastructure and workflow. Fpga-zynq is deprecated, but should be fine if you use it's exact submodules and rebuild everything. Deviating from that will, likely, require modifications on your end (e.g., if you try to use rocket-chip master inside fpga-zynq master).