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Commits on Apr 3, 2018
  1. nir+drivers: add helpers to get # of src/dest components

    robclark committed Mar 28, 2018
    Add helpers to get the number of src/dest components for an intrinsic,
    and update spots that were open-coding this logic to use the helpers
    instead.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
    Reviewed-by: Eric Anholt <eric@anholt.net>
  2. freedreno/ir3: fix fallout of unused false-depth elimination

    robclark committed Apr 2, 2018
    Since we were MARK flag for both preventing loops, and tracking whether
    instructions were used, we could end up in an infinite loop due to
    bd2ca2b.  Instead invert the logic.. mark all instructions UNUSED
    up front and clear the flag as we visit them.
    
    Fixes: bd2ca2b freedreno/ir3: eliminate unused false-deps
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  3. gallium/pipebuffer: fix parenthesis location

    Timothy Arceri
    Timothy Arceri committed Mar 31, 2018
    Without this the return value will never get set to -1. This
    was first added in 49866c8 and copied in 2b396ee.
    
    Fixes: 2b396ee "gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager"
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342
  4. Revert "mesa: add GL_HALF_FLOAT as supported type to readpixels"

    tpalli committed Apr 3, 2018
    This reverts commit 41cf30b.
    
    Commit caused regressions with KHR-GLES3.packed_pixels.* tests.
    
    Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
    Suggested-by: Eric Anholt <eric@anholt.net>
Commits on Apr 2, 2018
  1. gallivm: Fix include for LLVMAddPromoteMemoryToRegisterPass

    FireBurn authored and Marek Olšák committed Apr 1, 2018
    Include llvm-c/Transforms/Utils.h with the newest LLVM 7
    
    Signed-of-by: Mike Lothian <mike@fireburn.co.uk>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
    Signed-off-by: Marek Olšák <marek.olsak@amd.com>
  2. radeonsi: Fix include for LLVMAddPromoteMemoryToRegisterPass

    FireBurn authored and Marek Olšák committed Apr 1, 2018
    Include llvm-c/Transforms/Utils.h with the newest LLVM 7
    
    Signed-of-by: Mike Lothian <mike@fireburn.co.uk>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
    Signed-off-by: Marek Olšák <marek.olsak@amd.com>
  3. ac/nir: Fix include for LLVMAddPromoteMemoryToRegisterPass

    FireBurn authored and Marek Olšák committed Apr 1, 2018
    Include llvm-c/Transforms/Utils.h with the newest LLVM 7
    
    Signed-of-by: Mike Lothian <mike@fireburn.co.uk>
    Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
    Signed-off-by: Marek Olšák <marek.olsak@amd.com>
  4. st/dri: Initialise modifier to INVALID for DRI2

    fooishbar committed Apr 2, 2018
    When allocating a buffer for DRI2, set the modifier to INVALID to inform
    the backend that we have no supplied modifiers and it should do its own
    thing. The missed initialisation forced linear, even if the
    implementation had made other decisions.
    
    This resulted in VC4 DRI2 clients failing with:
      Modifier 0x0 vs. tiling (0x700000000000001) mismatch
    
    Signed-off-by: Daniel Stone <daniels@collabora.com>
    Reported-by: Andreas Müller <schnitzeltony@gmail.com>
    Reviewed-by: Eric Anholt <eric@anholt.net>
    Fixes: 3f85131 ("gallium/winsys/drm: introduce modifier field to winsys_handle")
  5. radeonsi: implement GL_KHR_blend_equation_advanced

    Marek Olšák
    Marek Olšák committed Jan 7, 2018
    MSAA is supported using sample shading. Layered rendering and all texture
    targets are also supported.
    
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  6. radeonsi: rename unpack_param -> si_unpack_param

    Marek Olšák
    Marek Olšák committed Mar 23, 2018
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  7. radeonsi: move FMASK shader logic to shared code

    Marek Olšák
    Marek Olšák committed Mar 20, 2018
    We'll need it for FBFETCH in both TGSI and NIR paths.
    
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  8. radeonsi: add R600_DEBUG=nofmask to disable MSAA compression

    Marek Olšák
    Marek Olšák committed Mar 20, 2018
    For testing.
    
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  9. gallium/u_tests: test FBFETCH and shader-based blending with MSAA

    Marek Olšák
    Marek Olšák committed Mar 20, 2018
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  10. ac/gpu_info: print GB_ADDR_CONFIG

    Marek Olšák
    Marek Olšák committed Mar 22, 2018
  11. ac/gpu_info: reorder the fields and print them nicely

    Marek Olšák
    Marek Olšák committed Mar 19, 2018
  12. ac/gpu_info: don't print irrelevant fields

    Marek Olšák
    Marek Olšák committed Mar 19, 2018
  13. st/mesa: don't draw if the bound element array buffer is not allocated

    Marek Olšák
    Marek Olšák committed Mar 19, 2018
    Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
  14. anv/cmd_buffer: honor pending clear views for depth/stencil attachments

    itoral committed Feb 28, 2018
    v2: rebased on top of subpass rework.
    
    v3: rebased
    
    v4:
     - rebased
     - reset pending clear views in one go rather one bit at a time (Caio)
    
    Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  15. anv/cmd_buffer: consider multiview masks for tracking pending clear a…

    itoral committed Feb 21, 2018
    …spects
    
    When multiview is active a subpass clear may only clear a subset of the
    attachment layers. Other subpasses in the same render pass may also
    clear too and we want to honor those clears as well, however, we need to
    ensure that we only clear a layer once, on the first subpass that uses
    a particular layer (view) of a given attachment.
    
    This means that when we check if a subpass attachment needs to be cleared
    we need to check if all the layers used by that subpass (as indicated by
    its view_mask) have already been cleared in previous subpasses or not, in
    which case, we must clear any pending layers used by the subpass, and only
    those pending.
    
    v2:
      - track pending clear views in the attachment state (Jason)
      - rebased on top of fast-clear rework.
    
    v3:
      - rebased on top of subpass rework.
    
    v4: rebased.
    
    v5 (Caio):
     - Rebased.
     - Initialize pending clear views to only have bits set for layers
       that exist.
     - Reset pending clear views in one go rather one bit at a time.
     - Put "last subpass for this attachment" condition in a separate
       function to simplify the conditional that resets pending_clear_aspects.
    
    Fixes:
    dEQP-VK.multiview.readback_implicit_clear.*
    
    Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
  16. radeonsi/nir: fix explicit component packing for geom/tess doubles

    Timothy Arceri
    Timothy Arceri committed Mar 21, 2018
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  17. radeonsi/nir: gather buffers declared more accurately and use const f…

    Timothy Arceri
    Timothy Arceri committed Mar 26, 2018
    …ast path
    
    For now we skip SI && HAVE_LLVM < 0x0600 for simplicity. We also skip
    setting the more accurate masks for builtin uniforms for now as it
    causes some piglit regressions.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  18. radeonsi: create load_const_buffer_desc_fast_path() helper

    Timothy Arceri
    Timothy Arceri committed Mar 26, 2018
    This will be shared by the TGSI and NIR backends. For simplicity
    we leave the SI LLVM 5.0 and lower work around only in the TGSI
    backend.
    
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  19. radeonsi/nir: set TGSI_PROPERTY_NEXT_SHADER

    Timothy Arceri
    Timothy Arceri committed Feb 26, 2018
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
  20. st/glsl_to_nir: gather next_stage in shader_info

    Timothy Arceri
    Timothy Arceri committed Feb 26, 2018
    Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Commits on Apr 1, 2018
  1. freedreno/a5xx: don't align height for PIPE_BUFFER

    robclark committed Apr 1, 2018
    Buffers can be large, so we probably don't want to make them all 32x
    bigger.  But they can't be rendered to (at least in GL) so we don't
    need this workaround to prevent page faults on mem<->gmem.
    
    Cc: "18.0" <mesa-stable@lists.freedesktop.org>
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  2. freedreno/a5xx: fix page faults on last level

    robclark committed Apr 1, 2018
    We could alternatively fall back to using "old style" draw's for
    mem<->gmem (ie. what <= a4xx do) when height is not aligned to 32,
    but that is somewhat more work (and not really something that could
    be applied to stable)
    
    Cc: "18.0" <mesa-stable@lists.freedesktop.org>
    Signed-off-by: Rob Clark <robdclark@gmail.com>
Commits on Mar 31, 2018
  1. freedreno/ir3: fix issue w/ glamor composite shaders

    robclark committed Mar 31, 2018
    Fixes an issue that became possible when we started lowering phi webs to
    regs (a7ea2b4) (although was not really seen until we also switched to
    using peephole select pass (ec8bc54) instead of lowering *all* if/else
    to select).
    
    If texture coord (or anything else that uses create_collect() to collect
    scalar values in a sequence of scalar registers) was consuming a value
    produced on either side of an if/else (ie. a phi lowered to nir reg,
    which in ir3 is an "array" of length 1) then register allocation would
    happen incorrectly and we'd end up sampling from garbage coordinates.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  2. freedreno/ir3: more half-precision fixes

    robclark committed Mar 31, 2018
    Some instructions require src/dst to be in full or half precision
    register depending on src/dst type.  So do a better job of propagating
    register type.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  3. freedreno/ir3: add helper to create immed of specified size

    robclark committed Mar 31, 2018
    We'll also need to be able to create a half-precision immediate.  So
    re-work create_immed().  Prep work for following patch.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  4. freedreno/ir3: pass ctx instead of block to create_collect()

    robclark committed Mar 31, 2018
    Prep work for following patch.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  5. freedreno/ir3: eliminate unused false-deps

    robclark committed Mar 6, 2018
    Previously false-dependencies would get flagged as used, even if the
    only "use" was a false dep to (for example) prevent a load from being
    scheduled after a store.
    
    In addition to being pointless instructions, in some cases they can
    cause problems.  For example, ldg (and similar instructions) depend on
    an immed arg getting CP'd into the instruction, but this doesn't happen
    if an instruction is otherwise unused.  Which can result in undefined
    results (overwriting unintended registers).
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  6. freedreno/ir3: add local_group_size

    robclark committed Mar 6, 2018
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  7. freedreno/ir3: clear SSA flag when assigning "ARRAY" regs too

    robclark committed Mar 31, 2018
    Avoids a misleading "INVALID FLAGS" warning in debug builds.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>
  8. freedreno/ir3: print array live ranges

    robclark committed Mar 31, 2018
    This is also useful to see if optmsgs are enabled.
    
    Signed-off-by: Rob Clark <robdclark@gmail.com>