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scc.c
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/*
* This file belongs to FreeMiNT. It's not in the original MiNT 1.12
* distribution. See the file CHANGES for a detailed log of changes.
*
*
* Copyright 1999, 2000, 2001 Frank Naumann <fnaumann@freemint.de>
* All rights reserved.
*
* This file is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
*
* Author: Frank Naumann <fnaumann@freemint.de>
* Started: 1999-09-14
*
* Please send suggestions, patches or bug reports to me or
* the MiNT mailing list.
*
*
* changes since last version:
*
* 2001-03-05: (v0.27)
*
* - new: on LAN port RTS is mapped to DTR line;
* the xdd behaves like HSMODEM now
*
* 2001-01-16: (v0.26)
*
* - fix: bugfix in the file locking code, lockpid was reset to wrong value
*
* 2000-06-12: (v0.25)
*
* - new: exact delay routine for SCC register access delay
*
* 2000-06-06: (v0.24)
*
* - fix: tt_scca baudtable had a typo for 115200 setting; also
* removed falcon_scca table as it's the same as the tt_scca
*
* 2000-05-24: (v0.23)
*
* - new: hopefully better behaviour on last close()
* (flush buffers, go back to carrier detection & update TS_BLIND)
*
* 2000-05-16: (v0.22)
*
* - fix: removed unnecessary debug messages that are printed
*
* 2000-05-14: (v0.21)
*
* - fix: corrected TS_BLIND <-> clocal handling; now hopefully correct
* - new: bios emulation doesn't poll now, use sleep/wake mechanism
* like the read/write functions
*
* 2000-05-12: (v0.20)
*
* - new: reworked the complete high level I/O routines;
* support now (hopefully) true tty functionality
* this include carrier handling, vmin/vtime handling,
* clocal settings and so on
* - new: seperate read/write routines for HSMODEM devices;
* they never block
* - fix: scc_close doesn't removed device locks
*
* 2000-05-05: (v0.16)
*
* - fix: every SCC register write access is now delayed a fixed time
*
* 2000-05-04: (v0.15)
*
* - fix: write register access with delay to verify SCC register integrity
*
* 2000-01-32: (v0.14)
*
* - new: added CD loss detection -> SIGHUP
*
* 2000-01-32: (v0.13)
*
* - new: changed naming scheme; now hopefully more logical
* - fix: corrected BIOS device numbers that are overlayed
*
* 2000-01-24: (v0.12)
*
* - new: added LAN port handling
* - fix: changed SCC base address from 0x00ff8c80 to 0xffff8c80
*
* 2000-01-20: (v0.11)
*
* - fix: bug in SCC register declaration; missing dummy chars
*
* 2000-01-19: (v0.10)
*
* - inital revision
*
*
* known bugs:
*
*
* todo:
*
*
*/
# include "mint/mint.h"
# include "arch/timer.h"
# include "libkern/libkern.h"
# include "mint/arch/delay.h"
# include "mint/asm.h"
# include "mint/dcntl.h"
# include "mint/file.h"
# include "mint/ioctl.h"
# include "mint/proc.h"
# include "mint/signal.h"
# include "mint/ssystem.h"
# include "mint/stat.h"
# include "cookie.h"
# include <mint/osbind.h>
# include "scc.h"
/*
* version
*/
# define VER_MAJOR 0
# define VER_MINOR 27
# define VER_STATUS
/*
* debugging stuff
*/
# if 0
# define DEV_DEBUG 1
# endif
# if 0
# define INT_DEBUG 1
# endif
/*
* default settings
*/
# define RSVF_SCCA_1 "serial2"
# define RSVF_SCCA_2 "lan"
# define RSVF_SCCB "modem2"
# define TTY_BASENAME "ttyS"
# define BDEV_START 6
# define BDEV_OFFSET 7
/*
* size of each buffer, compile time option,
* allocated through kmalloc on initialization time
*
* default to 12 bit = 4kb => 8kb per line (one page)
* maximum is 15 (limited range of ushort data types)
*/
# define IOBUFBITS 12 /* 4096 */
# define IOBUFSIZE (1UL << IOBUFBITS)
# define IOBUFMASK (IOBUFSIZE - 1)
# if 1
/* don't return EWOULDBLOCK as nobody support it at the moment
*/
# undef EWOULDBLOCK
# define EWOULDBLOCK 0
# endif
/*
* messages
*/
# define MSG_VERSION str (VER_MAJOR) "." str (VER_MINOR) str (VER_STATUS)
# define MSG_BUILDDATE __DATE__
# define MSG_BOOT \
"\033p SCC serial driver version " MSG_VERSION " \033q\r\n"
# define MSG_GREET \
"\275 1998, 1999 by Rainer Mannigel.\r\n" \
"\275 2000-2010 by Frank Naumann.\r\n\r\n"
# define MSG_MINT \
"\033pMiNT too old!\033q\r\n"
# define MSG_MACHINE \
"\033pThis driver requires a MegaSTE/TT/Falcon/Hades!\033q\r\n"
# define MSG_FAILURE \
"\7\r\nSorry, driver NOT installed - initialization failed!\r\n\r\n"
/****************************************************************************/
/* BEGIN kernel interface */
struct kerinfo *kernel;
/* END kernel interface */
/****************************************************************************/
/****************************************************************************/
/* BEGIN definition part */
typedef struct bauds BAUDS;
struct bauds
{
ulong baudrate;
ushort timeconst;
uchar clockdivisor;
uchar clockmode;
uchar brgenmode;
};
typedef struct iorec IOREC;
struct iorec
{
uchar *buffer; /* the buffer itself */
volatile ushort head; /* next data byte */
volatile ushort tail; /* next free byte */
ushort low_water; /* xon mark */
ushort high_water; /* xoff mark */
};
typedef struct iovar IOVAR;
struct iovar
{
SCC *regs; /* UART register base address */
uchar wr3; /* content of write register 3 */
uchar wr4; /* content of write register 4 */
uchar wr5; /* content of write register 5 */
uchar lan; /* LAN port flag */
volatile ushort state; /* receiver state */
# define STATE_HARD 0x1 /* CTS is low */
# define STATE_SOFT 0x2 /* XOFF is set */
ushort shake; /* handshake mode */
# define SHAKE_HARD STATE_HARD /* RTS/CTS handshake enabled */
# define SHAKE_SOFT STATE_SOFT /* XON/XOFF handshake enabled */
uchar rx_full; /* input buffer full */
uchar tx_empty; /* output buffer empty */
uchar sendnow; /* control data, bypasses buffer */
uchar datmask; /* AND mask for read from sccdat */
uchar iointr; /* I/O interrupt */
uchar stintr; /* status interrupt */
ushort lan_dev; /* device number of LAN port */
# define LANDEV(iovar) (iovar->lan_dev)
IOREC input; /* input buffer */
IOREC output; /* output buffer */
BAUDS *table; /* baudrate vector */
long baudrate; /* current baud rate value */
ushort res1; /* padding */
ushort bdev; /* BIOS devnumber */
ushort iosleepers; /* number of precesses that are sleeping in I/O */
ushort lockpid; /* file locking */
ushort clocal; /* */
ushort brkint; /* */
FILEPTR *open; /* */
TTY tty; /* */
};
# define XON 0x11
# define XOFF 0x13
/*
* buffer manipulation - mixed
*/
INLINE int iorec_empty (IOREC *iorec);
INLINE int iorec_full (IOREC *iorec);
INLINE uchar iorec_get (IOREC *iorec);
INLINE int iorec_put (IOREC *iorec, uchar data);
INLINE long iorec_used (IOREC *iorec);
INLINE long iorec_free (IOREC *iorec);
INLINE ushort iorec_size (IOREC *iorec);
/*
* inline assembler primitives - bottom half
*/
INLINE void rts_on (IOVAR *iovar, SCC *regs);
INLINE void rts_off (IOVAR *iovar, SCC *regs);
INLINE void dtr_on (IOVAR *iovar, SCC *regs);
INLINE void dtr_off (IOVAR *iovar, SCC *regs);
INLINE void brk_on (IOVAR *iovar, SCC *regs);
INLINE void brk_off (IOVAR *iovar, SCC *regs);
INLINE void txint_off (IOVAR *iovar, SCC *regs);
/*
* inline assembler primitives - top half
*/
INLINE void top_rts_on (IOVAR *iovar);
INLINE void top_rts_off (IOVAR *iovar);
INLINE void top_dtr_on (IOVAR *iovar);
INLINE void top_dtr_off (IOVAR *iovar);
INLINE void top_brk_on (IOVAR *iovar);
INLINE void top_brk_off (IOVAR *iovar);
INLINE void top_txint_off (IOVAR *iovar);
/*
* initialization - top half
*/
static int init_SCC (IOVAR **iovar, SCC *regs);
INLINE void init_scc (void);
/*
* interrupt handling - bottom half
*/
INLINE void notify_top_half (IOVAR *iovar);
static void wr_scc (IOVAR *iovar, SCC *regs);
static void scca_txempty_asm(void);
static void scca_rxavail_asm(void);
static void scca_stchange_asm(void);
static void scca_special_asm(void);
static void sccb_txempty_asm(void);
static void sccb_rxavail_asm(void);
static void sccb_stchange_asm(void);
static void sccb_special_asm(void);
/*
* interrupt handling - top half
*/
static void check_ioevent (PROC *p, long arg);
static void soft_cdchange (PROC *p, long arg);
/*
* control functions - top half
*/
INLINE void send_byte (IOVAR *iovar);
static long ctl_TIOCBAUD (IOVAR *iovar, long *buf);
static ushort ctl_TIOCGFLAGS (IOVAR *iovar);
static long ctl_TIOCSFLAGS (IOVAR *iovar, ushort flags);
static long ctl_TIOCSFLAGSB (IOVAR *iovar, long flags, long mask);
/*
* start/stop primitives - top half
*/
static void rx_start (IOVAR *iovar);
static void rx_stop (IOVAR *iovar);
static void tx_start (IOVAR *iovar);
static void tx_stop (IOVAR *iovar);
static void flush_output (IOVAR *iovar);
static void flush_input (IOVAR *iovar);
/*
* bios emulation - top half
*/
static long _cdecl scc_instat (int dev);
static long _cdecl scc_in (int dev);
static long _cdecl scc_outstat (int dev);
static long _cdecl scc_out (int dev, int c);
static long _cdecl scc_rsconf (int dev, int speed, int flowctl, int ucr, int rsr, int tsr, int scr);
/*
* device driver routines - top half
*/
static long _cdecl scc_open (FILEPTR *f);
static long _cdecl scc_close (FILEPTR *f, int pid);
static long _cdecl scc_write (FILEPTR *f, const char *buf, long bytes);
static long _cdecl scc_read (FILEPTR *f, char *buf, long bytes);
static long _cdecl scc_writeb (FILEPTR *f, const char *buf, long bytes);
static long _cdecl scc_readb (FILEPTR *f, char *buf, long bytes);
static long _cdecl scc_twrite (FILEPTR *f, const char *buf, long bytes);
static long _cdecl scc_tread (FILEPTR *f, char *buf, long bytes);
static long _cdecl scc_lseek (FILEPTR *f, long where, int whence);
static long _cdecl scc_ioctl (FILEPTR *f, int mode, void *buf);
static long _cdecl scc_datime (FILEPTR *f, ushort *timeptr, int rwflag);
static long _cdecl scc_select (FILEPTR *f, long proc, int mode);
static void _cdecl scc_unselect (FILEPTR *f, long proc, int mode);
/*
* device driver maps
*/
static BDEVMAP bios_devtab =
{
scc_instat, scc_in,
scc_outstat, scc_out,
scc_rsconf
};
static DEVDRV hsmodem_devtab =
{
scc_open,
scc_write, scc_read, scc_lseek, scc_ioctl, scc_datime,
scc_close,
scc_select, scc_unselect,
NULL, NULL
};
static DEVDRV tty_devtab =
{
scc_open,
scc_twrite, scc_tread, scc_lseek, scc_ioctl, scc_datime,
scc_close,
scc_select, scc_unselect,
scc_writeb, scc_readb
};
/*
* debugging stuff
*/
# ifdef DEV_DEBUG
# define DEBUG(x) KERNEL_DEBUG x
# define TRACE(x) KERNEL_TRACE x
# define ALERT(x) KERNEL_ALERT x
# else
# define DEBUG(x)
# define TRACE(x)
# define ALERT(x) KERNEL_ALERT x
# endif
# ifdef INT_DEBUG
# define DEBUG_I(x) KERNEL_DEBUG x
# define TRACE_I(x) KERNEL_TRACE x
# define ALERT_I(x) KERNEL_ALERT x
# else
# define DEBUG_I(x)
# define TRACE_I(x)
# define ALERT_I(x) KERNEL_ALERT x
# endif
/* END definition part */
/****************************************************************************/
/****************************************************************************/
/* BEGIN buffer manipulation - mixed */
/* input:
*
* - iorec_empty : top
* - iorec_full : -
* - iorec_get : top
* - iorec_put : bottom
* - iorec_used : bottom & top - uncritical
* - iorec_free : -
* - iorec_size : uncritical
*
* -> interrupt safe interaction
*
*
* output:
*
* - iorec_empty : bottom
* - iorec_full : -
* - iorec_get : bottom
* - iorec_put : top
* - iorec_used : top
* - iorec_free : top
* - iorec_size : uncritical
*
* -> interrupt safe interaction
*/
INLINE ushort
inc_ptr (ushort ptr)
{
return (++ptr & IOBUFMASK);
}
INLINE int
iorec_empty (IOREC *iorec)
{
return (iorec->head == iorec->tail);
}
INLINE int
iorec_full (IOREC *iorec)
{
return (iorec->head == inc_ptr (iorec->tail));
}
INLINE uchar
iorec_get (IOREC *iorec)
{
register ushort i;
i = inc_ptr (iorec->head);
iorec->head = i;
return iorec->buffer[i];
}
INLINE int
iorec_put (IOREC *iorec, uchar data)
{
register ushort i = inc_ptr (iorec->tail);
if (i == iorec->head)
{
/* buffer full */
return 0;
}
iorec->buffer[i] = data;
iorec->tail = i;
return 1;
}
INLINE long
iorec_used (IOREC *iorec)
{
register long tmp;
tmp = iorec->tail;
tmp -= iorec->head;
if (tmp < 0)
tmp += IOBUFSIZE;
return tmp;
}
INLINE long
iorec_free (IOREC *iorec)
{
register long tmp;
tmp = iorec->head;
tmp -= iorec->tail;
if (tmp <= 0)
tmp += IOBUFSIZE;
return tmp;
}
INLINE ushort
iorec_size (IOREC *iorec)
{
return IOBUFSIZE;
}
/* END buffer manipulation - mixed */
/****************************************************************************/
/****************************************************************************/
/* BEGIN global data definition & access implementation */
/* values of MCH cookie
*/
# define ST 0
# define STE 0x00010000L
# define MEGASTE 0x00010010L
# define TT 0x00020000L
# define FALCON 0x00030000L
# define MILAN_C 0x00040000L
static long mch;
static ushort flag_14_7456_mhz = 0;
static IOVAR *iovar_scca;
static IOVAR *iovar_sccb;
# define IOVAR_MAX 4
static IOVAR *iovar_tab [IOVAR_MAX * 2];
# define IOVARS(nr) (iovar_tab [nr])
# define IOVAR_TTY_OFFSET (IOVAR_MAX)
# define IOVAR_REAL_MAX (IOVAR_MAX * 2)
static BAUDS baudtable_tt_scca [] =
{
{ 50, 2293, TAKT_16x, 0x50, 0x1 },
{ 75, 1528, TAKT_16x, 0x50, 0x1 },
// { 110, 2286, TAKT_16x, 0x50, 0x3 },
// { 134, 1876, TAKT_16x, 0x50, 0x3 },
// { 150, 763, TAKT_16x, 0x50, 0x1 },
// { 200, 1256, TAKT_16x, 0x50, 0x3 },
{ 300, 837, TAKT_16x, 0x50, 0x3 },
{ 600, 417, TAKT_16x, 0x50, 0x3 },
{ 1200, 208, TAKT_16x, 0x50, 0x3 },
{ 1800, 138, TAKT_16x, 0x50, 0x3 },
{ 2000, 124, TAKT_16x, 0x50, 0x3 },
{ 2400, 103, TAKT_16x, 0x50, 0x3 },
{ 3600, 68, TAKT_16x, 0x50, 0x3 },
{ 4800, 22, TAKT_16x, 0x50, 0x1 },
{ 9600, 10, TAKT_16x, 0x50, 0x1 },
{ 19200, 4, TAKT_16x, 0x50, 0x1 },
{ 38400, 1, TAKT_16x, 0x50, 0x1 },
{ 57600, 0, TAKT_16x, 0x50, 0x1 },
{ 115200, 0, TAKT_32x, 0x00, 0x0 },
{ 230400, 0, TAKT_16x, 0x00, 0x0 },
{ 0, 0, 0, 0, 0 }
};
static BAUDS baudtable_tt_sccb [] =
{
// { 50, 190, TAKT_16x, 0x50, 0x1 },
// { 75, 126, TAKT_16x, 0x50, 0x1 },
// { 110, 2286, TAKT_16x, 0x50, 0x3 },
{ 134, 1876, TAKT_16x, 0x50, 0x3 },
{ 150, 62, TAKT_16x, 0x50, 0x1 },
{ 200, 1256, TAKT_16x, 0x50, 0x3 },
{ 300, 30, TAKT_16x, 0x50, 0x1 },
{ 600, 417, TAKT_16x, 0x50, 0x3 },
{ 1200, 6, TAKT_16x, 0x50, 0x1 },
{ 1800, 138, TAKT_16x, 0x50, 0x3 },
{ 2000, 124, TAKT_16x, 0x50, 0x3 },
{ 2400, 2, TAKT_16x, 0x50, 0x1 },
{ 3600, 68, TAKT_16x, 0x50, 0x3 },
{ 4800, 0, TAKT_16x, 0x50, 0x1 },
{ 9600, 0, TAKT_32x, 0x00, 0x0 },
{ 19200, 0, TAKT_16x, 0x00, 0x0 },
{ 38400, 0, TAKT_64x, 0x28, 0x0 },
{ 76800, 0, TAKT_32x, 0x28, 0x0 },
{ 153600, 0, TAKT_16x, 0x28, 0x0 },
{ 0, 0, 0, 0, 0 }
};
# if 0
static BAUDS baudtable_falcon_scca [] =
{
{ 50, 2293, TAKT_16x, 0x50, 0x1 },
{ 75, 1528, TAKT_16x, 0x50, 0x1 },
// { 110, 2286, TAKT_16x, 0x50, 0x3 },
// { 134, 1876, TAKT_16x, 0x50, 0x3 },
// { 150, 763, TAKT_16x, 0x50, 0x1 },
// { 200, 1256, TAKT_16x, 0x50, 0x3 },
{ 300, 837, TAKT_16x, 0x50, 0x3 },
{ 600, 417, TAKT_16x, 0x50, 0x3 },
{ 1200, 208, TAKT_16x, 0x50, 0x3 },
{ 1800, 138, TAKT_16x, 0x50, 0x3 },
{ 2000, 124, TAKT_16x, 0x50, 0x3 },
{ 2400, 103, TAKT_16x, 0x50, 0x3 },
{ 3600, 68, TAKT_16x, 0x50, 0x3 },
{ 4800, 22, TAKT_16x, 0x50, 0x1 },
{ 9600, 10, TAKT_16x, 0x50, 0x1 },
{ 19200, 4, TAKT_16x, 0x50, 0x1 },
{ 38400, 1, TAKT_16x, 0x50, 0x1 },
{ 57600, 0, TAKT_16x, 0x50, 0x1 },
{ 115200, 0, TAKT_32x, 0x00, 0x0 },
{ 230400, 0, TAKT_16x, 0x00, 0x0 },
{ 0, 0, 0, 0, 0 }
};
# endif
static BAUDS baudtable_falcon_sccb [] =
{
// { 50, 2293, TAKT_16x, 0x50, 0x1 },
// { 75, 1528, TAKT_16x, 0x50, 0x1 },
// { 110, 2286, TAKT_16x, 0x50, 0x3 },
// { 134, 1876, TAKT_16x, 0x50, 0x3 },
// { 150, 763, TAKT_16x, 0x50, 0x1 },
// { 200, 1256, TAKT_16x, 0x50, 0x3 },
{ 300, 837, TAKT_16x, 0x50, 0x3 },
{ 600, 417, TAKT_16x, 0x50, 0x3 },
{ 1200, 208, TAKT_16x, 0x50, 0x3 },
{ 1800, 138, TAKT_16x, 0x50, 0x3 },
{ 2000, 124, TAKT_16x, 0x50, 0x3 },
{ 2400, 103, TAKT_16x, 0x50, 0x3 },
{ 3600, 68, TAKT_16x, 0x50, 0x3 },
{ 4800, 22, TAKT_16x, 0x50, 0x1 },
{ 9600, 10, TAKT_16x, 0x50, 0x1 },
{ 19200, 4, TAKT_16x, 0x50, 0x1 },
{ 38400, 0, TAKT_64x, 0x28, 0x0 },
{ 57600, 0, TAKT_16x, 0x50, 0x1 },
{ 76800, 0, TAKT_32x, 0x28, 0x0 },
{ 115200, 0, TAKT_32x, 0x00, 0x0 },
{ 153600, 0, TAKT_16x, 0x28, 0x0 },
{ 230400, 0, TAKT_16x, 0x00, 0x0 },
{ 0, 0, 0, 0, 0 }
};
/* PCLK 14.7456 MHZ
*
* TT (modified)
* Hades
*/
static BAUDS baudtable_14_7456_mhz [] =
{
// { 50, 9214, TAKT_16x, 0x50, 0x3 },
// { 75, 6142, TAKT_16x, 0x50, 0x3 },
// { 110, 4187, TAKT_16x, 0x50, 0x3 },
// { 134, 854, TAKT_16x, 0x50, 0x1 },
// { 150, 3070, TAKT_16x, 0x50, 0x3 },
// { 200, 2302, TAKT_16x, 0x50, 0x3 },
{ 300, 1534, TAKT_16x, 0x50, 0x3 },
{ 600, 766, TAKT_16x, 0x50, 0x3 },
{ 1200, 382, TAKT_16x, 0x50, 0x3 },
{ 1800, 254, TAKT_16x, 0x50, 0x3 },
{ 2000, 228, TAKT_16x, 0x50, 0x3 },
{ 2400, 190, TAKT_16x, 0x50, 0x3 },
{ 3600, 126, TAKT_16x, 0x50, 0x3 },
{ 4800, 94, TAKT_16x, 0x50, 0x3 },
{ 9600, 46, TAKT_16x, 0x50, 0x3 },
{ 19200, 22, TAKT_16x, 0x50, 0x3 },
{ 38400, 10, TAKT_16x, 0x50, 0x3 },
{ 57600, 6, TAKT_16x, 0x50, 0x3 },
{ 76800, 4, TAKT_16x, 0x50, 0x3 },
{ 115200, 2, TAKT_16x, 0x50, 0x3 },
{ 153600, 1, TAKT_16x, 0x50, 0x3 },
{ 230400, 0, TAKT_16x, 0x50, 0x3 },
{ 0, 0, 0, 0, 0 }
};
/* END global data & access implementation */
/****************************************************************************/
/****************************************************************************/
/* BEGIN SCC register access */
# define ZS_PAUSE udelay (10)
INLINE void
ZS_WRITE_0 (SCC *regs, uchar data)
{
regs->sccctl = data;
ZS_PAUSE;
}
INLINE void
ZS_WRITE (SCC *regs, uchar reg, uchar data)
{
regs->sccctl = reg;
ZS_PAUSE;
regs->sccctl = data;
ZS_PAUSE;
}
INLINE void
ZS_WRITE_DATA (SCC *regs, uchar data)
{
regs->sccdat = data;
ZS_PAUSE;
}
INLINE uchar
ZS_READ_0 (SCC *regs)
{
return regs->sccctl;
}
INLINE uchar
ZS_READ (SCC *regs, uchar reg)
{
regs->sccctl = reg;
ZS_PAUSE;
return regs->sccctl;
}
INLINE uchar
ZS_READ_DATA (SCC *regs)
{
return regs->sccdat;
}
/* END SCC register access */
/****************************************************************************/
/****************************************************************************/
/* BEGIN inline assembler primitives - bottom half */
INLINE void
rts_on (IOVAR *iovar, SCC *regs)
{
iovar->wr5 |= RTS;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
rts_off (IOVAR *iovar, SCC *regs)
{
iovar->wr5 &= ~RTS;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
dtr_on (IOVAR *iovar, SCC *regs)
{
iovar->wr5 |= DTR;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
dtr_off (IOVAR *iovar, SCC *regs)
{
iovar->wr5 &= ~DTR;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
brk_on (IOVAR *iovar, SCC *regs)
{
iovar->wr5 |= SBRK;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
brk_off (IOVAR *iovar, SCC *regs)
{
iovar->wr5 &= ~SBRK;
ZS_WRITE (regs, WR5, iovar->wr5);
}
INLINE void
txint_off (IOVAR *iovar, SCC *regs)
{
ZS_WRITE_0 (regs, RESINT);
}
/* END inline assembler primitives - bottom half */
/****************************************************************************/
/****************************************************************************/
/* BEGIN inline assembler primitives - top half */
INLINE void
top_rts_on (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
rts_on (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_rts_off (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
rts_off (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_dtr_on (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
dtr_on (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_dtr_off (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
dtr_off (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_brk_on (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
brk_on (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_brk_off (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
brk_off (iovar, iovar->regs);
spl (sr);
}
INLINE void
top_txint_off (IOVAR *iovar)
{
ushort sr;
sr = splhigh ();
ZS_WRITE_0 (iovar->regs, RESINT);
spl (sr);
}
/* END inline assembler primitives - top half */
/****************************************************************************/
/****************************************************************************/
/* BEGIN initialization - top half */
static int
init_SCC (IOVAR **iovar, SCC *regs)
{
char *buffer = NULL;
*iovar = kmalloc (sizeof (**iovar));
// *iovar = m_xalloc (sizeof (**iovar), 0x20|0);
if (!*iovar)
goto error;
bzero (*iovar, sizeof (**iovar));
buffer = kmalloc (2 * IOBUFSIZE);
// buffer = m_xalloc (2 * IOBUFSIZE, 0x20|0);
if (!buffer)
goto error;
(*iovar)->input.buffer = (unsigned char *)buffer;
(*iovar)->input.low_water = 1 * (IOBUFSIZE / 4);
(*iovar)->input.high_water = 3 * (IOBUFSIZE / 4);
(*iovar)->output.buffer = (unsigned char *)buffer + IOBUFSIZE;
(*iovar)->output.low_water = 1 * (IOBUFSIZE / 4);
(*iovar)->output.high_water = 3 * (IOBUFSIZE / 4);
(*iovar)->regs = regs;
{
static const uchar init_reglist [] =
{
WR4, STB_ASYNC1|TAKT_16x,
WR1, 0x04,
WR2, 0x60,
WR3, 0xC0,
WR5, TX8BIT,
WR6, 0x00,
WR7, 0x00,
WR9, 0x01,
WR10, 0x00,
WR11, 0x50,
WR12, 0x18,
WR13, 0x00,
WR14, 0x02,
WR14, 0x03,
WR3, 0xC1,
WR5, TXEN|TX8BIT,
WR15, 0x08|0x20, /* CD, RTS intr enable */
WR0, 0x10,
WR0, 0x10,
WR1, 0x17,
WR9, 0x09,
0xff /* end */
};
const uchar *src = init_reglist;
ushort sr;
uchar ctlreg;
sr = splhigh ();
while (*src != 0xff)
{
ZS_WRITE (regs, src[0], src[1]);
src += 2;
}
spl (sr);