From 7dcb109a1af764eafdd1b9cb2f7c48f33c2d8a14 Mon Sep 17 00:00:00 2001 From: jensen Date: Fri, 13 Nov 2015 18:57:09 +0800 Subject: [PATCH] ARM: s5p4418: Add new board `nanopi2' (<-- drone) --- Makefile | 3 +- arch/arm/configs/nanopi2_android_defconfig | 3181 +++++++++++++++++ arch/arm/plat-s5p4418/Kconfig | 50 +- arch/arm/plat-s5p4418/Makefile | 6 +- arch/arm/plat-s5p4418/nanopi2/Makefile | 10 + arch/arm/plat-s5p4418/nanopi2/board.c | 215 ++ arch/arm/plat-s5p4418/nanopi2/dev-ion.c | 30 + arch/arm/plat-s5p4418/nanopi2/device.c | 1222 +++++++ .../plat-s5p4418/nanopi2/include/axp22-cfg.h | 97 + .../plat-s5p4418/nanopi2/include/cfg_gpio.h | 269 ++ .../plat-s5p4418/nanopi2/include/cfg_main.h | 312 ++ .../plat-s5p4418/nanopi2/include/cfg_mem.h | 32 + arch/arm/plat-s5p4418/nanopi2/pm.c | 39 + arch/arm/plat-s5p4418/nanopi2/usb-connector.c | 460 +++ 14 files changed, 5900 insertions(+), 26 deletions(-) create mode 100644 arch/arm/configs/nanopi2_android_defconfig create mode 100644 arch/arm/plat-s5p4418/nanopi2/Makefile create mode 100644 arch/arm/plat-s5p4418/nanopi2/board.c create mode 100644 arch/arm/plat-s5p4418/nanopi2/dev-ion.c create mode 100644 arch/arm/plat-s5p4418/nanopi2/device.c create mode 100644 arch/arm/plat-s5p4418/nanopi2/include/axp22-cfg.h create mode 100644 arch/arm/plat-s5p4418/nanopi2/include/cfg_gpio.h create mode 100644 arch/arm/plat-s5p4418/nanopi2/include/cfg_main.h create mode 100644 arch/arm/plat-s5p4418/nanopi2/include/cfg_mem.h create mode 100644 arch/arm/plat-s5p4418/nanopi2/pm.c create mode 100644 arch/arm/plat-s5p4418/nanopi2/usb-connector.c diff --git a/Makefile b/Makefile index 5de9b43bc86..0d6394df236 100644 --- a/Makefile +++ b/Makefile @@ -192,7 +192,8 @@ SUBARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ \ # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile export KBUILD_BUILDHOST := $(SUBARCH) -ARCH ?= $(SUBARCH) +#ARCH ?= $(SUBARCH) +ARCH ?= arm CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%) # Architecture as present in compile.h diff --git a/arch/arm/configs/nanopi2_android_defconfig b/arch/arm/configs/nanopi2_android_defconfig new file mode 100644 index 00000000000..0d881904b22 --- /dev/null +++ b/arch/arm/configs/nanopi2_android_defconfig @@ -0,0 +1,3181 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.4.39 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_LOCKBREAK=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_NEED_MACH_IO_H=y +CONFIG_NEED_MACH_MEMORY_H=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="arm-linux-" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +CONFIG_DEFAULT_HOSTNAME="S5P4418" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_FHANDLE is not set +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_DEBUG=y + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_FANOUT=32 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_CGROUP_MEM_RES_CTLR=y +# CONFIG_CGROUP_MEM_RES_CTLR_KMEM is not set +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +# CONFIG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_MM_OWNER=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_PANIC_TIMEOUT=5 +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +# CONFIG_AIO is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +CONFIG_ARCH_S5P4418=y +# CONFIG_ARCH_S5P6818 is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +CONFIG_HZ_1000=y +CONFIG_HZ=1000 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_CPU_SLSI=y +CONFIG_S5P4418_PROTO_RELEASE=y +# CONFIG_S5P4418_PROTO_DEBUG is not set +CONFIG_S5P4418_MEM_MAX_ORDER_11=y +# CONFIG_S5P4418_MEM_MAX_ORDER_12 is not set +# CONFIG_S5P4418_MEM_MAX_ORDER_13 is not set +CONFIG_FORCE_MAX_ZONEORDER=11 + +# +# CPU feature +# +CONFIG_SUSPEND_POWEROFF=y +# CONFIG_SUSPEND_IDLE is not set +CONFIG_CPU_S5P4418_SMP_ISR=y +CONFIG_CPU_S5P4418_EX_PERI_BUS=y +CONFIG_PWM_SYSFS=y +CONFIG_HAVE_PWM_CH0=y +# CONFIG_HAVE_PWM_CH1 is not set +# CONFIG_HAVE_PWM_CH2 is not set +# CONFIG_HAVE_PWM_CH3 is not set +CONFIG_NXP_PWM=y +CONFIG_NXP_DISPLAY=y +CONFIG_NXP_DISPLAY_1ST=y +CONFIG_NXP_DISPLAY_2ST=y +CONFIG_NXP_DISPLAY_RESCONV=y +# CONFIG_NXP_DFS_BCLK is not set +CONFIG_ANDROID_PERSISTENT_RAM_CONS_AREA=0x0 +CONFIG_ANDROID_PERSISTENT_RAM_CONS_SIZE=16 +# CONFIG_PM_DBGOUT is not set + +# +# Board features +# +# CONFIG_PLAT_S5P4418_DRONE is not set +# CONFIG_PLAT_S5P4418_SVT is not set +# CONFIG_PLAT_S5P4418_ASB is not set +# CONFIG_PLAT_S5P4418_LEPUS is not set +CONFIG_PLAT_S5P4418_NANOPI2=y + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_TRUSTZONE is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_CPU_HAS_PMU=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_742230 is not set +# CONFIG_ARM_ERRATA_742231 is not set +# CONFIG_PL310_ERRATA_588369 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_PL310_ERRATA_727915 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_PL310_ERRATA_753970 is not set +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +# CONFIG_ARM_ERRATA_764369 is not set +# CONFIG_PL310_ERRATA_769419 is not set +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_766421 is not set +# CONFIG_ARM_ERRATA_773022 is not set +# CONFIG_ARM_ERRATA_774769 is not set +# CONFIG_ARM_ERRATA_798181 is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_VIC=y +CONFIG_ARM_VIC_NR=2 +# CONFIG_FIQ_DEBUGGER is not set + +# +# Bus support +# +CONFIG_ARM_AMBA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_SMT=y +CONFIG_HAVE_ARM_SCU=y +CONFIG_HAVE_ARM_TWD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_CLEANCACHE is not set +CONFIG_CMA=y +CONFIG_CMA_DEVELOPEMENT=y +CONFIG_CMA_DEBUG=y +CONFIG_CMA_SYSFS=y +CONFIG_CMA_CMDLINE=y +CONFIG_CMA_BEST_FIT=y +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="console=ttyAMA0,115200n8 androidboot.console=ttyAMA0 androidboot.serialno=0123456789abcdef initrd=0x49000000,0x100000 init=/init" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_AUTO_ZRELADDR is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set +CONFIG_ARM_NXP_CPUFREQ=y +# CONFIG_ARM_NXP_CPUFREQ_DEBUG is not set +# CONFIG_ARM_NXP_CPUFREQ_VOLTAGE_DEBUG is not set +# CONFIG_ARM_NXP_CPUFREQ_BY_RESOURCE is not set +# CONFIG_NXP_CPUFREQ_PLL_0 is not set +CONFIG_NXP_CPUFREQ_PLL_1=y +CONFIG_NXP_CPUFREQ_PLLDEV=1 +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_WAKELOCK=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_PM_AUTOSLEEP=y +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=0 +# CONFIG_PM_WAKELOCKS_GC is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_CAN_PM_TRACE=y +# CONFIG_APM_EMULATION is not set +CONFIG_CPU_PM=y +CONFIG_SUSPEND_TIME=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +CONFIG_INET_ESP=y +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +# CONFIG_IPV6_ROUTE_INFO is not set +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_MULTIPLE_TABLES=y +# CONFIG_IPV6_SUBTREES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETLABEL is not set +CONFIG_ANDROID_PARANOID_NETWORK=y +CONFIG_NET_ACTIVITY_STATS=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +# CONFIG_NF_CONNTRACK_SECMARK is not set +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +# CONFIG_NF_CONNTRACK_SIP is not set +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +# CONFIG_NETFILTER_XT_TARGET_CT is not set +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +# CONFIG_NETFILTER_XT_TARGET_HL is not set +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ECN=y +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QTAGUID=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +# CONFIG_IP_NF_MATCH_RPFILTER is not set +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_REJECT_SKERR=y +# CONFIG_IP_NF_TARGET_ULOG is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_PROTO_UDPLITE=y +CONFIG_NF_NAT_PROTO_SCTP=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +# CONFIG_NF_NAT_SIP is not set +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +CONFIG_IP_NF_RAW=y +# CONFIG_IP_NF_SECURITY is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_TARGET_REJECT_SKERR=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +# CONFIG_IP6_NF_SECURITY is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_PHONET=y +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +CONFIG_NET_SCH_HTB=y +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_PLUG is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +CONFIG_NET_EMATCH_U32=y +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +# CONFIG_GACT_PROB is not set +CONFIG_NET_ACT_MIRRED=y +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_NETPRIO_CGROUP is not set +CONFIG_BQL=y +CONFIG_HAVE_BPF_JIT=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_RTKBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_LL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +# CONFIG_CFG80211_ALLOW_RECONNECT is not set +# CONFIG_MAC80211 is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_RFKILL_REGULATOR is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_NFC_DEVICES is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_SYNC=y +CONFIG_SW_SYNC=y +CONFIG_SW_SYNC_USER=y +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set + +# +# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +# +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_NXP_FTL is not set + +# +# Misc devices +# +# CONFIG_HAPTIC_DRV260X is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HAPTIC_ISA1200 is not set +# CONFIG_SAMSUNG_JACK is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_UID_STAT=y +# CONFIG_BMP085 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_STMPE811_ADC is not set +# CONFIG_AUDIENCE_ES305 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +# CONFIG_SLSIAP_BACKWARD_CAMERA is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_NXP is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_PHYLIB is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=y +CONFIG_PPP_BSDCOMP=y +CONFIG_PPP_DEFLATE=y +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPPOE is not set +CONFIG_PPPOLAC=y +CONFIG_PPPOPNS=y +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=y +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET=y +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=y +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_CDC_PHONET is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_KEYRESET=y + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NXP_KEY is not set +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y +# CONFIG_JOYSTICK_ANALOG is not set +# CONFIG_JOYSTICK_A3D is not set +# CONFIG_JOYSTICK_ADI is not set +# CONFIG_JOYSTICK_COBRA is not set +# CONFIG_JOYSTICK_GF2K is not set +# CONFIG_JOYSTICK_GRIP is not set +# CONFIG_JOYSTICK_GRIP_MP is not set +# CONFIG_JOYSTICK_GUILLEMOT is not set +# CONFIG_JOYSTICK_INTERACT is not set +# CONFIG_JOYSTICK_SIDEWINDER is not set +# CONFIG_JOYSTICK_TMDC is not set +# CONFIG_JOYSTICK_IFORCE is not set +# CONFIG_JOYSTICK_WARRIOR is not set +# CONFIG_JOYSTICK_MAGELLAN is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_STINGER is not set +# CONFIG_JOYSTICK_TWIDJOY is not set +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JOYSTICK_AS5011 is not set +# CONFIG_JOYSTICK_JOYDUMP is not set +CONFIG_JOYSTICK_XPAD=y +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_INPUT_TABLET=y +# CONFIG_TABLET_USB_ACECAD is not set +# CONFIG_TABLET_USB_AIPTEK is not set +# CONFIG_TABLET_USB_GTCO is not set +# CONFIG_TABLET_USB_HANWANG is not set +# CONFIG_TABLET_USB_KBTAB is not set +# CONFIG_TABLET_USB_WACOM is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX_I2C is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +# CONFIG_TOUCHSCREEN_FT5X0X is not set +# CONFIG_TOUCHSCREEN_AW5306 is not set +# CONFIG_TOUCHSCREEN_GSLX680 is not set +# CONFIG_TOUCHSCREEN_HC8600 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT640T is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYCHORD is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +CONFIG_INPUT_GPIO=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_CMA3000 is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_AMBAKMI is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_NXP_S3C is not set +CONFIG_SERIAL_NXP_UART0=y +# CONFIG_SERIAL_NXP_UART0_DMA is not set +# CONFIG_SERIAL_NXP_UART1 is not set +# CONFIG_SERIAL_NXP_UART2 is not set +# CONFIG_SERIAL_NXP_UART3 is not set +# CONFIG_SERIAL_NXP_UART4 is not set +# CONFIG_SERIAL_NXP_UART5 is not set +CONFIG_SERIAL_NXP_RESUME_WORK=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DCC_TTY is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_GPIO=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set +# CONFIG_I2C_SLSI is not set +CONFIG_I2C_NXP=y +CONFIG_I2C_NXP_PORT0=y +CONFIG_I2C_NXP_PORT0_GPIO_MODE=y +CONFIG_I2C_NXP_PORT1=y +# CONFIG_I2C_NXP_PORT1_GPIO_MODE is not set +CONFIG_I2C_NXP_PORT2=y +# CONFIG_I2C_NXP_PORT2_GPIO_MODE is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_SLSI is not set +CONFIG_SPI_PL022=y +CONFIG_SPI_PL022_PORT0=y +CONFIG_USE_DMA_PORT0=y +# CONFIG_SPI_PL022_PORT1 is not set +# CONFIG_USE_DMA_PORT1 is not set +# CONFIG_SPI_PL022_PORT2 is not set +# CONFIG_USE_DMA_PORT2 is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_PL061 is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +CONFIG_GPIO_NXP=y +CONFIG_GPIO_NXP_GROUP_A=y +CONFIG_GPIO_NXP_GROUP_B=y +CONFIG_GPIO_NXP_GROUP_C=y +CONFIG_GPIO_NXP_GROUP_D=y +CONFIG_GPIO_NXP_GROUP_E=y +CONFIG_GPIO_NXP_GROUP_ALV=y +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_KP_AXP is not set +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_FUELGAUGE_DS2784 is not set +# CONFIG_BATTERY_NXE2000 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_SMB347 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_MMA7660 is not set +# CONFIG_SENSORS_MMA865X is not set +# CONFIG_SENSORS_STK831X is not set +# CONFIG_SENSORS_NXP_ADC_TEMP is not set +# CONFIG_BOSCH is not set +# CONFIG_SENSORS_BMA222E_NX is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_NXP_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_NXE2000 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_S5M_CORE is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_RC5T583 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_NXE2000 is not set +# CONFIG_REGULATOR_MP8845C is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=y + +# +# Multimedia drivers +# +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_ATTACH is not set +CONFIG_MEDIA_TUNER=y +# CONFIG_MEDIA_TUNER_CUSTOMISE is not set +CONFIG_MEDIA_TUNER_SIMPLE=y +CONFIG_MEDIA_TUNER_TDA8290=y +CONFIG_MEDIA_TUNER_TDA827X=y +CONFIG_MEDIA_TUNER_TDA18271=y +CONFIG_MEDIA_TUNER_TDA9887=y +CONFIG_MEDIA_TUNER_TEA5761=y +CONFIG_MEDIA_TUNER_TEA5767=y +CONFIG_MEDIA_TUNER_MT20XX=y +CONFIG_MEDIA_TUNER_XC2028=y +CONFIG_MEDIA_TUNER_XC5000=y +CONFIG_MEDIA_TUNER_XC4000=y +CONFIG_MEDIA_TUNER_MC44S803=y +CONFIG_VIDEO_V4L2=y +CONFIG_V4L2_MEM2MEM_DEV=y +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_CMA_PHYS=y +CONFIG_VIDEOBUF2_ION_NXP=y +CONFIG_V4L2_NXP=y +CONFIG_VIDEO_NXP_CAPTURE=y +CONFIG_NXP_CAPTURE_DECIMATOR=y +# CONFIG_NXP_CAPTURE_MIPI_CSI is not set +CONFIG_TURNAROUND_VIP_RESET=y +# CONFIG_LOOPBACK_SENSOR_DRIVER is not set +CONFIG_VIDEO_NXP_M2M=y +CONFIG_NXP_M2M_SCALER=y +CONFIG_ENABLE_SCALER_MISC_DEVICE=y +CONFIG_USE_SCALER_COMMAND_BUFFER=y +# CONFIG_NXP_M2M_DEINTERLACER is not set +CONFIG_VIDEO_NXP_OUT=y +CONFIG_NXP_OUT_RESOLUTION_CONVERTER=y +CONFIG_NXP_OUT_HDMI=y +CONFIG_NXP_HDMI_AUDIO_SPDIF=y +# CONFIG_NXP_HDMI_AUDIO_I2S is not set +# CONFIG_NXP_HDMI_USE_HDCP is not set +CONFIG_NXP_HDMI_CEC=y +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_TW9992 is not set +# CONFIG_VIDEO_TW9900 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# MPEG video encoders +# +# CONFIG_VIDEO_CX2341X is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9M032 is not set +# CONFIG_VIDEO_MT9P031 is not set +# CONFIG_VIDEO_MT9T001 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_MT9V032 is not set +# CONFIG_VIDEO_MT9D111_CAM is not set +# CONFIG_VIDEO_THP7212_CAM is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SR030PC30 is not set +# CONFIG_VIDEO_NOON010PC30 is not set +# CONFIG_VIDEO_S5K4ECGX is not set +# CONFIG_VIDEO_S5K5CAGX is not set +CONFIG_VIDEO_SP2518=y +CONFIG_VIDEO_SP2518_FIXED_FRAMERATE=y +# CONFIG_VIDEO_GC2035 is not set +# CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_HM2057 is not set +# CONFIG_VIDEO_SP0A19 is not set +CONFIG_VIDEO_SP0838=y +CONFIG_VIDEO_SP0838_FIXED_FRAMERATE=y +# CONFIG_VIDEO_OV5645 is not set +# CONFIG_VIDEO_S5K6AA is not set + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set +# CONFIG_VIDEO_AS3645A is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_V4L_USB_DRIVERS is not set +# CONFIG_V4L_PLATFORM_DRIVERS is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_RADIO_ADAPTERS is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +CONFIG_ION=y +CONFIG_ION_NXP=y +CONFIG_ION_NXP_CONTIGHEAP_SIZE=196608 +# CONFIG_ION_NXP_RESERVE is not set + +# +# ARM GPU Configuration +# +# CONFIG_MALI_T6XX is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_WMT_GE_ROPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_FB_NXP=y +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LCD_PLATFORM is not set +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_MIPI_S6E8AB0 is not set +# CONFIG_LCD_MIPI_TC358764 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LP855X is not set + +# +# Nexell Graphics +# +CONFIG_FB_NXP_ION_MEM=y +CONFIG_FB0_NXP=y +CONFIG_FB0_NXP_DISPOUT=0 +# CONFIG_FB1_NXP is not set +CONFIG_NXP_DISPLAY_LCD=y +CONFIG_NXP_DISPLAY_LCD_IN=0 +# CONFIG_NXP_DISPLAY_LVDS is not set +# CONFIG_NXP_DISPLAY_MIPI is not set +# CONFIG_NXP_DISPLAY_TVOUT is not set +# CONFIG_NXP_DISPLAY_HDMI is not set +CONFIG_NXP_DISPLAY_HDMI_AUDIO_SPDIF=y +# CONFIG_NXP_DISPLAY_HDMI_AUDIO_I2S is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +# CONFIG_LOGO_LINUX_CLUT224 is not set +CONFIG_LOGO_NXP_COPY=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +CONFIG_SND_NXP_SOC=y +# CONFIG_SND_NXP_DFS is not set +CONFIG_SND_NXP_I2S=y +CONFIG_SND_NXP_I2S_CH0=y +# CONFIG_SND_NXP_I2S_CH1 is not set +# CONFIG_SND_NXP_I2S_CH2 is not set +CONFIG_SND_NXP_SPDIF_TX=y +CONFIG_SND_SPDIF_TRANSCIEVER=y +# CONFIG_SND_SPDIF_RECEIVER is not set +# CONFIG_SND_PDM_REC is not set +# CONFIG_SND_CODEC_NULL is not set +# CONFIG_SND_CODEC_RT5631 is not set +# CONFIG_SND_CODEC_ES8316 is not set +# CONFIG_SND_CODEC_ALC5623 is not set +# CONFIG_SND_CODEC_ALC5633 is not set +# CONFIG_SND_CODEC_WM8976 is not set +# CONFIG_SND_CODEC_CS42L51_NX is not set +# CONFIG_SND_CODEC_WM8903 is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_SPDIF=y +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +CONFIG_UHID=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +CONFIG_HID_ACRUX=y +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_APPLE=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +CONFIG_HID_PRODIKEYS=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_DRAGONRISE=y +CONFIG_DRAGONRISE_FF=y +CONFIG_HID_EMS_FF=y +# CONFIG_HID_ELECOM is not set +CONFIG_HID_EZKEY=y +CONFIG_HID_HOLTEK=y +# CONFIG_HOLTEK_FF is not set +CONFIG_HID_KEYTOUCH=y +CONFIG_HID_KYE=y +CONFIG_HID_UCLOGIC=y +CONFIG_HID_WALTOP=y +CONFIG_HID_GYRATION=y +CONFIG_HID_TWINHAN=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_LCPOWER=y +CONFIG_HID_LOGITECH=y +CONFIG_HID_LOGITECH_DJ=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGIG940_FF=y +CONFIG_LOGIWHEELS_FF=y +# CONFIG_HID_MAGICMOUSE is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_HID_MULTITOUCH=y +CONFIG_HID_NTRIG=y +CONFIG_HID_ORTEK=y +CONFIG_HID_PANTHERLORD=y +CONFIG_PANTHERLORD_FF=y +CONFIG_HID_PETALYNX=y +CONFIG_HID_PICOLCD=y +# CONFIG_HID_PICOLCD_FB is not set +# CONFIG_HID_PICOLCD_BACKLIGHT is not set +# CONFIG_HID_PICOLCD_LCD is not set +# CONFIG_HID_PICOLCD_LEDS is not set +CONFIG_HID_PRIMAX=y +CONFIG_HID_ROCCAT=y +CONFIG_HID_SAITEK=y +CONFIG_HID_SAMSUNG=y +CONFIG_HID_SONY=y +CONFIG_HID_SPEEDLINK=y +CONFIG_HID_SUNPLUS=y +CONFIG_HID_GREENASIA=y +CONFIG_GREENASIA_FF=y +CONFIG_HID_SMARTJOYPLUS=y +CONFIG_SMARTJOYPLUS_FF=y +CONFIG_HID_TIVO=y +CONFIG_HID_TOPSEED=y +CONFIG_HID_THRUSTMASTER=y +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +CONFIG_HID_ZEROPLUS=y +# CONFIG_ZEROPLUS_FF is not set +CONFIG_HID_ZYDACRON=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +CONFIG_USB_DEVICE_CLASS=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_SYNOPSYS=y +# CONFIG_USB_HSIC_SYNOPSYS is not set +CONFIG_USB_EHCI_SYNOPSYS_RESUME_WORK=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_DWCOTG=y +# CONFIG_USB_CONNECT_NXP_DRV is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +CONFIG_USB_GADGET_DWCOTG=y +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_AUDIO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_MASS_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +CONFIG_USB_G_ANDROID=y +# CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_NOKIA is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +CONFIG_USB_OTG_WAKELOCK=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set +# CONFIG_MMC_EMBEDDED_SDIO is not set +# CONFIG_MMC_PARANOID_SD_INIT is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_MMC_BLOCK_DEFERRED_RESUME is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_ARMMMCI is not set +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_PLTFM=y +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +CONFIG_MMC_NXP=y +CONFIG_MMC_NXP_CH0=y +CONFIG_MMC_NXP_CH0_USE_DMA=y +# CONFIG_MMC_NXP_CH1 is not set +# CONFIG_MMC_NXP_CH2 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_TRIGGERS is not set + +# +# LED Triggers +# +CONFIG_SWITCH=y +# CONFIG_SWITCH_GPIO is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +CONFIG_RTC_DRV_NXP=y +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_AMBA_PL08X=y +# CONFIG_AMBA_PL08X_USE_ISR is not set +# CONFIG_TIMB_DMA is not set +# CONFIG_PL330_DMA is not set +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +# CONFIG_ECHO is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_LINE6_USB is not set +CONFIG_IIO=y +# CONFIG_IIO_ST_HWMON is not set +CONFIG_IIO_BUFFER=y +CONFIG_IIO_SW_RING=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_KXSD9 is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_SCA3000 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_ADT7310 is not set +# CONFIG_ADT7410 is not set +# CONFIG_AD7280 is not set +# CONFIG_MAX1363 is not set +CONFIG_NXP_ADC=y + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5686 is not set +# CONFIG_MAX517 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_INV_MPU_IIO is not set + +# +# Light sensors +# +# CONFIG_SENSORS_BH1721 is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Pressure sensors +# +# CONFIG_BMP182 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_PERSISTENT_RAM=y +CONFIG_ANDROID_RAM_CONSOLE=y +# CONFIG_PERSISTENT_TRACER is not set +CONFIG_ANDROID_TIMED_OUTPUT=y +CONFIG_ANDROID_TIMED_GPIO=y +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y +# CONFIG_ANDROID_SWITCH is not set +CONFIG_ANDROID_INTF_ALARM_DEV=y +# CONFIG_PHONE is not set +# CONFIG_USB_WPAN_HCD is not set +CONFIG_HAVE_MACH_CLKDEV=y + +# +# Hardware Spinlock drivers +# +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers (EXPERIMENTAL) +# + +# +# Rpmsg drivers (EXPERIMENTAL) +# +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_PM_DEVFREQ is not set + +# +# MobiCore secure driver +# + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_HARDLOCKUP_DETECTOR_NMI is not set +CONFIG_HARDLOCKUP_DETECTOR_OTHER_CPU=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_EVENT_POWER_TRACING_DEPRECATED=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +CONFIG_DYNAMIC_DEBUG=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_KDB=y +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_RODATA=y +CONFIG_DEBUG_RODATA_TEST=y +# CONFIG_DEBUG_LL is not set +# CONFIG_OC_ETM is not set +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=4096 +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set +# CONFIG_SECURITY_SELINUX_DISABLE is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY="selinux" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +# CONFIG_AVERAGE is not set +# CONFIG_CORDIC is not set diff --git a/arch/arm/plat-s5p4418/Kconfig b/arch/arm/plat-s5p4418/Kconfig index 7f14642cc62..1a96411d5e3 100644 --- a/arch/arm/plat-s5p4418/Kconfig +++ b/arch/arm/plat-s5p4418/Kconfig @@ -6,28 +6,33 @@ comment "Board features" choice - prompt "Platform board" - default PLAT_S5P4418_DRONE - - config PLAT_S5P4418_DRONE - bool "DRONE: Android drone board" - help - Support for the drone board. - - config PLAT_S5P4418_SVT - bool "SVT: Linux svt board" - help - Support for the svt board. - - config PLAT_S5P4418_ASB - bool "ASB: Linux asb board" - help - Support for the asb board. - - config PLAT_S5P4418_LEPUS - bool "DRONE: Android lepus board" - help - Support for the drone board. + prompt "Platform board" + default PLAT_S5P4418_DRONE + +config PLAT_S5P4418_DRONE + bool "DRONE: Android drone board" + help + Support for the drone board. + +config PLAT_S5P4418_SVT + bool "SVT: Linux svt board" + help + Support for the svt board. + +config PLAT_S5P4418_ASB + bool "ASB: Linux asb board" + help + Support for the asb board. + +config PLAT_S5P4418_LEPUS + bool "DRONE: Android lepus board" + help + Support for the drone board. + +config PLAT_S5P4418_NANOPI2 + bool "NANOPI2: FriendlyARM S5P4418 board" + help + Support for the NanoPi 2 board. endchoice @@ -35,4 +40,3 @@ endchoice # Board dependent configure # - diff --git a/arch/arm/plat-s5p4418/Makefile b/arch/arm/plat-s5p4418/Makefile index 668ee8337a0..8f669c95554 100644 --- a/arch/arm/plat-s5p4418/Makefile +++ b/arch/arm/plat-s5p4418/Makefile @@ -19,6 +19,10 @@ ifeq ($(CONFIG_PLAT_S5P4418_LEPUS),y) PLATBOARD :=lepus endif +ifeq ($(CONFIG_PLAT_S5P4418_NANOPI2),y) +PLATBOARD := nanopi2 +endif + # # Build options # @@ -32,5 +36,3 @@ KBUILD_CFLAGS += -I$(srctree)/$(platdirs)common \ KBUILD_CPPFLAGS += -I$(srctree)/$(platdirs)common \ -I$(srctree)/$(platdirs)$(PLATBOARD)/include - - diff --git a/arch/arm/plat-s5p4418/nanopi2/Makefile b/arch/arm/plat-s5p4418/nanopi2/Makefile new file mode 100644 index 00000000000..d553443b092 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2009 Nexell Co. +# +# Makefile for the S5P4418 + +obj-y := board.o device.o +obj-$(CONFIG_SUSPEND) += pm.o +obj-$(CONFIG_ION_NXP) += dev-ion.o +obj-$(CONFIG_USB_CONNECT_NXP_DRV) += usb-connector.o + diff --git a/arch/arm/plat-s5p4418/nanopi2/board.c b/arch/arm/plat-s5p4418/nanopi2/board.c new file mode 100644 index 00000000000..f5b78b596a6 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/board.c @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2009 + * jung hyun kim, Nexell Co, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include + +/* debug macro */ +#define DBGOUT(msg...) { printk(KERN_INFO msg); } + +/*------------------------------------------------------------------------------ + * set nexell soc pad func. + */ +static void set_gpio_strenth(U32 Group, U32 BitNumber, U32 mA) +{ + U32 drv1=0, drv0=0; + U32 drv1_value, drv0_value; + + switch( mA ) + { + case 0 : drv0 = 0; drv1 = 0; break; + case 1 : drv0 = 0; drv1 = 1; break; + case 2 : drv0 = 1; drv1 = 0; break; + case 3 : drv0 = 1; drv1 = 1; break; + default: drv0 = 0; drv1 = 0; break; + } + + drv1_value = NX_GPIO_GetDRV1(Group) & ~(1 << BitNumber); + drv0_value = NX_GPIO_GetDRV0(Group) & ~(1 << BitNumber); + if (drv1) drv1_value |= (drv1 << BitNumber); + if (drv0) drv0_value |= (drv0 << BitNumber); + + NX_GPIO_SetDRV0 ( Group, drv0_value ); + NX_GPIO_SetDRV1 ( Group, drv1_value ); +} + +static void bd_gpio_init(void) +{ + int index, bit; + int mode, func, out, lv, plup, stren; + U32 gpio; + + const U32 pads[NUMBER_OF_GPIO_MODULE][32] = { + { /* GPIO_A */ + PAD_GPIOA0 , PAD_GPIOA1 , PAD_GPIOA2 , PAD_GPIOA3 , PAD_GPIOA4 , PAD_GPIOA5 , PAD_GPIOA6 , PAD_GPIOA7 , PAD_GPIOA8 , PAD_GPIOA9 , + PAD_GPIOA10, PAD_GPIOA11, PAD_GPIOA12, PAD_GPIOA13, PAD_GPIOA14, PAD_GPIOA15, PAD_GPIOA16, PAD_GPIOA17, PAD_GPIOA18, PAD_GPIOA19, + PAD_GPIOA20, PAD_GPIOA21, PAD_GPIOA22, PAD_GPIOA23, PAD_GPIOA24, PAD_GPIOA25, PAD_GPIOA26, PAD_GPIOA27, PAD_GPIOA28, PAD_GPIOA29, + PAD_GPIOA30, PAD_GPIOA31 + }, { /* GPIO_B */ + PAD_GPIOB0 , PAD_GPIOB1 , PAD_GPIOB2 , PAD_GPIOB3 , PAD_GPIOB4 , PAD_GPIOB5 , PAD_GPIOB6 , PAD_GPIOB7 , PAD_GPIOB8 , PAD_GPIOB9 , + PAD_GPIOB10, PAD_GPIOB11, PAD_GPIOB12, PAD_GPIOB13, PAD_GPIOB14, PAD_GPIOB15, PAD_GPIOB16, PAD_GPIOB17, PAD_GPIOB18, PAD_GPIOB19, + PAD_GPIOB20, PAD_GPIOB21, PAD_GPIOB22, PAD_GPIOB23, PAD_GPIOB24, PAD_GPIOB25, PAD_GPIOB26, PAD_GPIOB27, PAD_GPIOB28, PAD_GPIOB29, + PAD_GPIOB30, PAD_GPIOB31 + }, { /* GPIO_C */ + PAD_GPIOC0 , PAD_GPIOC1 , PAD_GPIOC2 , PAD_GPIOC3 , PAD_GPIOC4 , PAD_GPIOC5 , PAD_GPIOC6 , PAD_GPIOC7 , PAD_GPIOC8 , PAD_GPIOC9 , + PAD_GPIOC10, PAD_GPIOC11, PAD_GPIOC12, PAD_GPIOC13, PAD_GPIOC14, PAD_GPIOC15, PAD_GPIOC16, PAD_GPIOC17, PAD_GPIOC18, PAD_GPIOC19, + PAD_GPIOC20, PAD_GPIOC21, PAD_GPIOC22, PAD_GPIOC23, PAD_GPIOC24, PAD_GPIOC25, PAD_GPIOC26, PAD_GPIOC27, PAD_GPIOC28, PAD_GPIOC29, + PAD_GPIOC30, PAD_GPIOC31 + }, { /* GPIO_D */ + PAD_GPIOD0 , PAD_GPIOD1 , PAD_GPIOD2 , PAD_GPIOD3 , PAD_GPIOD4 , PAD_GPIOD5 , PAD_GPIOD6 , PAD_GPIOD7 , PAD_GPIOD8 , PAD_GPIOD9 , + PAD_GPIOD10, PAD_GPIOD11, PAD_GPIOD12, PAD_GPIOD13, PAD_GPIOD14, PAD_GPIOD15, PAD_GPIOD16, PAD_GPIOD17, PAD_GPIOD18, PAD_GPIOD19, + PAD_GPIOD20, PAD_GPIOD21, PAD_GPIOD22, PAD_GPIOD23, PAD_GPIOD24, PAD_GPIOD25, PAD_GPIOD26, PAD_GPIOD27, PAD_GPIOD28, PAD_GPIOD29, + PAD_GPIOD30, PAD_GPIOD31 + }, { /* GPIO_E */ + PAD_GPIOE0 , PAD_GPIOE1 , PAD_GPIOE2 , PAD_GPIOE3 , PAD_GPIOE4 , PAD_GPIOE5 , PAD_GPIOE6 , PAD_GPIOE7 , PAD_GPIOE8 , PAD_GPIOE9 , + PAD_GPIOE10, PAD_GPIOE11, PAD_GPIOE12, PAD_GPIOE13, PAD_GPIOE14, PAD_GPIOE15, PAD_GPIOE16, PAD_GPIOE17, PAD_GPIOE18, PAD_GPIOE19, + PAD_GPIOE20, PAD_GPIOE21, PAD_GPIOE22, PAD_GPIOE23, PAD_GPIOE24, PAD_GPIOE25, PAD_GPIOE26, PAD_GPIOE27, PAD_GPIOE28, PAD_GPIOE29, + PAD_GPIOE30, PAD_GPIOE31 + }, + }; + + /* GPIO pad function */ + for (index = 0; NUMBER_OF_GPIO_MODULE > index; index++) { + + NX_GPIO_ClearInterruptPendingAll(index); + + for (bit = 0; 32 > bit; bit++) { + gpio = pads[index][bit]; + func = PAD_GET_FUNC(gpio); + mode = PAD_GET_MODE(gpio); + lv = PAD_GET_LEVEL(gpio); + stren = PAD_GET_STRENGTH(gpio); + plup = PAD_GET_PULLUP(gpio); + + /* get pad alternate function (0,1,2,4) */ + switch (func) { + case PAD_GET_FUNC(PAD_FUNC_ALT0): func = NX_GPIO_PADFUNC_0; break; + case PAD_GET_FUNC(PAD_FUNC_ALT1): func = NX_GPIO_PADFUNC_1; break; + case PAD_GET_FUNC(PAD_FUNC_ALT2): func = NX_GPIO_PADFUNC_2; break; + case PAD_GET_FUNC(PAD_FUNC_ALT3): func = NX_GPIO_PADFUNC_3; break; + default: printk("ERROR, unknown alt func (%d.%02d=%d)\n", index, bit, func); + continue; + } + + switch (mode) { + case PAD_GET_MODE(PAD_MODE_ALT): out = 0; + case PAD_GET_MODE(PAD_MODE_IN ): out = 0; + case PAD_GET_MODE(PAD_MODE_INT): out = 0; break; + case PAD_GET_MODE(PAD_MODE_OUT): out = 1; break; + default: printk("ERROR, unknown io mode (%d.%02d=%d)\n", index, bit, mode); + continue; + } + + NX_GPIO_SetPadFunction(index, bit, func); + NX_GPIO_SetOutputEnable(index, bit, (out ? CTRUE : CFALSE)); + NX_GPIO_SetOutputValue(index, bit, (lv ? CTRUE : CFALSE)); + NX_GPIO_SetInterruptMode(index, bit, (lv)); + + NX_GPIO_SetPullMode(index, bit, plup); + set_gpio_strenth(index, bit, stren); /* pad strength */ + } + + NX_GPIO_SetDRV0_DISABLE_DEFAULT(index, 0xFFFFFFFF); + NX_GPIO_SetDRV1_DISABLE_DEFAULT(index, 0xFFFFFFFF); + } +} + +static void bd_alive_init(void) +{ + int index, bit; + int mode, out, lv, plup, detect; + U32 gpio; + + const U32 pads[] = { + PAD_GPIOALV0, PAD_GPIOALV1, PAD_GPIOALV2, + PAD_GPIOALV3, PAD_GPIOALV4, PAD_GPIOALV5 + }; + + index = sizeof(pads)/sizeof(pads[0]); + + /* Alive pad function */ + for (bit = 0; index > bit; bit++) { + NX_ALIVE_ClearInterruptPending(bit); + gpio = pads[bit]; + mode = PAD_GET_MODE(gpio); + lv = PAD_GET_LEVEL(gpio); + plup = PAD_GET_PULLUP(gpio); + + switch (mode) { + case PAD_GET_MODE(PAD_MODE_IN ): + case PAD_GET_MODE(PAD_MODE_INT): out = 0; break; + case PAD_GET_MODE(PAD_MODE_OUT): out = 1; break; + case PAD_GET_MODE(PAD_MODE_ALT): + printk("ERROR, alive.%d not support alt function\n", bit); + continue; + default : + printk("ERROR, unknown alive mode (%d=%d)\n", bit, mode); + continue; + } + + NX_ALIVE_SetOutputEnable(bit, (out ? CTRUE : CFALSE)); + NX_ALIVE_SetOutputValue (bit, (lv)); + NX_ALIVE_SetPullUpEnable(bit, (plup & 1 ? CTRUE : CFALSE)); + /* set interrupt mode */ + for (detect = 0; 6 > detect; detect++) { + if (mode == PAD_GET_MODE(PAD_MODE_INT)) + NX_ALIVE_SetDetectMode(detect, bit, (lv == detect ? CTRUE : CFALSE)); + else + NX_ALIVE_SetDetectMode(detect, bit, CFALSE); + } + NX_ALIVE_SetDetectEnable(bit, (mode == PAD_MODE_INT ? CTRUE : CFALSE)); + } +} + +/*------------------------------------------------------------------------------ + * board interface + */ +static int g_initGpio = 1; +void nxp_board_base_init(void) +{ + if (g_initGpio) + { + bd_gpio_init(); + bd_alive_init(); + DBGOUT("%s : done board initialize ...\n", CFG_SYS_BOARD_NAME); + + g_initGpio = 0; + } +} + +#if defined (CONFIG_INITRAMFS_SOURCE) && defined (CONFIG_DEVTMPFS_MOUNT) +#include +static int __init devtmpfs_init(void) +{ + char *rdsrc = CONFIG_INITRAMFS_SOURCE; + if (!strcmp(rdsrc, "")) + return 0; + + printk("Mount : devtmpfs\n"); + devtmpfs_mount("dev"); + return 0; +} +late_initcall(devtmpfs_init); +#endif diff --git a/arch/arm/plat-s5p4418/nanopi2/dev-ion.c b/arch/arm/plat-s5p4418/nanopi2/dev-ion.c new file mode 100644 index 00000000000..78d82ef7fc8 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/dev-ion.c @@ -0,0 +1,30 @@ +#include +#include +#include +#include +#include +#include + +/* platform device is defined in mach/device.c */ +extern struct platform_device nxp_device_ion; + +void __init nxp_ion_set_platdata(void) +{ + struct ion_platform_data *pdata; + pdata = kzalloc(sizeof(struct ion_platform_data), GFP_KERNEL); + pdata->heaps = kzalloc(5 * sizeof(struct ion_platform_heap), GFP_KERNEL); + + if (pdata) { + pdata->nr = 3; + pdata->heaps[0].type = ION_HEAP_TYPE_SYSTEM; + pdata->heaps[0].name = "ion_noncontig_heap"; + pdata->heaps[0].id = ION_HEAP_TYPE_SYSTEM; + pdata->heaps[1].type = ION_HEAP_TYPE_SYSTEM_CONTIG; + pdata->heaps[1].name = "ion_contig_heap"; + pdata->heaps[1].id = ION_HEAP_TYPE_SYSTEM_CONTIG; + pdata->heaps[2].type = ION_HEAP_TYPE_NXP_CONTIG; + pdata->heaps[2].name = "nxp_contig_heap"; + pdata->heaps[2].id = ION_HEAP_TYPE_NXP_CONTIG; + nxp_device_ion.dev.platform_data = pdata; + } +} diff --git a/arch/arm/plat-s5p4418/nanopi2/device.c b/arch/arm/plat-s5p4418/nanopi2/device.c new file mode 100644 index 00000000000..ed639f45450 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/device.c @@ -0,0 +1,1222 @@ +/* + * (C) Copyright 2009 + * jung hyun kim, Nexell Co, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include + +/* nexell soc headers */ +#include +#include +#include + +#if defined(CONFIG_NXP_HDMI_CEC) +#include +#endif + +/*------------------------------------------------------------------------------ + * BUS Configure + */ +#if (CFG_BUS_RECONFIG_ENB == 1) +#include + +const u8 g_DrexBRB_RD[2] = { + 0x1, // Port0 + 0xF // Port1 +}; + +const u8 g_DrexBRB_WR[2] = { + 0x1, // Port0 + 0xF // Port1 +}; + +const u16 g_DrexQoS[2] = { + 0x100, // S0 + 0xFFF // S1, Default value +}; + + +#if (CFG_BUS_RECONFIG_TOPBUSSI == 1) +const u8 g_TopBusSI[8] = { + TOPBUS_SI_SLOT_DMAC0, + TOPBUS_SI_SLOT_USBOTG, + TOPBUS_SI_SLOT_USBHOST0, + TOPBUS_SI_SLOT_DMAC1, + TOPBUS_SI_SLOT_SDMMC, + TOPBUS_SI_SLOT_USBOTG, + TOPBUS_SI_SLOT_USBHOST1, + TOPBUS_SI_SLOT_USBOTG +}; +#endif + +#if (CFG_BUS_RECONFIG_TOPBUSQOS == 1) +const u8 g_TopQoSSI[2] = { + 1, // Tidemark + (1< + +static struct resource dm9000_resource[] = { + [0] = { + .start = CFG_ETHER_EXT_PHY_BASEADDR, + .end = CFG_ETHER_EXT_PHY_BASEADDR + 1, // 1 (8/16 BIT) + .flags = IORESOURCE_MEM + }, + [1] = { + .start = CFG_ETHER_EXT_PHY_BASEADDR + 4, // + 4 (8/16 BIT) + .end = CFG_ETHER_EXT_PHY_BASEADDR + 5, // + 5 (8/16 BIT) + .flags = IORESOURCE_MEM + }, + [2] = { + .start = CFG_ETHER_EXT_IRQ_NUM, + .end = CFG_ETHER_EXT_IRQ_NUM, + .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, + } +}; + +static struct dm9000_plat_data eth_plat_data = { + .flags = DM9000_PLATF_8BITONLY, // DM9000_PLATF_16BITONLY +}; + +static struct platform_device dm9000_plat_device = { + .name = "dm9000", + .id = 0, + .num_resources = ARRAY_SIZE(dm9000_resource), + .resource = dm9000_resource, + .dev = { + .platform_data = ð_plat_data, + } +}; +#endif /* CONFIG_DM9000 || CONFIG_DM9000_MODULE */ + +/*------------------------------------------------------------------------------ + * DISPLAY (LVDS) / FB + */ +#if defined (CONFIG_FB_NXP) +#if defined (CONFIG_FB0_NXP) +static struct nxp_fb_plat_data fb0_plat_data = { + .module = CONFIG_FB0_NXP_DISPOUT, + .layer = CFG_DISP_PRI_SCREEN_LAYER, + .format = CFG_DISP_PRI_SCREEN_RGB_FORMAT, + .bgcolor = CFG_DISP_PRI_BACK_GROUND_COLOR, + .bitperpixel = CFG_DISP_PRI_SCREEN_PIXEL_BYTE * 8, + .x_resol = CFG_DISP_PRI_RESOL_WIDTH, + .y_resol = CFG_DISP_PRI_RESOL_HEIGHT, + #ifdef CONFIG_ANDROID + .buffers = 3, + .skip_pan_vsync = 1, + #else + .buffers = 2, + #endif + .lcd_with_mm = CFG_DISP_PRI_LCD_WIDTH_MM, /* 152.4 */ + .lcd_height_mm = CFG_DISP_PRI_LCD_HEIGHT_MM, /* 91.44 */ +}; + +static struct platform_device fb0_device = { + .name = DEV_NAME_FB, + .id = 0, /* FB device node num */ + .dev = { + .coherent_dma_mask = 0xffffffffUL, /* for DMA allocate */ + .platform_data = &fb0_plat_data + }, +}; +#endif + +static struct platform_device *fb_devices[] = { + #if defined (CONFIG_FB0_NXP) + &fb0_device, + #endif +}; +#endif /* CONFIG_FB_NXP */ + +/*------------------------------------------------------------------------------ + * backlight : generic pwm device + */ +#if defined(CONFIG_BACKLIGHT_PWM) +#include + +static struct platform_pwm_backlight_data bl_plat_data = { + .pwm_id = CFG_LCD_PRI_PWM_CH, + .max_brightness = 400, /* 255 is 100%, set over 100% */ + .dft_brightness = 128, /* 50% */ + .pwm_period_ns = 1000000000/CFG_LCD_PRI_PWM_FREQ, +}; + +static struct platform_device bl_plat_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &bl_plat_data, + }, +}; + +#endif + +/*------------------------------------------------------------------------------ + * NAND device + */ +#if defined(CONFIG_MTD_NAND_NXP) +#include +#include + +static struct mtd_partition nxp_nand_parts[] = { +#if 0 + { + .name = "root", + .offset = 0 * SZ_1M, + }, +#else + { + .name = "system", + .offset = 64 * SZ_1M, + .size = 512 * SZ_1M, + }, { + .name = "cache", + .offset = MTDPART_OFS_APPEND, + .size = 256 * SZ_1M, + }, { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + } +#endif +}; + +static struct nxp_nand_plat_data nand_plat_data = { + .parts = nxp_nand_parts, + .nr_parts = ARRAY_SIZE(nxp_nand_parts), + .chip_delay = 10, +}; + +static struct platform_device nand_plat_device = { + .name = DEV_NAME_NAND, + .id = -1, + .dev = { + .platform_data = &nand_plat_data, + }, +}; +#endif /* CONFIG_MTD_NAND_NXP */ + +#if defined(CONFIG_TOUCHSCREEN_GSLX680) +#include +#define GSLX680_I2C_BUS (1) + +static struct i2c_board_info __initdata gslX680_i2c_bdi = { + .type = "gslX680", + .addr = (0x40), + .irq = PB_PIO_IRQ(CFG_IO_TOUCH_PENDOWN_DETECT), +}; +#endif + + +/*------------------------------------------------------------------------------ + * Keypad platform device + */ +#if defined(CONFIG_KEYBOARD_NXP_KEY) || defined(CONFIG_KEYBOARD_NXP_KEY_MODULE) + +#include + +static unsigned int button_gpio[] = CFG_KEYPAD_KEY_BUTTON; +static unsigned int button_code[] = CFG_KEYPAD_KEY_CODE; + +struct nxp_key_plat_data key_plat_data = { + .bt_count = ARRAY_SIZE(button_gpio), + .bt_io = button_gpio, + .bt_code = button_code, + .bt_repeat = CFG_KEYPAD_REPEAT, +}; + +static struct platform_device key_plat_device = { + .name = DEV_NAME_KEYPAD, + .id = -1, + .dev = { + .platform_data = &key_plat_data + }, +}; +#endif /* CONFIG_KEYBOARD_NXP_KEY || CONFIG_KEYBOARD_NXP_KEY_MODULE */ + +/*------------------------------------------------------------------------------ + * ASoC Codec platform device + */ +#if defined(CONFIG_SND_SPDIF_TRANSCIEVER) || defined(CONFIG_SND_SPDIF_TRANSCIEVER_MODULE) +static struct platform_device spdif_transciever = { + .name = "spdif-dit", + .id = -1, +}; + +struct nxp_snd_dai_plat_data spdif_trans_dai_data = { + .sample_rate = 48000, + .pcm_format = SNDRV_PCM_FMTBIT_S16_LE, +}; + +static struct platform_device spdif_trans_dai = { + .name = "spdif-transciever", + .id = -1, + .dev = { + .platform_data = &spdif_trans_dai_data, + } +}; +#endif + +#if defined(CONFIG_SND_CODEC_ES8316) || defined(CONFIG_SND_CODEC_ES8316_MODULE) +#include + +#define ES8316_I2C_BUS (0) + +/* CODEC */ +static struct i2c_board_info __initdata es8316_i2c_bdi = { + .type = "es8316", + .addr = (0x22>>1), // 0x11 (7BIT), 0x22(8BIT) +}; + +/* DAI */ +struct nxp_snd_dai_plat_data i2s_dai_data = { + .i2s_ch = 0, + .sample_rate = 48000, + .pcm_format = SNDRV_PCM_FMTBIT_S16_LE, +#if 1 + .hp_jack = { + .support = 1, + .detect_io = PAD_GPIO_B + 27, + .detect_level = 1, + }, +#endif +}; + +static struct platform_device es8316_dai = { + .name = "es8316-audio", + .id = 0, + .dev = { + .platform_data = &i2s_dai_data, + } +}; +#endif + + +/*------------------------------------------------------------------------------ + * G-Sensor platform device + */ +#if defined(CONFIG_SENSORS_MMA865X) || defined(CONFIG_SENSORS_MMA865X_MODULE) +#include + +#define MMA865X_I2C_BUS (2) + +/* CODEC */ +static struct i2c_board_info __initdata mma865x_i2c_bdi = { + .type = "mma8653", + .addr = 0x1D//(0x3a), +}; + +#endif + +#if defined(CONFIG_SENSORS_STK831X) || defined(CONFIG_SENSORS_STK831X_MODULE) +#include + +#define STK831X_I2C_BUS (2) + +/* CODEC */ +static struct i2c_board_info __initdata stk831x_i2c_bdi = { +#if defined CONFIG_SENSORS_STK8312 + .type = "stk8312", + .addr = (0x3d), +#elif defined CONFIG_SENSORS_STK8313 + .type = "stk8313", + .addr = (0x22), +#endif +}; + +#endif + +/*------------------------------------------------------------------------------ + * * reserve mem + * */ +#ifdef CONFIG_CMA +#include +extern void nxp_cma_region_reserve(struct cma_region *, const char *); + +void __init nxp_reserve_mem(void) +{ + static struct cma_region regions[] = { + { + .name = "ion", +#ifdef CONFIG_ION_NXP_CONTIGHEAP_SIZE + .size = CONFIG_ION_NXP_CONTIGHEAP_SIZE * SZ_1K, +#else + .size = 0, +#endif + { + .alignment = PAGE_SIZE, + } + }, + { + .size = 0 + } + }; + + static const char map[] __initconst = + "ion-nxp=ion;" + "nx_vpu=ion;"; + +#ifdef CONFIG_ION_NXP_CONTIGHEAP_SIZE + printk("%s: reserve CMA: size %d\n", __func__, CONFIG_ION_NXP_CONTIGHEAP_SIZE * SZ_1K); +#endif + nxp_cma_region_reserve(regions, map); +} +#endif + +#if defined(CONFIG_I2C_NXP) || defined (CONFIG_I2C_SLSI) +#define I2CUDELAY(x) 1000000/x +/* gpio i2c 3 */ +#define I2C3_SCL PAD_GPIO_D + 20 +#define I2C3_SDA PAD_GPIO_D + 16 + +static struct i2c_gpio_platform_data nxp_i2c_gpio_port3 = { + .sda_pin = I2C3_SDA, + .scl_pin = I2C3_SCL, + .udelay = I2CUDELAY(CFG_I2C3_CLK), /* Gpio_mode CLK Rate = 1/( udelay*2) * 1000000 */ + + .timeout = 10, +}; + + +static struct platform_device i2c_device_ch3 = { + .name = "i2c-gpio", + .id = 3, + .dev = { + .platform_data = &nxp_i2c_gpio_port3, + }, +}; + +static struct platform_device *i2c_devices[] = { + &i2c_device_ch3, +}; +#endif /* CONFIG_I2C_NXP || CONFIG_I2C_SLSI */ + +/*------------------------------------------------------------------------------ + * v4l2 platform device + */ +#if defined(CONFIG_V4L2_NXP) || defined(CONFIG_V4L2_NXP_MODULE) +#include +#include +#include +#include +#include + +static int camera_common_set_clock(ulong clk_rate) +{ + PM_DBGOUT("%s: %d\n", __func__, (int)clk_rate); + if (clk_rate > 0) + nxp_soc_pwm_set_frequency(1, clk_rate, 50); + else + nxp_soc_pwm_set_frequency(1, 0, 0); + msleep(1); + return 0; +} + +static bool is_camera_port_configured = false; +static void camera_common_vin_setup_io(int module, bool force) +{ + if (!force && is_camera_port_configured) + return; + else { + u_int *pad; + int i, len; + u_int io, fn; + + + /* VIP0:0 = VCLK, VID0 ~ 7 */ + const u_int port[][2] = { +#if 0 + /* VCLK, HSYNC, VSYNC */ + { PAD_GPIO_E + 4, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_E + 5, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_E + 6, NX_GPIO_PADFUNC_1 }, + /* DATA */ + { PAD_GPIO_D + 28, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_D + 29, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_D + 30, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_D + 31, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_E + 0, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_E + 1, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_E + 2, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_E + 3, NX_GPIO_PADFUNC_1 }, +#endif + /* VCLK, HSYNC, VSYNC */ + { PAD_GPIO_A + 28, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_E + 13, NX_GPIO_PADFUNC_2 }, + { PAD_GPIO_E + 7, NX_GPIO_PADFUNC_2 }, + + { PAD_GPIO_A + 30, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_B + 0, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_B + 2, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_B + 4, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_B + 6, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_B + 8, NX_GPIO_PADFUNC_1 }, + { PAD_GPIO_B + 9, NX_GPIO_PADFUNC_1 }, { PAD_GPIO_B + 10, NX_GPIO_PADFUNC_1 }, + }; + + printk("%s\n", __func__); + + pad = (u_int *)port; + len = sizeof(port)/sizeof(port[0]); + + for (i = 0; i < len; i++) { + io = *pad++; + fn = *pad++; + nxp_soc_gpio_set_io_dir(io, 0); + nxp_soc_gpio_set_io_func(io, fn); + } + + is_camera_port_configured = true; + } +} + +static bool camera_power_enabled = false; +// fix for dronel +#if 0 +static void camera_power_control(int enable) +{ + struct regulator *cam_io_28V = NULL; + struct regulator *cam_core_18V = NULL; + struct regulator *cam_io_33V = NULL; + + if (enable && camera_power_enabled) + return; + if (!enable && !camera_power_enabled) + return; + + cam_core_18V = regulator_get(NULL, "vcam1_1.8V"); + if (IS_ERR(cam_core_18V)) { + printk(KERN_ERR "%s: failed to regulator_get() for vcam1_1.8V", __func__); + return; + } + + cam_io_28V = regulator_get(NULL, "vcam_2.8V"); + if (IS_ERR(cam_io_28V)) { + printk(KERN_ERR "%s: failed to regulator_get() for vcam_2.8V", __func__); + return; + } + + cam_io_33V = regulator_get(NULL, "vcam_3.3V"); + if (IS_ERR(cam_io_33V)) { + printk(KERN_ERR "%s: failed to regulator_get() for vcam_3.3V", __func__); + return; + } + + printk("%s: %d\n", __func__, enable); + if (enable) { + regulator_enable(cam_core_18V); + regulator_enable(cam_io_28V); + regulator_enable(cam_io_33V); + } else { + regulator_disable(cam_io_33V); + regulator_disable(cam_io_28V); + regulator_disable(cam_core_18V); + } + + regulator_put(cam_io_28V); + regulator_put(cam_core_18V); + regulator_put(cam_io_33V); + + camera_power_enabled = enable ? true : false; +} +#else +static void camera_power_control(int enable) +{ + struct regulator *cam_core_18V = NULL; + + if (enable && camera_power_enabled) + return; + if (!enable && !camera_power_enabled) + return; + + cam_core_18V = regulator_get(NULL, "vcam1_1.8V"); + if (IS_ERR(cam_core_18V)) { + printk(KERN_ERR "%s: failed to regulator_get() for vcam1_1.8V", __func__); + return; + } + printk("%s: %d\n", __func__, enable); + if (enable) { + regulator_enable(cam_core_18V); + } else { + regulator_disable(cam_core_18V); + } + + regulator_put(cam_core_18V); + + camera_power_enabled = enable ? true : false; +} +#endif + +static bool is_back_camera_enabled = false; +static bool is_back_camera_power_state_changed = false; +static bool is_front_camera_enabled = false; +static bool is_front_camera_power_state_changed = false; + +static int front_camera_power_enable(bool on); +static int back_camera_power_enable(bool on) +{ + unsigned int io = CFG_IO_CAMERA_BACK_POWER_DOWN; + unsigned int reset_io = CFG_IO_CAMERA_RESET; + PM_DBGOUT("%s: is_back_camera_enabled %d, on %d\n", __func__, is_back_camera_enabled, on); + if (on) { + front_camera_power_enable(0); + if (!is_back_camera_enabled) { + camera_power_control(1); + /* PD signal */ + nxp_soc_gpio_set_out_value(io, 0); + nxp_soc_gpio_set_io_dir(io, 1); + nxp_soc_gpio_set_io_func(io, nxp_soc_gpio_get_altnum(io)); + nxp_soc_gpio_set_out_value(io, 1); + camera_common_set_clock(24000000); + /* mdelay(10); */ + mdelay(1); + nxp_soc_gpio_set_out_value(io, 0); + /* RST signal */ + nxp_soc_gpio_set_out_value(reset_io, 1); + nxp_soc_gpio_set_io_dir(reset_io, 1); + nxp_soc_gpio_set_io_func(reset_io, nxp_soc_gpio_get_altnum(io)); + nxp_soc_gpio_set_out_value(reset_io, 0); + /* mdelay(100); */ + mdelay(1); + nxp_soc_gpio_set_out_value(reset_io, 1); + /* mdelay(100); */ + mdelay(1); + is_back_camera_enabled = true; + is_back_camera_power_state_changed = true; + } else { + is_back_camera_power_state_changed = false; + } + } else { + if (is_back_camera_enabled) { + nxp_soc_gpio_set_out_value(io, 1); + nxp_soc_gpio_set_out_value(reset_io, 0); + is_back_camera_enabled = false; + is_back_camera_power_state_changed = true; + } else { + nxp_soc_gpio_set_out_value(io, 1); + nxp_soc_gpio_set_io_dir(io, 1); + nxp_soc_gpio_set_io_func(io, nxp_soc_gpio_get_altnum(io)); + nxp_soc_gpio_set_out_value(io, 1); + is_back_camera_power_state_changed = false; + } + + if (!(is_back_camera_enabled || is_front_camera_enabled)) { + camera_power_control(0); + } + } + + return 0; +} + +static bool back_camera_power_state_changed(void) +{ + return is_back_camera_power_state_changed; +} + +static struct i2c_board_info back_camera_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("SP2518", 0x60>>1), + }, +}; + +static int front_camera_power_enable(bool on) +{ + unsigned int io = CFG_IO_CAMERA_FRONT_POWER_DOWN; + unsigned int reset_io = CFG_IO_CAMERA_RESET; + PM_DBGOUT("%s: is_front_camera_enabled %d, on %d\n", __func__, is_front_camera_enabled, on); + if (on) { + back_camera_power_enable(0); + if (!is_front_camera_enabled) { + camera_power_control(1); + /* First RST signal to low */ + nxp_soc_gpio_set_out_value(reset_io, 1); + nxp_soc_gpio_set_io_dir(reset_io, 1); + nxp_soc_gpio_set_io_func(reset_io, nxp_soc_gpio_get_altnum(io)); + nxp_soc_gpio_set_out_value(reset_io, 0); + mdelay(1); + + /* PWDN signal High to Low */ + nxp_soc_gpio_set_out_value(io, 0); + nxp_soc_gpio_set_io_dir(io, 1); + nxp_soc_gpio_set_io_func(io, nxp_soc_gpio_get_altnum(io)); + nxp_soc_gpio_set_out_value(io, 1); + camera_common_set_clock(24000000); + mdelay(10); + /* mdelay(1); */ + nxp_soc_gpio_set_out_value(io, 0); + /* mdelay(10); */ + mdelay(10); + + /* RST signal to High */ + nxp_soc_gpio_set_out_value(reset_io, 1); + /* mdelay(100); */ + mdelay(5); + + is_front_camera_enabled = true; + is_front_camera_power_state_changed = true; + } else { + is_front_camera_power_state_changed = false; + } + } else { + if (is_front_camera_enabled) { + nxp_soc_gpio_set_out_value(io, 1); + is_front_camera_enabled = false; + is_front_camera_power_state_changed = true; + } else { + nxp_soc_gpio_set_out_value(io, 1); + is_front_camera_power_state_changed = false; + } + if (!(is_back_camera_enabled || is_front_camera_enabled)) { + camera_power_control(0); + } + } + + return 0; +} + +static bool front_camera_power_state_changed(void) +{ + return is_front_camera_power_state_changed; +} + +static struct i2c_board_info front_camera_i2c_boardinfo[] = { + { + I2C_BOARD_INFO("SP0838", 0x18), + }, +}; + +static struct nxp_v4l2_i2c_board_info sensor[] = { + { + .board_info = &back_camera_i2c_boardinfo[0], + .i2c_adapter_id = 0, + }, + { + .board_info = &front_camera_i2c_boardinfo[0], + .i2c_adapter_id = 0, + }, +}; + + +static struct nxp_capture_platformdata capture_plat_data[] = { + { + /* back_camera 656 interface */ + .module = 0, + .sensor = &sensor[0], + .type = NXP_CAPTURE_INF_PARALLEL, + .parallel = { + /* for 656 */ + .is_mipi = false, + .external_sync = false, /* 656 interface */ + .h_active = 800, + .h_frontporch = 7, + .h_syncwidth = 1, + .h_backporch = 10, + .v_active = 600, + .v_frontporch = 0, + .v_syncwidth = 2, + .v_backporch = 3, + .clock_invert = true, + .port = 0, + .data_order = NXP_VIN_Y0CBY1CR, + .interlace = false, + .clk_rate = 24000000, + .late_power_down = true, + .power_enable = back_camera_power_enable, + .power_state_changed = back_camera_power_state_changed, + .set_clock = camera_common_set_clock, + .setup_io = camera_common_vin_setup_io, + }, + .deci = { + .start_delay_ms = 0, + .stop_delay_ms = 0, + }, + }, + { + /* front_camera 601 interface */ + .module = 0, + .sensor = &sensor[1], + .type = NXP_CAPTURE_INF_PARALLEL, + .parallel = { + .is_mipi = false, + .external_sync = true, + .h_active = 640, + .h_frontporch = 0, + .h_syncwidth = 0, + .h_backporch = 2, + .v_active = 480, + .v_frontporch = 0, + .v_syncwidth = 0, + .v_backporch = 2, + .clock_invert = false, + .port = 0, + .data_order = NXP_VIN_CBY0CRY1, + .interlace = false, + .clk_rate = 24000000, + .late_power_down = true, + .power_enable = front_camera_power_enable, + .power_state_changed = front_camera_power_state_changed, + .set_clock = camera_common_set_clock, + .setup_io = camera_common_vin_setup_io, + }, + .deci = { + .start_delay_ms = 0, + .stop_delay_ms = 0, + }, + }, + { 0, NULL, 0, }, +}; +/* out platformdata */ +static struct i2c_board_info hdmi_edid_i2c_boardinfo = { + I2C_BOARD_INFO("nxp_edid", 0xA0>>1), +}; + +static struct nxp_v4l2_i2c_board_info edid = { + .board_info = &hdmi_edid_i2c_boardinfo, + .i2c_adapter_id = 0, +}; + +static struct i2c_board_info hdmi_hdcp_i2c_boardinfo = { + I2C_BOARD_INFO("nxp_hdcp", 0x74>>1), +}; + +static struct nxp_v4l2_i2c_board_info hdcp = { + .board_info = &hdmi_hdcp_i2c_boardinfo, + .i2c_adapter_id = 0, +}; + + +static void hdmi_set_int_external(int gpio) +{ + nxp_soc_gpio_set_int_enable(gpio, 0); + nxp_soc_gpio_set_int_mode(gpio, 1); /* high level */ + nxp_soc_gpio_set_int_enable(gpio, 1); + nxp_soc_gpio_clr_int_pend(gpio); +} + +static void hdmi_set_int_internal(int gpio) +{ + nxp_soc_gpio_set_int_enable(gpio, 0); + nxp_soc_gpio_set_int_mode(gpio, 0); /* low level */ + nxp_soc_gpio_set_int_enable(gpio, 1); + nxp_soc_gpio_clr_int_pend(gpio); +} + +static int hdmi_read_hpd_gpio(int gpio) +{ + return nxp_soc_gpio_get_in_value(gpio); +} + +static struct nxp_out_platformdata out_plat_data = { + .hdmi = { + .internal_irq = 0, + .external_irq = 0,//PAD_GPIO_A + 19, + .set_int_external = hdmi_set_int_external, + .set_int_internal = hdmi_set_int_internal, + .read_hpd_gpio = hdmi_read_hpd_gpio, + .edid = &edid, + .hdcp = &hdcp, + }, +}; + +static struct nxp_v4l2_platformdata v4l2_plat_data = { + .captures = &capture_plat_data[0], + .out = &out_plat_data, +}; + +static struct platform_device nxp_v4l2_dev = { + .name = NXP_V4L2_DEV_NAME, + .id = 0, + .dev = { + .platform_data = &v4l2_plat_data, + }, +}; +#endif /* CONFIG_V4L2_NXP || CONFIG_V4L2_NXP_MODULE */ + +/*------------------------------------------------------------------------------ + * SSP/SPI + */ +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) +#include +static void spi0_cs(u32 chipselect) +{ +#if (CFG_SPI0_CS_GPIO_MODE) + if(nxp_soc_gpio_get_io_func( CFG_SPI0_CS )!= nxp_soc_gpio_get_altnum( CFG_SPI0_CS)) + nxp_soc_gpio_set_io_func( CFG_SPI0_CS, nxp_soc_gpio_get_altnum( CFG_SPI0_CS)); + + nxp_soc_gpio_set_io_dir( CFG_SPI0_CS,1); + nxp_soc_gpio_set_out_value( CFG_SPI0_CS , chipselect); +#else + ; +#endif +} +struct pl022_config_chip spi0_info = { + /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */ + .com_mode = CFG_SPI0_COM_MODE, + .iface = SSP_INTERFACE_MOTOROLA_SPI, + /* We can only act as master but SSP_SLAVE is possible in theory */ + .hierarchy = SSP_MASTER, + /* 0 = drive TX even as slave, 1 = do not drive TX as slave */ + .slave_tx_disable = 1, + .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, + .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, + .ctrl_len = SSP_BITS_8, + .wait_state = SSP_MWIRE_WAIT_ZERO, + .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, + /* + * This is where you insert a call to a function to enable CS + * (usually GPIO) for a certain chip. + */ +#if (CFG_SPI0_CS_GPIO_MODE) + .cs_control = spi0_cs, +#endif + .clkdelay = SSP_FEEDBACK_CLK_DELAY_1T, + +}; + +static struct spi_board_info spi_plat_board[] __initdata = { + [0] = { + .modalias = "spidev", /* fixup */ + .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, /* Note> set bus num, must be smaller than ARRAY_SIZE(spi_plat_device) */ + .chip_select = 0, /* Note> set chip select num, must be smaller than spi cs_num */ + .controller_data = &spi0_info, + .mode = SPI_MODE_3 | SPI_CPOL | SPI_CPHA, + }, +}; + +#endif +/*------------------------------------------------------------------------------ + * DW MMC board config + */ +#if defined(CONFIG_MMC_DW) +static int _dwmci_ext_cd_init(void (*notify_func)(struct platform_device *, int state)) +{ + return 0; +} + +static int _dwmci_ext_cd_cleanup(void (*notify_func)(struct platform_device *, int state)) +{ + return 0; +} + +static int _dwmci_get_ro(u32 slot_id) +{ + return 0; +} + +static int _dwmci0_init(u32 slot_id, irq_handler_t handler, void *data) +{ + struct dw_mci *host = (struct dw_mci *)data; + int io = CFG_SDMMC0_DETECT_IO; + int irq = IRQ_GPIO_START + io; + int id = 0, ret = 0; + + printk("dw_mmc dw_mmc.%d: Using external card detect irq %3d (io %2d)\n", id, irq, io); + + ret = request_irq(irq, handler, IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, + DEV_NAME_SDHC "0", (void*)host->slot[slot_id]); + if (0 > ret) + pr_err("dw_mmc dw_mmc.%d: fail request interrupt %d ...\n", id, irq); + return 0; +} +static int _dwmci0_get_cd(u32 slot_id) +{ + int io = CFG_SDMMC0_DETECT_IO; + return nxp_soc_gpio_get_in_value(io); +} +#ifdef CONFIG_MMC_NXP_CH0 +static struct dw_mci_board _dwmci0_data = { + .quirks = DW_MCI_QUIRK_HIGHSPEED, + .bus_hz = 100 * 1000 * 1000, + .caps = MMC_CAP_CMD23, + .detect_delay_ms= 200, + .cd_type = DW_MCI_CD_EXTERNAL, + .clk_dly = DW_MMC_DRIVE_DELAY(0) | DW_MMC_SAMPLE_DELAY(0) | DW_MMC_DRIVE_PHASE(2) | DW_MMC_SAMPLE_PHASE(1), + .init = _dwmci0_init, + .get_ro = _dwmci_get_ro, + .get_cd = _dwmci0_get_cd, + .ext_cd_init = _dwmci_ext_cd_init, + .ext_cd_cleanup = _dwmci_ext_cd_cleanup, +#if defined (CONFIG_MMC_DW_IDMAC) && defined (CONFIG_MMC_NXP_CH0_USE_DMA) + .mode = DMA_MODE, +#else + .mode = PIO_MODE, +#endif +}; +#endif + +#ifdef CONFIG_MMC_NXP_CH1 +static struct dw_mci_board _dwmci1_data = { + .quirks = DW_MCI_QUIRK_HIGHSPEED, + .bus_hz = 100 * 1000 * 1000, + .caps = MMC_CAP_CMD23|MMC_CAP_NONREMOVABLE, + .detect_delay_ms= 200, + .cd_type = DW_MCI_CD_NONE, + .pm_caps = MMC_PM_KEEP_POWER | MMC_PM_IGNORE_PM_NOTIFY, + .clk_dly = DW_MMC_DRIVE_DELAY(0) | DW_MMC_SAMPLE_DELAY(0) | DW_MMC_DRIVE_PHASE(0) | DW_MMC_SAMPLE_PHASE(0), +#if defined (CONFIG_MMC_DW_IDMAC) && defined (CONFIG_MMC_NXP_CH1_USE_DMA) + .mode = DMA_MODE, +#else + .mode = PIO_MODE, +#endif +}; +#endif + +#ifdef CONFIG_MMC_NXP_CH2 +static struct dw_mci_board _dwmci2_data = { + .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION | + DW_MCI_QUIRK_HIGHSPEED | + DW_MMC_QUIRK_HW_RESET_PW | + DW_MCI_QUIRK_NO_DETECT_EBIT, + .bus_hz = 100 * 1000 * 1000, + .caps = MMC_CAP_UHS_DDR50 | + MMC_CAP_NONREMOVABLE | + MMC_CAP_4_BIT_DATA | MMC_CAP_CMD23 | + MMC_CAP_HW_RESET, + .clk_dly = DW_MMC_DRIVE_DELAY(0) | DW_MMC_SAMPLE_DELAY(0) | DW_MMC_DRIVE_PHASE(3) | DW_MMC_SAMPLE_PHASE(2), + + .desc_sz = 4, + .detect_delay_ms= 200, + .sdr_timing = 0x01010001, + .ddr_timing = 0x03030002, +#if defined (CONFIG_MMC_DW_IDMAC) && defined (CONFIG_MMC_NXP_CH2_USE_DMA) + .mode = DMA_MODE, +#else + .mode = PIO_MODE, +#endif +}; +#endif + +#endif /* CONFIG_MMC_DW */ + +/*------------------------------------------------------------------------------ + * RFKILL driver + */ +#if defined(CONFIG_NXP_RFKILL) + +struct rfkill_dev_data rfkill_dev_data = +{ + .supply_name = "vgps_3.3V", // vwifi_3.3V, vgps_3.3V + .module_name = "wlan", + .initval = RFKILL_INIT_SET | RFKILL_INIT_OFF, + .delay_time_off = 1000, +}; + +struct nxp_rfkill_plat_data rfkill_plat_data = { + .name = "WiFi-Rfkill", + .type = RFKILL_TYPE_WLAN, + .rf_dev = &rfkill_dev_data, + .rf_dev_num = 1, +}; + +static struct platform_device rfkill_device = { + .name = DEV_NAME_RFKILL, + .dev = { + .platform_data = &rfkill_plat_data, + } +}; +#endif /* CONFIG_RFKILL_NXP */ + +/*------------------------------------------------------------------------------ + * USB HSIC power control. + */ +int nxp_hsic_phy_pwr_on(struct platform_device *pdev, bool on) +{ + return 0; +} +EXPORT_SYMBOL(nxp_hsic_phy_pwr_on); + +/*------------------------------------------------------------------------------ + * HDMI CEC driver + */ +#if defined(CONFIG_NXP_HDMI_CEC) +static struct platform_device hdmi_cec_device = { + .name = NXP_HDMI_CEC_DRV_NAME, +}; +#endif /* CONFIG_NXP_HDMI_CEC */ + +/*------------------------------------------------------------------------------ + * register board platform devices + */ +void __init nxp_board_devices_register(void) +{ + printk("[Register board platform devices]\n"); + +#if defined(CONFIG_ARM_NXP_CPUFREQ) + printk("plat: add dynamic frequency (pll.%d)\n", dfs_plat_data.pll_dev); + platform_device_register(&dfs_plat_device); +#endif + +#if defined (CONFIG_FB_NXP) + printk("plat: add framebuffer\n"); + platform_add_devices(fb_devices, ARRAY_SIZE(fb_devices)); +#endif + +#if defined(CONFIG_MMC_DW) + #ifdef CONFIG_MMC_NXP_CH0 + nxp_mmc_add_device(0, &_dwmci0_data); + #endif + #ifdef CONFIG_MMC_NXP_CH1 + nxp_mmc_add_device(1, &_dwmci1_data); + #endif + #ifdef CONFIG_MMC_NXP_CH2 + nxp_mmc_add_device(2, &_dwmci2_data); + #endif +#endif + +#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) + printk("plat: add device dm9000 net\n"); + platform_device_register(&dm9000_plat_device); +#endif + +#if defined(CONFIG_BACKLIGHT_PWM) + printk("plat: add backlight pwm device\n"); + platform_device_register(&bl_plat_device); +#endif + +#if defined(CONFIG_MTD_NAND_NXP) + platform_device_register(&nand_plat_device); +#endif + +#if defined(CONFIG_KEYBOARD_NXP_KEY) || defined(CONFIG_KEYBOARD_NXP_KEY_MODULE) + printk("plat: add device keypad\n"); + platform_device_register(&key_plat_device); +#endif + +#if defined(CONFIG_I2C_NXP) || defined (CONFIG_I2C_SLSI) + platform_add_devices(i2c_devices, ARRAY_SIZE(i2c_devices)); +#endif + +#if defined(CONFIG_SND_SPDIF_TRANSCIEVER) || defined(CONFIG_SND_SPDIF_TRANSCIEVER_MODULE) + printk("plat: add device spdif playback\n"); + platform_device_register(&spdif_transciever); + platform_device_register(&spdif_trans_dai); +#endif + +#if defined(CONFIG_SND_CODEC_ES8316) || defined(CONFIG_SND_CODEC_ES8316_MODULE) + printk("plat: add device asoc-es8316\n"); + i2c_register_board_info(ES8316_I2C_BUS, &es8316_i2c_bdi, 1); + platform_device_register(&es8316_dai); +#endif + +#if defined(CONFIG_V4L2_NXP) || defined(CONFIG_V4L2_NXP_MODULE) + printk("plat: add device nxp-v4l2\n"); + platform_device_register(&nxp_v4l2_dev); +#endif + +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + spi_register_board_info(spi_plat_board, ARRAY_SIZE(spi_plat_board)); + printk("plat: register spidev\n"); +#endif + +#if defined(CONFIG_TOUCHSCREEN_GSLX680) + printk("plat: add touch(gslX680) device\n"); + i2c_register_board_info(GSLX680_I2C_BUS, &gslX680_i2c_bdi, 1); +#endif + +#if defined(CONFIG_SENSORS_MMA865X) || defined(CONFIG_SENSORS_MMA865X_MODULE) + printk("plat: add g-sensor mma865x\n"); + i2c_register_board_info(2, &mma865x_i2c_bdi, 1); +#elif defined(CONFIG_SENSORS_MMA7660) || defined(CONFIG_SENSORS_MMA7660_MODULE) + printk("plat: add g-sensor mma7660\n"); + i2c_register_board_info(MMA7660_I2C_BUS, &mma7660_i2c_bdi, 1); +#endif + +#if defined(CONFIG_RFKILL_NXP) + printk("plat: add device rfkill\n"); + platform_device_register(&rfkill_device); +#endif + +#if defined(CONFIG_NXP_HDMI_CEC) + printk("plat: add device hdmi-cec\n"); + platform_device_register(&hdmi_cec_device); +#endif + + /* END */ + printk("\n"); +} diff --git a/arch/arm/plat-s5p4418/nanopi2/include/axp22-cfg.h b/arch/arm/plat-s5p4418/nanopi2/include/axp22-cfg.h new file mode 100644 index 00000000000..e707f94b7df --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/include/axp22-cfg.h @@ -0,0 +1,97 @@ +/* + * (C) Copyright 2015 + * Jongshin Park, Nexell Co, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __AXP228_POWER_H_ +#define __AXP228_POWER_H_ + +/* + * Config Value + */ + +/*i2c channel */ +#define AXP_I2CBUS 3 + +/* interrupt */ +#define AXP_IRQNO CFG_GPIO_PMIC_INTR // 164 + + +/* + * Default Value + */ + +/* DCDC-LDO Name */ +#define AXP_DCDC1_NAME "vdd_sys_3.3V" /* VCC3P3_SYS */ +#define AXP_DCDC2_NAME "vdd_arm_1.3V" /* VCC1P1_ARM */ +#define AXP_DCDC3_NAME "vdd_core_1.2V" /* VCC1P1_ARM(CORE) */ +#define AXP_DCDC4_NAME "vdd_sys_1.6V" /* VCC1P5_SYS */ +#define AXP_DCDC5_NAME "vdd_ddr_1.6V" /* VCC1P5_DDR */ +#define AXP_ALDO1_NAME "valive_3.3V" /* VCC3P3_ALIVE */ +#define AXP_ALDO2_NAME "valive_1.8V" /* VCC1P8_ALIVE */ +#define AXP_ALDO3_NAME "valive_1.0V" /* VCC1P0_ALIVE */ +#define AXP_DLDO1_NAME "vwide_3.3V" /* VCC_WIDE */ +#define AXP_DLDO2_NAME "vcam1_1.8V" /* VCC1P8_CAM */ +#define AXP_DLDO3_NAME "vdumy1_0.7V" /* NC */ +#define AXP_DLDO4_NAME "vdumy2_0.7V" /* NC */ +#define AXP_ELDO1_NAME "vsys1_1.8V" /* VCC1P8_SYS */ +#define AXP_ELDO2_NAME "vwifi_3.3V" /* VCC3P3_WIFI */ +#define AXP_ELDO3_NAME "vdumy3_0.7V" /* NC */ +#define AXP_DC5LDO_NAME "vcvbs_1.2V" /* VCC1P2_CVBS */ + +/* DCDC-LDO Voltage Value */ +#define AXP_DCDC1_VALUE 3300000 /* VCC3P3_SYS DCDC1 : AXP22:1600~3400, 100/setp*/ +#define AXP_DCDC2_VALUE 1125000 /* VCC1P1_ARM DCDC2 : AXP22: 600~1540, 20/step*/ +#define AXP_DCDC3_VALUE 1100000 /* VCC1P0_CORE DCDC3 : AXP22: 600~1860, 20/step*/ +#define AXP_DCDC4_VALUE 1500000 /* VCC1P5_SYS DCDC4 : AXP22: 600~1540, 20/step*/ +#define AXP_DCDC5_VALUE 1500000 /* VCC1P5_DDR DCDC5 : AXP22:1000~2550, 50/step*/ +#define AXP_ALDO1_VALUE 3300000 /* VCC3P3_ALIVE ALDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_ALDO2_VALUE 1800000 /* VCC1P8_ALIVE ALDO2 : AXP22: 700~3300, 100/step*/ +#define AXP_ALDO3_VALUE 1000000 /* VCC1P0_ALIVE ALDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO1_VALUE 3300000 /* VCC_WIDE DLDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO2_VALUE 1800000 /* VCC1P8_CAM DLDO2 : AXP22 : 700~3300, 100/step*/ +#define AXP_DLDO3_VALUE 700000 /* NC DLDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO4_VALUE 700000 /* NC DLDO4 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO1_VALUE 1800000 /* VCC1P8_SYS ELDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO2_VALUE 3300000 /* VCC3P3_WIFI ELDO2 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO3_VALUE 700000 /* NC ELDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DC5LDO_VALUE 1200000 /* VCC1P2_CVBS DC5LDO : AXP22: 700~1400, 100/step*/ + +/* DCDC-LDO Voltage Enable Value */ +#define AXP_DCDC1_ENABLE 1 /* VCC3P3_SYS DCDC1 : AXP22:1600~3400, 100/setp*/ +#define AXP_DCDC2_ENABLE 1 /* VCC1P1_ARM DCDC2 : AXP22: 600~1540, 20/step*/ +#define AXP_DCDC3_ENABLE 1 /* VCC1P0_CORE DCDC3 : AXP22: 600~1860, 20/step*/ +#define AXP_DCDC4_ENABLE 1 /* VCC1P5_SYS DCDC4 : AXP22: 600~1540, 20/step*/ +#define AXP_DCDC5_ENABLE 1 /* VCC1P5_DDR DCDC5 : AXP22:1000~2550, 50/step*/ +#define AXP_ALDO1_ENABLE 1 /* VCC3P3_ALIVE ALDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_ALDO2_ENABLE 1 /* VCC1P8_ALIVE ALDO2 : AXP22: 700~3300, 100/step*/ +#define AXP_ALDO3_ENABLE 1 /* VCC1P0_ALIVE ALDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO1_ENABLE 1 /* VCC_WIDE DLDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO2_ENABLE 0 /* VCC1P8_CAM DLDO2 : AXP22 : 700~3300, 100/step*/ +#define AXP_DLDO3_ENABLE 0 /* NC DLDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DLDO4_ENABLE 0 /* NC DLDO4 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO1_ENABLE 1 /* VCC1P8_SYS ELDO1 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO2_ENABLE 1 /* VCC3P3_WIFI ELDO2 : AXP22: 700~3300, 100/step*/ +#define AXP_ELDO3_ENABLE 0 /* NC ELDO3 : AXP22: 700~3300, 100/step*/ +#define AXP_DC5LDO_ENABLE 0 /* VCC1P2_CVBS DC5LDO : AXP22: 700~1400, 100/step*/ +#define AXP_DC1SW_ENABLE 0 /* NC DC1SW : AXP22: */ + +#endif /* __AXP228_POWER_H_ */ diff --git a/arch/arm/plat-s5p4418/nanopi2/include/cfg_gpio.h b/arch/arm/plat-s5p4418/nanopi2/include/cfg_gpio.h new file mode 100644 index 00000000000..456560a0650 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/include/cfg_gpio.h @@ -0,0 +1,269 @@ +/*------------------------------------------------------------------------------ + * + * Copyright (C) 2009 Nexell Co., Ltd All Rights Reserved + * Nexell Co. Proprietary & Confidential + * + * NEXELL INFORMS THAT THIS CODE AND INFORMATION IS PROVIDED "AS IS" BASE + * AND WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Module : System memory config + * Description: + * Author : Platform Team + * Export : + * History : + * 2009/05/13 first implementation + ------------------------------------------------------------------------------*/ +#ifndef __CFG_GPIO_H__ +#define __CFG_GPIO_H__ + +/*------------------------------------------------------------------------------ + * + * (GROUP_A) + * + * 0 bit 8 bit 12 bit 16 bit 20 bit + * | PAD_MODE_XXX | PAD_FUNC_ALT(0,1,2,3) | PAD_LEVEL_XXX | PAD_PULL_UP,OFF | PAD_STRENGTH_0,1,2,3 + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOA0 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PVCLK ,2:_ ,3: TESTMODE[4] = +#define PAD_GPIOA1 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[0] ,2:_ ,3:_ = +#define PAD_GPIOA2 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[1] ,2:_ ,3: TESTMODE[0] = +#define PAD_GPIOA3 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[2] ,2:_ ,3: TESTMODE[1] = +#define PAD_GPIOA4 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[3] ,2:_ ,3: TESTMODE[2] = +#define PAD_GPIOA5 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[4] ,2:_ ,3: TESTMODE[3] = +#define PAD_GPIOA6 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[5] ,2:_ ,3:_ = +#define PAD_GPIOA7 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[6] ,2:_ ,3:_ = +#define PAD_GPIOA8 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[7] ,2:_ ,3:_ = +#define PAD_GPIOA9 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[8] ,2:_ ,3:_ = +#define PAD_GPIOA10 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[9] ,2:_ ,3:_ = +#define PAD_GPIOA11 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[10] ,2:_ ,3:_ = +#define PAD_GPIOA12 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[11] ,2:_ ,3:_ = +#define PAD_GPIOA13 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[12] ,2:_ ,3:_ = +#define PAD_GPIOA14 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[13] ,2:_ ,3:_ = +#define PAD_GPIOA15 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[14] ,2:_ ,3:_ = +#define PAD_GPIOA16 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[15] ,2:_ ,3:- = +#define PAD_GPIOA17 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[16] ,2:_ ,3:_ = +#define PAD_GPIOA18 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[17] ,2:_ ,3:_ = +#define PAD_GPIOA19 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[18] ,2:_ ,3:_ = +#define PAD_GPIOA20 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[19] ,2:_ ,3:_ = +#define PAD_GPIOA21 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[20] ,2:_ ,3:_ = +#define PAD_GPIOA22 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[21] ,2:_ ,3:_ = +#define PAD_GPIOA23 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[22] ,2:_ ,3:_ = +#define PAD_GPIOA24 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDRGB24[23] ,2:_ ,3:_ = +#define PAD_GPIOA25 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDVSYNC ,2:_ ,3:_ = +#define PAD_GPIOA26 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDHSYNC ,2:_ ,3:_ = +#define PAD_GPIOA27 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PDDE ,2:_ ,3:_ = +#define PAD_GPIOA28 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VP0_EXTCLK ,2: I2S2_CLK ,3: I2S1_CLK = +#define PAD_GPIOA29 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CCLK ,2:_ ,3:_ = +#define PAD_GPIOA30 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[0] ,2: SDEX[0] ,3: I2S1_BCLK = +#define PAD_GPIOA31 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CMD ,2:_ ,3:_ = + +/*------------------------------------------------------------------------------ + * (GROUP_B) + * + * 0 bit 8 bit 12 bit 16 bit 20 bit + * | PAD_MODE_XXX | PAD_FUNC_ALT(0,1,2,3) | PAD_LEVEL_XXX | PAD_PULL_UP,OFF | PAD_STRENGTH_0,1,2,3 + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOB0 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[1] ,2: SDEX[1] ,3: I2S1_LRCLK = +#define PAD_GPIOB1 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CDATA[0] ,2:_ ,3:_ = +#define PAD_GPIOB2 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[2] ,2: SDEX[2] ,3: I2S2_BCLK = +#define PAD_GPIOB3 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CDATA[1] ,2:_ ,3:_ = +#define PAD_GPIOB4 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[3] ,2: SDEX[3] ,3: I2S2_LRCLK = +#define PAD_GPIOB5 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CDATA[2] ,2:_ ,3:_ = +#define PAD_GPIOB6 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[4] ,2: SDEX[4] ,3: I2S1SDO = +#define PAD_GPIOB7 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: SDMMC0_CDATA[3] ,2:_ ,3:_ = +#define PAD_GPIOB8 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[5] ,2: SDEX[5] ,3: I2S2SDO = +#define PAD_GPIOB9 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[6] ,2: SDEX[6] ,3: I2S1SDI = +#define PAD_GPIOB10 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: VIP0_VD[7] ,2: SDEX[7] ,3: I2S2SDI = +#define PAD_GPIOB11 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: CLE ,1: CLE1 ,2: GPIO ,3:_ = +#define PAD_GPIOB12 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: ALE ,1: ALE1 ,2: GPIO ,3:_ = +#define PAD_GPIOB13 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[0] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB14 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_RnB ,1: MCUS_RnB1 ,2: GPIO ,3:_ = +#define PAD_GPIOB15 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[1] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB16 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_nNOFE ,1: MCUS_nNOFE1 ,2: GPIO ,3:_ = +#define PAD_GPIOB17 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[2] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB18 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_nNFWE ,1: MCUS_nNFWE1 ,2: GPIO ,3:_ = +#define PAD_GPIOB19 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[3] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB20 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[4] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB21 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[5] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB22 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[6] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB23 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[7] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOB24 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[8] ,1: GPIO ,2: MPEGTSI0_TDATA[0] ,3:_ = +#define PAD_GPIOB25 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[9] ,1: GPIO ,2: MPEGTSI0_TDATA[1] ,3:_ = +#define PAD_GPIOB26 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[10] ,1: GPIO ,2: MPEGTSI0_TDATA[2] ,3: ECID_BONDING_ID[2] = +#define PAD_GPIOB27 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_HIGH | PAD_PULL_OFF | PAD_STRENGTH_3) // 0: MCUS_SD[11] ,1: GPIO ,2: MPEGTSI0_TDATA[3] ,3:_ = +#define PAD_GPIOB28 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[12] ,1: GPIO ,2: MPEGTSI0_TDATA[4] ,3: UART4_RXD = +#define PAD_GPIOB29 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_UP | PAD_STRENGTH_0) // 0: MCUS_SD[13] ,1: GPIO ,2: MPEGTSI0_TDATA[5] ,3: UART4_TXD = +#define PAD_GPIOB30 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[14] ,1: GPIO ,2: MPEGTSI0_TDATA[6] ,3: UART5_RXD = +#define PAD_GPIOB31 (PAD_MODE_INT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_SD[15] ,1: GPIO ,2: MPEGTSI0_TDATA[7] ,3: UART5_TXD = + +/*------------------------------------------------------------------------------ + * (GROUP_C) + * + * 0 bit 8 bit 12 bit 16 bit 20 bit + * | PAD_MODE_XXX | PAD_FUNC_ALT(0,1,2,3) | PAD_LEVEL_XXX | PAD_PULL_UP,OFF | PAD_STRENGTH_0,1,2,3 + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOC0 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[0] ,1: GPIO ,2: MPEGTSI0_TSERR ,3:_ = +#define PAD_GPIOC1 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[1] ,1: GPIO ,2: MPEGTSI1_TSERR ,3:_ = +#define PAD_GPIOC2 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_ADDR[2] ,1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOC3 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_ADDR[3] ,1: GPIO ,2: HDMI_CEC ,3: SDMMC0_nRST = +#define PAD_GPIOC4 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[4] ,1: GPIO ,2: UART1_DCD ,3: SDMMC0_CARD_nint = +#define PAD_GPIOC5 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[5] ,1: GPIO ,2: UART1_CTS ,3: SDMMC0_WP = +#define PAD_GPIOC6 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[6] ,1: GPIO ,2: UART1_RTS ,3: SDMMC0_DETECT = +#define PAD_GPIOC7 (PAD_MODE_OUT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[7] ,1: GPIO ,2: UART1_DSR ,3: SDMMC1_nRST = +#define PAD_GPIOC8 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[8] ,1: GPIO ,2: UART1_DTR ,3: SDMMC1_CARD_nint = +#define PAD_GPIOC9 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[9] ,1: GPIO ,2: SSP2_CLK_IO ,3: PDM_STROBE = +#define PAD_GPIOC10 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_HIGH | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_ADDR[10] ,1: GPIO ,2: SSP2_FSS ,3: MCUS_nNCS[2] = +#define PAD_GPIOC11 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[11] ,1: GPIO ,2: SSP2_RXD ,3: USB2.0OTG0_DRVBUS = +#define PAD_GPIOC12 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[12] ,1: GPIO ,2: SSP2_TXD ,3: SDMMC2_nRST = +#define PAD_GPIOC13 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_ADDR[13] ,1: GPIO ,2: PWM1_OUT ,3: SDMMC2_CARD_nint = +#define PAD_GPIOC14 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[14] ,1: GPIO ,2: PWM2_OUT ,3: VIP0_ExtCLK2 = +#define PAD_GPIOC15 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[15] ,1: GPIO ,2: MPEGTSI0_TSCLK ,3: VIP0_HSYNC2 = +#define PAD_GPIOC16 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[16] ,1: GPIO ,2: MPEGTSI0_TSYNC0 ,3: VIP0_VSYNC2 = +#define PAD_GPIOC17 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_ADDR[17] ,1: GPIO ,2: MPEGTSI0_TDP0 ,3: VIP0_VD2[0] = +#define PAD_GPIOC18 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_UP | PAD_STRENGTH_2) // 0: MCUS_ADDR[18] ,1: GPIO ,2: SDMMC2_CCLK ,3: VIP0_VD2[1] = +#define PAD_GPIOC19 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_UP | PAD_STRENGTH_2) // 0: MCUS_ADDR[19] ,1: GPIO ,2: SDMMC2_CMD ,3: VIP0_VD2[2] = +#define PAD_GPIOC20 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_2) // 0: MCUS_ADDR[20] ,1: GPIO ,2: SDMMC2_CDATA[0] ,3: VIP0_VD2[3] = +#define PAD_GPIOC21 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_2) // 0: MCUS_ADDR[21] ,1: GPIO ,2: SDMMC2_CDATA[1] ,3: VIP0_VD2[4] = +#define PAD_GPIOC22 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_2) // 0: MCUS_ADDR[22] ,1: GPIO ,2: SDMMC2_CDATA[2] ,3: VIP0_VD2[5] = +#define PAD_GPIOC23 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_2) // 0: MCUS_ADDR[23] ,1: GPIO ,2: SDMMC2_CDATA[3] ,3: VIP0_VD2[6] = +#define PAD_GPIOC24 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_LATADDR ,1: GPIO ,2: SPDIFIN ,3: VIP0_VD2[7] = +#define PAD_GPIOC25 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_nSWAIT ,1: GPIO ,2: SPDIF_DATA ,3:_ = +#define PAD_GPIOC26 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_RDnWR ,1: GPIO ,2: PDM_DATA0 ,3:_ = DM9000 (IRQ) +#define PAD_GPIOC27 (PAD_MODE_IN | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: MCUS_nSDQM1 ,1: GPIO ,2: PDM_DATA1 ,3:_ = +#define PAD_GPIOC28 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: MCUS_nSCS[1] ,2: UART1_TRI ,3:_ = DM9000 (ETHERNET) +#define PAD_GPIOC29 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SSP0_CLKIO ,2:_ ,3:_ = +#define PAD_GPIOC30 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SSP0_FSS ,2:_ ,3:_ = +#define PAD_GPIOC31 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SSP0_TXD ,2:_ ,3:_ = + +/*------------------------------------------------------------------------------ + * (GROUP_D) + * + * 0 bit 8 bit 12 bit 16 bit 20 bit + * | PAD_MODE_XXX | PAD_FUNC_ALT(0,1,2,3) | PAD_LEVEL_XXX | PAD_PULL_UP,OFF | PAD_STRENGTH_0,1,2,3 + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOD0 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SSP0_RXD ,2: PWM3_OUT ,3:_ = +#define PAD_GPIOD1 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: PWM0_OUT ,2: MCUS_ADDR[25] ,3:_ = +/* psw0523 for camera i2c error */ +#define PAD_GPIOD2 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C0_SCL ,2: UART4_SMCAYEN ,3:_ = +#define PAD_GPIOD3 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C0_SDA ,2: UART5_SMCAYEN ,3:_ = +#define PAD_GPIOD4 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C1_SCL ,2:_ ,3:_ = +#define PAD_GPIOD5 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C1_SDA ,2:_ ,3:_ = +#define PAD_GPIOD6 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C2_SCL ,2:_ ,3:_ = +#define PAD_GPIOD7 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_1) // 0: GPIO ,1: I2C2_SDA ,2:_ ,3:_ = +#define PAD_GPIOD8 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: PPM_IN ,2:_ ,3:_ = +#define PAD_GPIOD9 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: I2S0_SDO ,2: AC97_ACSDATAOUT ,3:_ = +#define PAD_GPIOD10 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: I2S0_BCLK ,2: AC97_ACBITCLK ,3:_ = +#define PAD_GPIOD11 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: I2S0_SDI ,2: AC97_ACSDATAIN ,3:_ = +#define PAD_GPIOD12 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: I2S0_LRCLK ,2: AC97_ACSYNC ,3:_ = +#define PAD_GPIOD13 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: I2S0_CODCLK ,2: AC97_nACRESET ,3:_ = +#define PAD_GPIOD14 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO ,1: UART0RXD ,2: UART1_SMCAYEN ,3:_ = +#define PAD_GPIOD15 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: UART1RXD ,2: UART2_SMCAYEN ,3:_ = +#define PAD_GPIOD16 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO ,1: UART2RXD ,2: CAN0_TX ,3:_ = +#define PAD_GPIOD17 (PAD_MODE_OUT | PAD_FUNC_ALT0 | PAD_LEVEL_HIGH | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: UART3RXD ,2: CAN1_TX ,3:_ = +#define PAD_GPIOD18 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: UART0TXD ,2:_ ,3: SDnCD2 = +#define PAD_GPIOD19 (PAD_MODE_OUT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: UART1TXD ,2:_ ,3:_ = +#define PAD_GPIOD20 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: UART2TXD ,2:_ ,3:_ = +#define PAD_GPIOD21 (PAD_MODE_OUT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO ,1: UART3TXD ,2:_ ,3:_ = +#define PAD_GPIOD22 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CCLK ,2:_ ,3:_ = +#define PAD_GPIOD23 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CMD ,2:_ ,3:_ = +#define PAD_GPIOD24 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CDATA[0] ,2:_ ,3:_ = +#define PAD_GPIOD25 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CDATA[1] ,2:_ ,3:_ = +#define PAD_GPIOD26 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CDATA[3] ,2:_ ,3:_ = +#define PAD_GPIOD27 (PAD_MODE_ALT | PAD_FUNC_ALT1 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: SDMMC1_CDATA[3] ,2:_ ,3:_ = +#define PAD_GPIOD28 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VIP1_VD[0] ,2: MPEGTSI_TDATA1[0] ,3: MCUS_ADDR[24] = +#define PAD_GPIOD29 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VIP1_VD[1] ,2: MPEGTSI_TDATA1[1] ,3:_ = +#define PAD_GPIOD30 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VIP1_VD[2] ,2: MPEGTSI_TDATA1[2] ,3:_ = +#define PAD_GPIOD31 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO ,1: VIP1_VD[3] ,2: MPEGTSI_TDATA1[3] ,3:_ = + +/*------------------------------------------------------------------------------ + * (GROUP_E) + * + * 0 bit 8 bit 12 bit 16 bit 20 bit + * | PAD_MODE_XXX | PAD_FUNC_ALT(0,1,2,3) | PAD_LEVEL_XXX | PAD_PULL_UP,OFF | PAD_STRENGTH_0,1,2,3 + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOE0 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_VD[4] ,2: MPEGTSI_TDATA1[0] ,3:_ = +#define PAD_GPIOE1 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_VD[5] ,2: MPEGTSI_TDATA1[0] ,3:_ = +#define PAD_GPIOE2 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_VD[6] ,2: MPEGTSI_TDATA1[0] ,3:_ = +#define PAD_GPIOE3 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_VD[7] ,2: MPEGTSI_TDATA1[0] ,3:_ = +#define PAD_GPIOE4 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_ExtCLK ,2: MPEGTSI_TCLK1 ,3:_ = +#define PAD_GPIOE5 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP1_HSYNC ,2: MPEGTSI_TSYNC1 ,3:_ = +#define PAD_GPIOE6 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: VIP_VSYNC ,2: MPEGTSI_TDP1 ,3:_ = +#define PAD_GPIOE7 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXD[0] ,2: VIP0_Ext_VSYNC ,3:_ = +#define PAD_GPIOE8 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXD[1] ,2:_ ,3:_ = +#define PAD_GPIOE9 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXD[2] ,2:_ ,3:_ = +#define PAD_GPIOE10 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXD[3] ,2:_ ,3:_ = +#define PAD_GPIOE11 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXEN ,2:_ ,3:_ = +#define PAD_GPIOE12 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_TXER ,2:_ ,3:_ = Backlight Enable +#define PAD_GPIOE13 (PAD_MODE_ALT | PAD_FUNC_ALT2 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_COL ,2: VIP0_Ext_HSYNC ,3:_ = +#define PAD_GPIOE14 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RXD[0] ,2: SSP1_CLKIO ,3:_ = +#define PAD_GPIOE15 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RXD[1] ,2: SSP1_FSS ,3:_ = +#define PAD_GPIOE16 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RXD[2] ,2:_ ,3:_ = VG_EN +#define PAD_GPIOE17 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RXD[3] ,2:_ ,3:_ = +#define PAD_GPIOE18 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_CLK_RX ,2: SSP1_RXD ,3:_ = +#define PAD_GPIOE19 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RX_DV ,2: SSP1_TXD ,3:_ = +#define PAD_GPIOE20 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_DN | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_GMII_MDC ,2:_ ,3:_ = +#define PAD_GPIOE21 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_HIGH | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_GMII_MDI ,2: SDMMC2_CDATA[4] ,3:_ = +#define PAD_GPIOE22 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_HIGH | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_RXER ,2: SDMMC2_CDATA[5] ,3:_ = +#define PAD_GPIOE23 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_HIGH | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_PHY_CRS ,2: SDMMC2_CDATA[6] ,3:_ = +#define PAD_GPIOE24 (PAD_MODE_IN | PAD_FUNC_ALT0 | PAD_LEVEL_HIGH | PAD_PULL_UP | PAD_STRENGTH_0) // 0: GPIO 1: GMAC0_GTX_CLK ,2: SDMMC2_CDATA[7] ,3:_ = +#define PAD_GPIOE25 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: nTRST 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE26 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: TMS 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE27 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: TDI 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE28 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: TCLK 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE29 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: TDO 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE30 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_nSOE 1: GPIO ,2:_ ,3:_ = +#define PAD_GPIOE31 (PAD_MODE_ALT | PAD_FUNC_ALT0 | PAD_LEVEL_LOW | PAD_PULL_OFF | PAD_STRENGTH_0) // 0: MCUS_nSWE 1: GPIO ,2:_ ,3:_ = + +/*------------------------------------------------------------------------------ + * (GROUPALV) + * 0 4 8 12 + * | MODE(IN/OUT/DETECT) | ALIVE OUT or ALIVE DETMODE0 | PullUp | + * + -----------------------------------------------------------------------------*/ +#define PAD_GPIOALV0 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // +#define PAD_GPIOALV1 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // +#define PAD_GPIOALV2 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // +#define PAD_GPIOALV3 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // +#define PAD_GPIOALV4 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // +#define PAD_GPIOALV5 (PAD_MODE_IN | PAD_LEVEL_LOW | PAD_PULL_UP ) // + +/*------------------------------------------------------------------------------ + * TOUCH + */ +#define CFG_IO_TOUCH_PENDOWN_DETECT (PAD_GPIO_B + 29) +//#define CFG_IO_TOUCH_RESET_PIN (PAD_GPIO_C + 12) /* for aw5306 */ + +/*------------------------------------------------------------------------------ + * GPIO EEPROM + */ +#define CFG_IO_SPI_EEPROM_WP ((PAD_GPIO_B + 26) | PAD_FUNC_ALT1) /* GPIO */ + +/*------------------------------------------------------------------------------ + * CAMERA Back Power Down PN + */ +#define CFG_IO_CAMERA_BACK_POWER_DOWN ((PAD_GPIO_C + 4) | PAD_FUNC_ALT0) + +/*------------------------------------------------------------------------------ + * CAMERA Front Power Down PD + */ +#define CFG_IO_CAMERA_FRONT_POWER_DOWN ((PAD_GPIO_C + 6) | PAD_FUNC_ALT0) /* GPIO */ + +/*------------------------------------------------------------------------------ + * CAMERA Reset + */ +#define CFG_IO_CAMERA_RESET ((PAD_GPIO_C + 5) | PAD_FUNC_ALT0) /* GPIO */ + +/*------------------------------------------------------------------------------ + * AUDIO AMP for es8316 + */ +#define CFG_IO_AUDIO_AMP_POWER (PAD_GPIO_D + 19) /* GPIO */ + + +#endif /* __CFG_GPIO_H__ */ + diff --git a/arch/arm/plat-s5p4418/nanopi2/include/cfg_main.h b/arch/arm/plat-s5p4418/nanopi2/include/cfg_main.h new file mode 100644 index 00000000000..a7ed9c5b398 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/include/cfg_main.h @@ -0,0 +1,312 @@ +/*------------------------------------------------------------------------------ + * + * Copyright (C) 2009 Nexell Co., Ltd All Rights Reserved + * Nexell Co. Proprietary & Confidential + * + * NEXELL INFORMS THAT THIS CODE AND INFORMATION IS PROVIDED "AS IS" BASE + * AND WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Module : System memory config + * Description: + * Author : Platform Team + * Export : + * History : + * 2009/05/13 first implementation + ------------------------------------------------------------------------------*/ +#ifndef __CFG_MAIN_H__ +#define __CFG_MAIN_H__ + +#include + +//------------------------------------------------------------------------------ +// PLL input crystal +//------------------------------------------------------------------------------ +#define CFG_SYS_PLLFIN 24000000UL + +/*------------------------------------------------------------------------------ + * System Name + */ +#define CFG_SYS_CPU_NAME "s5p4418" +#define CFG_SYS_BOARD_NAME "s5p4418-NanoPi2" + +/*------------------------------------------------------------------------------ + * BUS config + */ +#define CFG_DREX_PORT0_QOS_ENB 0 +#define CFG_DREX_PORT1_QOS_ENB 1 +#define CFG_BUS_RECONFIG_ENB 1 /* if want bus reconfig, select this first */ + +#define CFG_BUS_RECONFIG_DREXQOS 1 +#define CFG_BUS_RECONFIG_TOPBUSSI 0 +#define CFG_BUS_RECONFIG_TOPBUSQOS 0 +#define CFG_BUS_RECONFIG_BOTTOMBUSSI 0 +#define CFG_BUS_RECONFIG_BOTTOMBUSQOS 0 +#define CFG_BUS_RECONFIG_DISPBUSSI 1 + +/*------------------------------------------------------------------------------ + * Uart + */ +/* For Low level debug */ +#define CFG_UART_DEBUG_BAUDRATE 115200 +#define CFG_UART_CLKGEN_CLOCK_HZ 14750000 /* 50000000 */ + +/*------------------------------------------------------------------------------ + * Timer List (SYS = Source, EVT = Event, WDT = WatchDog) + */ +#define CFG_TIMER_SYS_TICK_CH 0 +#define CFG_TIMER_EVT_TICK_CH 1 + +/*------------------------------------------------------------------------------ + * Extern Ethernet + */ +#define CFG_ETHER_EXT_PHY_BASEADDR 0x04000000 // DM9000: CS1 +#define CFG_ETHER_EXT_IRQ_NUM (IRQ_GPIO_C_START + 26) + +/*------------------------------------------------------------------------------ + * GMAC PHY + */ + +#define CFG_ETHER_LOOPBACK_MODE 0 /* 0: disable, 1: 10M, 2: 100M(x), 3: 1000M(x) */ + + /*for rtl8211*/ +#define CFG_ETHER_GMAC_PHY_IRQ_NUM (IRQ_GPIO_A_START + 9) +#define CFG_ETHER_GMAC_PHY_RST_NUM (PAD_GPIO_A + 10) + +/*------------------------------------------------------------------------------ + * Nand (HWECC) + */ +#define CFG_NAND_ECC_BYTES 1024 +#define CFG_NAND_ECC_BITS 40 /* 512 - 4,8,16,24 1024 - 24,40,60 */ +//#define CFG_NAND_ECCIRQ_MODE + +/* FTL */ +#define CFG_NAND_FTL_START_BLOCK 0x6000000 /* byte address, Must Be Multiple of 8MB */ + +/*------------------------------------------------------------------------------ + * Nand (GPIO) + */ +#define CFG_IO_NAND_nWP (PAD_GPIO_C + 27) /* GPIO */ + +/*------------------------------------------------------------------------------ + * Display (DPC and MLC) + */ +/* Primary */ +#define CFG_DISP_PRI_SCREEN_LAYER 0 +#define CFG_DISP_PRI_SCREEN_RGB_FORMAT MLC_RGBFMT_A8R8G8B8 +#define CFG_DISP_PRI_SCREEN_PIXEL_BYTE 4 +#define CFG_DISP_PRI_SCREEN_COLOR_KEY 0x090909 + +#define CFG_DISP_PRI_VIDEO_PRIORITY 2 // 0, 1, 2, 3 +#define CFG_DISP_PRI_BACK_GROUND_COLOR 0x000000 + +#define CFG_DISP_PRI_MLC_INTERLACE CFALSE + +#define CFG_DISP_PRI_LCD_WIDTH_MM 154 +#define CFG_DISP_PRI_LCD_HEIGHT_MM 85 + +#define CFG_DISP_PRI_RESOL_WIDTH 1024 // X Resolution +#define CFG_DISP_PRI_RESOL_HEIGHT 600 // Y Resolution + +#define CFG_DISP_PRI_HSYNC_SYNC_WIDTH 20 +#define CFG_DISP_PRI_HSYNC_BACK_PORCH 160 +#define CFG_DISP_PRI_HSYNC_FRONT_PORCH 160 +#define CFG_DISP_PRI_HSYNC_ACTIVE_HIGH CTRUE +#define CFG_DISP_PRI_VSYNC_SYNC_WIDTH 3 +#define CFG_DISP_PRI_VSYNC_BACK_PORCH 23 +#define CFG_DISP_PRI_VSYNC_FRONT_PORCH 12 +#define CFG_DISP_PRI_VSYNC_ACTIVE_HIGH CTRUE + +#define CFG_DISP_PRI_CLKGEN0_SOURCE DPC_VCLK_SRC_PLL2 +#define CFG_DISP_PRI_CLKGEN0_DIV 12 // even divide +#define CFG_DISP_PRI_CLKGEN0_DELAY 0 +#define CFG_DISP_PRI_CLKGEN0_INVERT 0 +#define CFG_DISP_PRI_CLKGEN1_SOURCE DPC_VCLK_SRC_VCLK2 +#define CFG_DISP_PRI_CLKGEN1_DIV 1 +#define CFG_DISP_PRI_CLKGEN1_DELAY 0 +#define CFG_DISP_PRI_CLKGEN1_INVERT 0 +#define CFG_DISP_PRI_CLKSEL1_SELECT 0 +#define CFG_DISP_PRI_PADCLKSEL DPC_PADCLKSEL_VCLK /* VCLK=CLKGEN1, VCLK12=CLKGEN0 */ + +#define CFG_DISP_PRI_PIXEL_CLOCK 800000000/CFG_DISP_PRI_CLKGEN0_DIV + +#define CFG_DISP_PRI_OUT_SWAPRB CFALSE +#define CFG_DISP_PRI_OUT_FORMAT DPC_FORMAT_RGB888 +#define CFG_DISP_PRI_OUT_YCORDER DPC_YCORDER_CbYCrY +#define CFG_DISP_PRI_OUT_INTERLACE CFALSE +#define CFG_DISP_PRI_OUT_INVERT_FIELD CFALSE +#define CFG_DISP_LCD_MPY_TYPE 0 + +/*------------------------------------------------------------------------------ + * LVDS + */ +#define CFG_DISP_LVDS_LCD_FORMAT LVDS_LCDFORMAT_VESA + +/*------------------------------------------------------------------------------ + * PWM + */ +#define CFG_LCD_PRI_PWM_CH 0 +#define CFG_LCD_PRI_PWM_FREQ 30000 +#define CFG_LCD_PRI_PWM_DUTYCYCLE 50 /* (%) */ + +/*------------------------------------------------------------------------------ + * Audio I2S (0, 1, 2) + */ +#define CFG_AUDIO_I2S0_MASTER_MODE CTRUE // CTRUE +#define CFG_AUDIO_I2S0_TRANS_MODE 0 // 0:I2S, 1:Left 2:Right justified */ +#define CFG_AUDIO_I2S0_FRAME_BIT 32 // 32, 48 +#define CFG_AUDIO_I2S0_SAMPLE_RATE 48000 +#define CFG_AUDIO_I2S0_PRE_SUPPLY_MCLK 1 + +#define CFG_AUDIO_I2S1_MASTER_MODE CTRUE // CTRUE +#define CFG_AUDIO_I2S1_TRANS_MODE 0 // 0:I2S, 1:Left 2:Right justified */ +#define CFG_AUDIO_I2S1_FRAME_BIT 48 // 32, 48 +#define CFG_AUDIO_I2S1_SAMPLE_RATE 48000 +#define CFG_AUDIO_I2S1_PRE_SUPPLY_MCLK 0 + +#define CFG_AUDIO_I2S2_MASTER_MODE CTRUE // CTRUE +#define CFG_AUDIO_I2S2_TRANS_MODE 0 // 0:I2S, 1:Left 2:Right justified */ +#define CFG_AUDIO_I2S2_FRAME_BIT 48 // 32, 48 +#define CFG_AUDIO_I2S2_SAMPLE_RATE 48000 +#define CFG_AUDIO_I2S2_PRE_SUPPLY_MCLK 0 + +/*------------------------------------------------------------------------------ + * Audio SPDIF (TX/RX) + */ +#define CFG_AUDIO_SPDIF_TX_HDMI_OUT CTRUE +#define CFG_AUDIO_SPDIF_TX_SAMPLE_RATE 48000 +#define CFG_AUDIO_SPDIF_RX_SAMPLE_RATE 48000 + +/*------------------------------------------------------------------------------ + * I2C + */ +#define CFG_I2C0_CLK 100000 +#define CFG_I2C1_CLK 200000 /* TOUCH */ +#define CFG_I2C2_CLK 200000 +#define CFG_I2C3_CLK 100000 + +/*------------------------------------------------------------------------------ + * SPI + */ +#define CFG_SPI0_CLK 10000000 +#define CFG_SPI1_CLK 10000000 +#define CFG_SPI2_CLK 10000000 + +#define CFG_SPI0_COM_MODE 0 /* available 0: INTERRUPT_TRANSFER, 1: POLLING_TRANSFER, 2: DMA_TRANSFER */ +#define CFG_SPI1_COM_MODE 1 /* available 0: INTERRUPT_TRANSFER, 1: POLLING_TRANSFER, 2: DMA_TRANSFER */ +#define CFG_SPI2_COM_MODE 1 /* available 0: INTERRUPT_TRANSFER, 1: POLLING_TRANSFER, 2: DMA_TRANSFER */ + +#define CFG_SPI0_CS_GPIO_MODE 1 /* 0 FSS CONTROL, 1: CS CONTRO GPIO MODE */ +#define CFG_SPI1_CS_GPIO_MODE 1 /* 0 FSS CONTROL, 1: CS CONTRO GPIO MODE */ +#define CFG_SPI2_CS_GPIO_MODE 0 /* 0 FSS CONTROL, 1: CS CONTRO GPIO MODE */ + +#define CFG_SPI0_CS PAD_GPIO_C + 30 /* 0 FSS CONTROL, 1: CS CONTRO GPIO MODE */ +/*------------------------------------------------------------------------------ + * MPEGTSIF + */ +#define CFG_MPEGTS_MASTER_MODE 1 /* 0: slave, 1: master */ +#define CFG_MPEGTS_SLAVE_MODE 0 /* 0: slave, 1: master */ +#define CFG_MPEGTS_CLOCKPOL 1 /* 0: falling, 1: rising */ +#define CFG_MPEGTS_DATAPOL 1 /* 0: data is low, 1: data is high */ +#define CFG_MPEGTS_SYNCPOL 1 /* 0: falling, 1: rising */ +#define CFG_MPEGTS_ERRORPOL 1 /* 0: falling, 1: rising */ +#define CFG_MPEGTS_DATAWIDTH 0 /* 0: 8bit, 1: 1bit */ +#define CFG_MPEGTS_WORDCNT 47 /* 1 ~ 64 */ + +/*------------------------------------------------------------------------------ + * Keypad + */ + +#define CFG_KEYPAD_KEY_BUTTON { PAD_GPIO_ALV + 0 } +#define CFG_KEYPAD_KEY_CODE { KEY_POWER } +#define CFG_KEYPAD_REPEAT CFALSE /* 0: Repeat Off 1 : Repeat On */ + +/*------------------------------------------------------------------------------ + * SDHC + */ +#define CFG_SDMMC0_DETECT_IO (PAD_GPIO_ALV + 1) /* external cd */ + + +/*------------------------------------------------------------------------------ + * PMIC + */ +/* NXE2000 PMIC */ +#define CFG_SW_UBC_ENABLE (1) /* S/W UBC Check */ +#define CFG_USB_DET_FROM_PMIC_INT (0) /* 0 : GPIO interrupt (CFG_GPIO_PMIC_VUSB_DET) 1 : PMIC interrupt (FVUSBDETSINT) */ +#define CFG_GPIO_OTG_USBID_DET (PAD_GPIO_D + 16) /* USB ID Deteict */ +#define CFG_GPIO_OTG_VBUS_DET (PAD_GPIO_D + 21) /* USB OTG Power Enable */ +#define CFG_GPIO_PMIC_VUSB_DET (PAD_GPIO_ALV + 2) /* Choice for SW_UBC or Wake-up*/ +#define CFG_GPIO_PMIC_LOWBAT_DET (-1) /* Critical low battery detect */ +#define CFG_PMIC_BAT_CHG_SUPPORT (1) + +/* AXP228 PMIC */ +#define CFG_PMIC_I2_CBUS 3 /* i2c channel */ +#define CFG_BATTERY_CAP 3000 /* Battery Capacity */ + +/* PMIC Common*/ +#define CFG_GPIO_PMIC_INTR (PAD_GPIO_ALV + 4) /* PMIC Interrupt */ +//#define CONFIG_ENABLE_INIT_VOLTAGE /* Enalbe init voltage for ARM, CORE */ + + +/*------------------------------------------------------------------------------ + * Suspend mode + */ + +/* Wakeup Source : ALIVE [0~7] */ +#define CFG_PWR_WAKEUP_SRC_ALIVE0 CTRUE /* KEY */ +#define CFG_PWR_WAKEUP_MOD_ALIVE0 PWR_DECT_FALLINGEDGE +#define CFG_PWR_WAKEUP_SRC_ALIVE1 CTRUE +#define CFG_PWR_WAKEUP_MOD_ALIVE1 PWR_DECT_BOTHEDGE +#define CFG_PWR_WAKEUP_SRC_ALIVE2 CTRUE /* PMIC - VUSB*/ +#define CFG_PWR_WAKEUP_MOD_ALIVE2 PWR_DECT_FALLINGEDGE +#define CFG_PWR_WAKEUP_SRC_ALIVE3 CFALSE /* PMIC - CRITICAL LOW BATTERY */ +#define CFG_PWR_WAKEUP_MOD_ALIVE3 PWR_DECT_ASYNC_LOWLEVEL +#define CFG_PWR_WAKEUP_SRC_ALIVE4 CTRUE /* PMIC INTR */ +#define CFG_PWR_WAKEUP_MOD_ALIVE4 PWR_DECT_FALLINGEDGE +#define CFG_PWR_WAKEUP_SRC_ALIVE5 CFALSE +#define CFG_PWR_WAKEUP_MOD_ALIVE5 PWR_DECT_FALLINGEDGE + +/* + * Wakeup Source : RTC ALARM + * ifndef Enable ALARM Wakeup + */ +#define CFG_PWR_WAKEUP_SRC_ALARM CFALSE + +//------------------------------------------------------------------------------ +// Static Bus #0 ~ #9, NAND, IDE configuration +//------------------------------------------------------------------------------ +// _BW : Staic Bus width for Static #0 ~ #9 : 8 or 16 +// +// _TACS : adress setup time before chip select : 0 ~ 15 +// _TCOS : chip select setup time before nOE is asserted : 0 ~ 15 +// _TACC : access cycle : 1 ~ 256 +// _TSACC: burst access cycle for Static #0 ~ #9 & IDE : 1 ~ 256 +// _TOCH : chip select hold time after nOE not asserted : 0 ~ 15 +// _TCAH : address hold time after nCS is not asserted : 0 ~ 15 +// +// _WAITMODE : wait enable control for Static #0 ~ #9 & IDE : 1=disable, 2=Active High, 3=Active Low +// _WBURST : burst write mode for Static #0 ~ #9 : 0=disable, 1=4byte, 2=8byte, 3=16byte +// _RBURST : burst read mode for Static #0 ~ #9 : 0=disable, 1=4byte, 2=8byte, 3=16byte +// +//------------------------------------------------------------------------------ +#define CFG_SYS_STATICBUS_CONFIG( _name_, bw, tACS, tCOS, tACC, tSACC, tCOH, tCAH, wm, rb, wb ) \ + enum { \ + CFG_SYS_ ## _name_ ## _BW = bw, \ + CFG_SYS_ ## _name_ ## _TACS = tACS, \ + CFG_SYS_ ## _name_ ## _TCOS = tCOS, \ + CFG_SYS_ ## _name_ ## _TACC = tACC, \ + CFG_SYS_ ## _name_ ## _TSACC = tSACC, \ + CFG_SYS_ ## _name_ ## _TCOH = tCOH, \ + CFG_SYS_ ## _name_ ## _TCAH = tCAH, \ + CFG_SYS_ ## _name_ ## _WAITMODE = wm, \ + CFG_SYS_ ## _name_ ## _RBURST = rb, \ + CFG_SYS_ ## _name_ ## _WBURST = wb \ + }; + +// ( _name_ , bw, tACS tCOS tACC tSACC tOCH tCAH, wm, rb, wb ) +CFG_SYS_STATICBUS_CONFIG( STATIC0 , 8, 1, 1, 6, 6, 1, 1, 1, 0, 0 ) // 0x0000_0000 +CFG_SYS_STATICBUS_CONFIG( STATIC1 , 8, 6, 6, 32, 32, 6, 6, 1, 0, 0 ) // 0x0400_0000 +CFG_SYS_STATICBUS_CONFIG( NAND , 8, 0, 3, 9, 1, 3, 0, 1, 0, 0 ) // 0x2C00_0000, tOCH, tCAH must be greter than 0 + +#endif /* __CFG_MAIN_H__ */ diff --git a/arch/arm/plat-s5p4418/nanopi2/include/cfg_mem.h b/arch/arm/plat-s5p4418/nanopi2/include/cfg_mem.h new file mode 100644 index 00000000000..66e6f0e9dfe --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/include/cfg_mem.h @@ -0,0 +1,32 @@ +/*------------------------------------------------------------------------------ + * + * Copyright (C) 2009 Nexell Co., Ltd All Rights Reserved + * Nexell Co. Proprietary & Confidential + * + * NEXELL INFORMS THAT THIS CODE AND INFORMATION IS PROVIDED "AS IS" BASE + * AND WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING + * BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS + * FOR A PARTICULAR PURPOSE. + * + * Module : System memory config + * Description: + * Author : Platform Team + * Export : + * History : + * 2009/05/13 first implementation + ------------------------------------------------------------------------------*/ +#ifndef __CFG_MEM_H__ +#define __CFG_MEM_H__ + +/*------------------------------------------------------------------------------ + * System memory map + */ +#define CFG_MEM_PHY_SYSTEM_BASE 0x40000000 /* System, must be at an evne 2MB boundary (head.S) */ +#define CFG_MEM_PHY_SYSTEM_SIZE 0x3F000000 /* Total 1G MB */ + +/*------------------------------------------------------------------------------ + * DMA zone, if not defined DAM default size is 2M + */ +#define CFG_MEM_PHY_DMAZONE_SIZE 0x01000000 /* 16 MB DMA zone */ + +#endif /* __CFG_MEM_H__ */ diff --git a/arch/arm/plat-s5p4418/nanopi2/pm.c b/arch/arm/plat-s5p4418/nanopi2/pm.c new file mode 100644 index 00000000000..6b1ed19c927 --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/pm.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2009 + * jung hyun kim, Nexell Co, + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_PM) +#include +#include + +/* register pm ops function */ +static int __init board_suspend_init(void) +{ + return 0; +} +postcore_initcall(board_suspend_init); + +#endif /* CONFIG_PM */ diff --git a/arch/arm/plat-s5p4418/nanopi2/usb-connector.c b/arch/arm/plat-s5p4418/nanopi2/usb-connector.c new file mode 100644 index 00000000000..1c7dc58b31d --- /dev/null +++ b/arch/arm/plat-s5p4418/nanopi2/usb-connector.c @@ -0,0 +1,460 @@ +/* + * Copyright (C) 2012 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define USB_HOST_HUB (1) + +#define pr_fmt(fmt) "s5p4418_otg %s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + + +struct s5p4418_otg { + struct usb_otg otg; + struct usb_phy phy; + struct delayed_work work; + struct mutex lock; + bool usb_connected; + struct usb_bus *ohci; + + /* HACK: s5p4418 phy interface requires passing a pdev pointer */ + struct platform_device pdev; +}; + +static struct s5p4418_otg s_s5p4418_otg; +//static bool s_host_init; + + +static int s5p4418_phy_init(struct usb_phy *phy) +{ +#if !defined(USB_HOST_HUB) + struct s5p4418_otg *nxpotg = container_of(phy, struct s5p4418_otg, phy); + + if (phy->last_event == USB_EVENT_VBUS) + return nxp_usb_phy_init(&nxpotg->pdev, NXP_USB_PHY_DEVICE); + else + return nxp_usb_phy_init(&nxpotg->pdev, NXP_USB_PHY_HOST); +#else + + return 0; +#endif +} + +static void s5p4418_phy_shutdown(struct usb_phy *phy) +{ +#if !defined(USB_HOST_HUB) + struct s5p4418_otg *nxpotg = container_of(phy, struct s5p4418_otg, phy); + + if (nxpotg->phy.state == OTG_STATE_B_PERIPHERAL) + nxp_usb_phy_exit(&nxpotg->pdev, NXP_USB_PHY_DEVICE); + else + nxp_usb_phy_exit(&nxpotg->pdev, NXP_USB_PHY_HOST); +#endif +} + +static int s5p4418_phy_set_power(struct usb_phy *phy, unsigned mA) +{ + if (mA > 3) + atomic_notifier_call_chain(&phy->notifier, USB_EVENT_ENUMERATED, + phy->otg->gadget); + + return 0; +} + +static int s5p4418_otg_host_init(struct s5p4418_otg *nxpotg) +{ +#ifdef CONFIG_USB + struct usb_hcd *hcd = NULL; + struct usb_hcd *ohci_hcd = NULL; + int err; + + if (nxpotg->otg.host) + hcd = bus_to_hcd(nxpotg->otg.host); + + if (hcd) { + err = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); + if (err) { + pr_err("failed to add ehci: %d\n", err); + goto err_ehci; + } + } + + if (nxpotg->ohci) + ohci_hcd = bus_to_hcd(nxpotg->ohci); + + if (ohci_hcd) { + err = usb_add_hcd(ohci_hcd, hcd->irq, IRQF_SHARED); + if (err) { + pr_err("failed to add ohci: %d\n", err); + goto err_ohci; + } + } + + return 0; + +err_ohci: + if (hcd) + usb_remove_hcd(hcd); +err_ehci: + + return err; +#else + return 0; +#endif // #ifdef CONFIG_USB +} + + +static int s5p4418_otg_host_enable(struct s5p4418_otg *nxpotg) +{ +#ifdef CONFIG_USB + struct usb_hcd *hcd = NULL; + struct usb_hcd *ohci_hcd = NULL; + int err; + + usb_phy_init(&nxpotg->phy); + +#if !defined(USB_HOST_HUB) + err = s5p4418_otg_host_init(nxpotg); + if (err) { + pr_err("failed to s5p4418_otg_host_enable: %d\n", err); + goto err_vbus; + } +#endif + + err = otg_set_vbus(&nxpotg->otg, true); + if (err) { + pr_err("failed to enable vbus: %d\n", err); + goto err_vbus; + } + + return 0; + +err_vbus: + usb_phy_shutdown(&nxpotg->phy); + + return err; +#else + return 0; +#endif // #ifdef CONFIG_USB +} + +static void s5p4418_otg_host_disable(struct s5p4418_otg *nxpotg) +{ +#ifdef CONFIG_USB +#if !defined(USB_HOST_HUB) + struct usb_hcd *hcd = NULL; + struct usb_hcd *ohci_hcd = NULL; +#endif + int err; + +#if !defined(USB_HOST_HUB) + if (nxpotg->otg.host) + hcd = bus_to_hcd(nxpotg->otg.host); + + if (nxpotg->ohci) + ohci_hcd = bus_to_hcd(nxpotg->ohci); +#endif + + err = otg_set_vbus(&nxpotg->otg, false); + if (err) + pr_err("failed to disable vbus: %d\n", err); + +#if !defined(USB_HOST_HUB) + if (ohci_hcd) + usb_remove_hcd(ohci_hcd); + if (hcd) + usb_remove_hcd(hcd); +#endif + + usb_phy_shutdown(&nxpotg->phy); +#endif +} + +static int s5p4418_otg_set_host(struct usb_otg *otg, struct usb_bus *host) +{ +#ifdef CONFIG_USB + struct s5p4418_otg *nxpotg = container_of(otg, struct s5p4418_otg, otg); +#if !defined(USB_HOST_HUB) + struct usb_hcd *hcd = bus_to_hcd(host); +#endif + + mutex_lock(&nxpotg->lock); + + +#if defined(USB_HOST_HUB) + otg->host = host; + +#else + + /* HACK to support for ohci */ + if (host && otg->host) { + nxpotg->ohci = host; + usb_remove_hcd(hcd); + usb_phy_shutdown(&nxpotg->phy); + goto out; + } + + otg->host = host; + if (host) { + usb_remove_hcd(bus_to_hcd(host)); + usb_phy_shutdown(&nxpotg->phy); + } else { + if (otg->phy->state == OTG_STATE_A_HOST) + otg->phy->state = OTG_STATE_UNDEFINED; + } + +out: +#endif + mutex_unlock(&nxpotg->lock); +#endif + return 0; +} + +static int s5p4418_otg_set_peripheral(struct usb_otg *otg, + struct usb_gadget *gadget) +{ + struct s5p4418_otg *nxpotg = container_of(otg, struct s5p4418_otg, otg); + + mutex_lock(&nxpotg->lock); + + otg->gadget = gadget; + if (gadget) { + if (otg->phy->state == OTG_STATE_B_PERIPHERAL) + usb_gadget_vbus_connect(nxpotg->otg.gadget); + } else { + if (otg->phy->state == OTG_STATE_B_PERIPHERAL) + otg->phy->state = OTG_STATE_UNDEFINED; + } + + mutex_unlock(&nxpotg->lock); + + return 0; +} + +static int s5p4418_otg_set_vbus(struct usb_otg *otg, bool enabled) +{ + pr_debug("vbus %s\n", enabled ? "on" : "off"); + +#if !defined(USB_HOST_HUB) + if (enabled) + gpio_set_value(CFG_GPIO_OTG_VBUS_DET, 1); + else + gpio_set_value(CFG_GPIO_OTG_VBUS_DET, 0); +#endif + + return 0; +} + +static void s5p4418_otg_work(struct work_struct *work) +{ + struct s5p4418_otg *nxpotg = container_of(work, struct s5p4418_otg, work.work); + enum usb_otg_state prev_state; + int id, vbus, err; + + mutex_lock(&nxpotg->lock); + + prev_state = nxpotg->phy.state; +// vbus = nxpotg->usb_connected; +// vbus = gpio_get_value(CFG_GPIO_PMIC_VUSB_DET); + vbus = 0; + id = gpio_get_value(CFG_GPIO_OTG_USBID_DET); + + pr_debug("vbus=%d id=%d\n", vbus, id); + + if (!id) { + if (prev_state == OTG_STATE_A_HOST) + goto out; + + if (!nxpotg->otg.host) + goto out; + + nxpotg->phy.state = OTG_STATE_A_HOST; + nxpotg->phy.last_event = USB_EVENT_ID; + atomic_notifier_call_chain(&nxpotg->phy.notifier, + USB_EVENT_ID, NULL); + + err = s5p4418_otg_host_enable(nxpotg); + if (err) { + nxpotg->phy.last_event = USB_EVENT_NONE; + nxpotg->phy.state = OTG_STATE_B_IDLE; + atomic_notifier_call_chain(&nxpotg->phy.notifier, + USB_EVENT_NONE, NULL); + goto out; + } + } else if (vbus) { + if (!nxpotg->otg.gadget) + goto out; + + if (prev_state == OTG_STATE_B_PERIPHERAL) + goto out; + + nxpotg->phy.state = OTG_STATE_B_PERIPHERAL; + nxpotg->phy.last_event = USB_EVENT_VBUS; + atomic_notifier_call_chain(&nxpotg->phy.notifier, + USB_EVENT_VBUS, NULL); + usb_gadget_vbus_connect(nxpotg->otg.gadget); + } else { + if (prev_state == OTG_STATE_B_IDLE) + goto out; + + if (prev_state == OTG_STATE_B_PERIPHERAL && nxpotg->otg.gadget) + usb_gadget_vbus_disconnect(nxpotg->otg.gadget); + + if (prev_state == OTG_STATE_A_HOST && nxpotg->otg.host) + s5p4418_otg_host_disable(nxpotg); + + nxpotg->phy.state = OTG_STATE_B_IDLE; + nxpotg->phy.last_event = USB_EVENT_NONE; + atomic_notifier_call_chain(&nxpotg->phy.notifier, + USB_EVENT_NONE, NULL); + } + + pr_info("%s -> %s\n", otg_state_string(prev_state), + otg_state_string(nxpotg->phy.state)); + +out: + mutex_unlock(&nxpotg->lock); +} + +static irqreturn_t s5p4418_otg_irq(int irq, void *data) +{ + struct s5p4418_otg *nxpotg = data; + queue_delayed_work(system_nrt_wq, &nxpotg->work, msecs_to_jiffies(20)); + return IRQ_HANDLED; +} + +void s5p4418_otg_set_usb_state(bool connected) +{ + struct s5p4418_otg *nxpotg = &s_s5p4418_otg; + + nxpotg->usb_connected = connected; + queue_delayed_work(system_nrt_wq, &nxpotg->work, + connected ? msecs_to_jiffies(20) : 0); + if (!connected) + flush_delayed_work(&nxpotg->work); +} + +void nxp_usb_connector_init(void) +{ + struct s5p4418_otg *nxpotg = &s_s5p4418_otg; + struct device *dev = &nxpotg->pdev.dev; + + INIT_DELAYED_WORK(&nxpotg->work, s5p4418_otg_work); + ATOMIC_INIT_NOTIFIER_HEAD(&nxpotg->phy.notifier); + mutex_init(&nxpotg->lock); + + device_initialize(dev); + dev_set_name(dev, "%s", "s5p4418_otg"); + if (device_add(dev)) { + dev_err(dev, "%s: cannot reg device\n", __func__); + return; + } + dev_set_drvdata(dev, nxpotg); + + nxpotg->phy.dev = dev; + nxpotg->phy.label = "s5p4418_otg"; + nxpotg->phy.otg = &nxpotg->otg; + nxpotg->phy.init = s5p4418_phy_init; + nxpotg->phy.shutdown = s5p4418_phy_shutdown; + nxpotg->phy.set_power = s5p4418_phy_set_power; + + nxpotg->otg.phy = &nxpotg->phy; + nxpotg->otg.set_host = s5p4418_otg_set_host; + nxpotg->otg.set_peripheral = s5p4418_otg_set_peripheral; + nxpotg->otg.set_vbus = s5p4418_otg_set_vbus; + + usb_set_transceiver(&nxpotg->phy); +} + +static int __init s5p4418_connector_init(void) +{ + struct s5p4418_otg *nxpotg = &s_s5p4418_otg; + int ret; + + nxp_usb_connector_init(); + + nxp_soc_gpio_set_int_enable(CFG_GPIO_OTG_USBID_DET, 0); + +#if 0 + ret = request_irq(gpio_to_irq(CFG_GPIO_OTG_USBID_DET), s5p4418_otg_irq, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | + IRQF_ONESHOT, "usb_id", nxpotg); +#else + ret = request_irq(gpio_to_irq(CFG_GPIO_OTG_USBID_DET), s5p4418_otg_irq, + IRQ_TYPE_EDGE_BOTH, "usb_id", nxpotg); +#endif + if (ret) + { + pr_err("request_irq ID failed: %d\n", ret); + } + else + { + nxp_soc_gpio_set_io_pullup(CFG_GPIO_OTG_USBID_DET, true); +// nxp_soc_gpio_set_int_mode(CFG_GPIO_OTG_USBID_DET, 4); + nxp_soc_gpio_set_int_enable(CFG_GPIO_OTG_USBID_DET, 1); + nxp_soc_gpio_clr_int_pend(CFG_GPIO_OTG_USBID_DET); + } + +#if 0 + ret = request_irq(gpio_to_irq(CFG_GPIO_PMIC_VUSB_DET), s5p4418_otg_irq, + IRQ_TYPE_EDGE_BOTH, "vusb", nxpotg); + if (ret) + { + pr_err("request_irq CFG_GPIO_PMIC_VUSB_DET failed: %d\n", ret); + } + else + { + nxp_soc_gpio_set_io_pullup(CFG_GPIO_PMIC_VUSB_DET, true); +// nxp_soc_gpio_set_int_mode(CFG_GPIO_PMIC_VUSB_DET, 4); + nxp_soc_gpio_set_int_enable(CFG_GPIO_PMIC_VUSB_DET, 1); + nxp_soc_gpio_clr_int_pend(CFG_GPIO_PMIC_VUSB_DET); + } +#endif + +#if 0 + ret = request_irq(gpio_to_irq(CFG_GPIO_PMIC_LOWBAT_DET), s5p4418_otg_irq, + IRQ_TYPE_EDGE_FALLING, "lowbat", nxpotg); + if (ret) + { + pr_err("request_irq CFG_GPIO_PMIC_LOWBAT_DET failed: %d\n", ret); + } + else + { + nxp_soc_gpio_set_io_pullup(CFG_GPIO_PMIC_LOWBAT_DET, true); + } +#endif + + /* + * HACK: delay the initial otg detection by 4 secs so that it happens + * after the battery driver is ready (this fixes booting with otg cable + * attached) + */ + queue_delayed_work(system_nrt_wq, &nxpotg->work, msecs_to_jiffies(4000)); + + return ret; +} +device_initcall(s5p4418_connector_init);