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base fork: frot/binutils-dcpu16
base: 4098571b77
...
head fork: frot/binutils-dcpu16
compare: b1765c0a47
Checking mergeability… Don't worry, you can still create the pull request.
  • 2 commits
  • 6 files changed
  • 2 commit comments
  • 1 contributor
View
25 gas/testsuite/gas/dcpu16/byte.d
@@ -1,23 +1,26 @@
+# objdump: -Dr
-byte.o: filformat coff-dcpu16
+.*:.*
Disassembly of section .text:
00000000 <.text>:
- 0: 0000 **00** A
+ 0: 0000
1: 0001 set A, A
2: 0002 add A, A
3: 0003 sub A, A
- 4: 1234 3003 ifg [B+0x3003], Y
- 6: 4004 5005 mul A, [A+0x5005]
- 8: ffff fffe **1f** 0xfffe, 0x1e
- a: fffd fffc **1d** 0xfffc, 0x1e
- c: 0000 **00** A
+ 4: 1234 3003 ifg \[B\+0x3003\], Y
+ 6: 4004 5005 mul A, \[A\+0x5005\]
+ 8: ffff fffe std 0xfffe, 0x1e
+ a: fffd
+ b: fffc
+ c: 0000
d: 0001 set A, A
e: 0002 add A, A
f: 0003 sub A, A
- 10: 1234 3003 ifg [B+0x3003], Y
- 12: 4004 5005 mul A, [A+0x5005]
- 14: ffff fffe **1f** 0xfffe, 0x1e
- 16: fffd fffc **1d** 0xfffc, 0x1e
+ 10: 1234 3003 ifg \[B\+0x3003\], Y
+ 12: 4004 5005 mul A, \[A\+0x5005\]
+ 14: ffff fffe std 0xfffe, 0x1e
+ 16: fffd
+ 17: fffc
View
4 gas/testsuite/gas/dcpu16/dcpu16.exp
@@ -1,6 +1,6 @@
-# run tests for target Z80.
+# run tests for target dcpu16.
-if [istarget z80-*-*] then {
+if [istarget dcpu16-*] then {
# test sample program
run_dump_test "sample1"
# test .byte and .short pseudo ops
View
13 gas/testsuite/gas/dcpu16/sample1.d
@@ -1,13 +1,14 @@
+# objdump: -Dr
-sample1.o: filformat coff-dcpu16
+.*:.*
Disassembly of section .text:
00000000 <.text>:
0: 7c01 0030 set A, 0x0030
- 2: 7fc1 1000 0020 set [0x1000], 0x0020
- 5: 7803 1000 sub A, [0x1000]
+ 2: 7fc1 1000 0020 set \[0x1000\], 0x0020
+ 5: 7803 1000 sub A, \[0x1000\]
7: c413 ifn A, 0x10
8: 7f81 001a set PC, 0x001a
9: r_imm16 .text
@@ -15,7 +16,7 @@ Disassembly of section .text:
b: 7c01 2000 set A, 0x2000
0000000d <loop>:
- d: 22c1 2000 set [I+0x2000], [A]
+ d: 22c1 2000 set \[I\+0x2000\], \[A\]
f: 88c3 sub I, 0x01
10: 84d3 ifn I, 0x00
11: 7f81 000d set PC, 0x000d
@@ -27,8 +28,8 @@ Disassembly of section .text:
17: r_imm16 .text
00000018 <testsub>:
- 18: 946e shl X, 0x04
- 19: 6381 set PC, [SP++]
+ 18: 946f shl X, 0x04
+ 19: 6f81 set PC, SP
0000001a <crash>:
1a: 7f81 001a set PC, 0x001a
View
8 include/opcode/dcpu16.h
@@ -56,10 +56,10 @@ struct dcpu16_operand
int long_value;
};
-#define REG_INDEX_PICK 0x1a
-#define REG_INDEX_SP 0x1b
-#define REG_INDEX_PC 0x1c
-#define REG_INDEX_EX 0x1d
+#define REG_INDEX_PICK 11
+#define REG_INDEX_SP 12
+#define REG_INDEX_PC 13
+#define REG_INDEX_EX 14
/* The registers table is an array of struct dcpu16_register. */
struct dcpu16_register
View
20 opcodes/dcpu16-dis.c
@@ -150,21 +150,21 @@ print_insn_dcpu16 (bfd_vma memaddr, struct disassemble_info *info)
{
op = lookup_instruction (opcode&0x1f);
if (op)
- (*info->fprintf_func) (info->stream, "%s\t", op->name);
- else
- (*info->fprintf_func) (info->stream, "**%02x**\t", opcode&0x1f);
- result += print_operand(memaddr+result, info, (opcode>>5)&0x1f, 1);
- (*info->fprintf_func) (info->stream, ", ");
- result += print_operand(memaddr+result, info, opcode>>10, 0);
+ {
+ (*info->fprintf_func) (info->stream, "%s\t", op->name);
+ result += print_operand(memaddr+result, info, (opcode>>5)&0x1f, 1);
+ (*info->fprintf_func) (info->stream, ", ");
+ result += print_operand(memaddr+result, info, opcode>>10, 0);
+ }
}
else
{
op = lookup_instruction (opcode&0x3ff);
if (op)
- (*info->fprintf_func) (info->stream, "%s\t", op->name);
- else
- (*info->fprintf_func) (info->stream, "**%02x:00**\t", (opcode&0x3ff)>>5);
- result += print_operand(memaddr+result, info, opcode>>10, 0);
+ {
+ (*info->fprintf_func) (info->stream, "%s\t", op->name);
+ result += print_operand(memaddr+result, info, opcode>>10, 0);
+ }
}
return 2*result;
View
2  opcodes/dcpu16-opc.c
@@ -65,8 +65,6 @@ const struct dcpu16_opcode dcpu16_opcode_table[] =
{ "hwq", 0x11<<5, 1 },
{ "hwi", 0x12<<5, 1 },
- { "push", 0x0301, 1 },
- /* { "pop", 0x6001, 1 }, this won't actually work -- need b operand, not a */
{ "jmp", 0x0381, 1 },
{ "bra", 0x0382, 1 },
{ "ret", 0x6381, 0 },

Showing you all comments on commits in this comparison.

@a1k0n

Why did you make this change? Did you forget to add a matching change to dcpu16_register_table?

@frot
Owner

Mixup of different ideas during development. Should be the index into the register table.

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