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v0.1.12
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@github-actions github-actions released this 16 Jan 22:08
· 248 commits to master since this release
v0.1.12
f11e0e7

Compiler

  • Support conditional compiler directives in importer.
  • Support macro definitions in importer.
  • Support decimal literals in u and s functions.
  • Support tasks with return values.
  • fork and join functions.
  • Support x and z bit constants.
  • Support type alias with type parameters.
  • Evaluate logical operators and if expressions.
  • Added end-to-end regression tests.
  • Four state boolean values unknown and floating.
  • Copy KDoc comments into generated SystemVerilog.
  • Adopt StageType based stage sequence in importer.
  • Turn off enableLineDirective by default.
  • Rename Logical to Optional.
  • Rewrite constant expression handling.
  • Merge Optional with Cardinal.
  • Separate MID_TRANSFORM into UPPER_TRANSFORM and LOWER_TRANSFORM.
  • Rewrite specialize and resolve stages to move type resolution after specialization.
  • New scheme for extracting expressions with BlockExpressionReducerStage.
  • Merge KtCallExpression and SvCallExpression.
  • Merge KtBlockExpression and SvBlockExpression.
  • Merge KtProperty and SvProperty.
  • Shorten function names on Ubit such as sli, rev, and inv.
Assets 2