diff --git a/src/CGB_Registers.md b/src/CGB_Registers.md
index a38441c0..d7717a5b 100644
--- a/src/CGB_Registers.md
+++ b/src/CGB_Registers.md
@@ -39,12 +39,14 @@ tested on Echo RAM, OAM, FEXX, IO and HRAM\]. Trying to specify a source
 address in VRAM will cause garbage to be copied.
 
 The four lower bits of this address will be ignored and treated as 0.
+The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again.
 
 #### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]
 
 These two registers specify the address within 8000-9FF0 to which the
 data will be copied. Only bits 12-4 are respected; others are ignored.
 The four lower bits of this address will be ignored and treated as 0.
+The address specified by those registers is cached internally and incremented by $10 for each block of $10 bytes successfully transferred. The cached address persists until the registers are written again.
 
 #### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start