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mov (0x8e) should has [SREG, RFULL_M16] as its operand #45

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GoogleCodeExporter opened this Issue Mar 20, 2015 · 2 comments

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GoogleCodeExporter commented Mar 20, 2015

I'm using diStorm's disOps python script to generate an instruction database, 
and try to write a disassembler (to learn x86 instruction set better).

Currently mov (0x8e) has [SREG, RM16] as its operand. Objdump uses 32bit 
register in its decoding output.
But for lldt (0x0f 0x00 /02), which has [RM16] as its operand, objdump uses 
16bit register.

Here's a comparison of objdump's output for mov (0x8e and 0x8c) and lldt:

8e e0:   mov  %eax,%fs
8c e8:   mov %gs,%eax
0f 00 d2:    lldt %dx

When consulting the Intel Manual (vol 2b, 2011 version), the mov (0x8e) opcode 
has the same note as 0x8c.
So I guess mov (0x8e) should also have RFULL_M16 as its 2nd operand, the same 
as the 1st operand of mov (0x8c).

Original issue reported on code.google.com by cyfde...@gmail.com on 15 Mar 2012 at 10:35

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GoogleCodeExporter Mar 20, 2015

Thanks, I will check it out and fix it. Keep on finding problems in the DB ;)

Original comment by distorm@gmail.com on 19 Mar 2012 at 1:44

  • Changed state: Accepted

GoogleCodeExporter commented Mar 20, 2015

Thanks, I will check it out and fix it. Keep on finding problems in the DB ;)

Original comment by distorm@gmail.com on 19 Mar 2012 at 1:44

  • Changed state: Accepted
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Original comment by distorm@gmail.com on 21 Mar 2012 at 4:45

  • Changed state: Fixed

GoogleCodeExporter commented Mar 20, 2015

Original comment by distorm@gmail.com on 21 Mar 2012 at 4:45

  • Changed state: Fixed
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