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gdessouky/hackdac_2018_beta

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The SoC used for the beta phase of Hack@DAC 2018.

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  • SystemVerilog 50.6%
  • Verilog 22.7%
  • VHDL 21.8%
  • Tcl 2.6%
  • Coq 1.0%
  • Perl 0.6%
  • Other 0.7%