From 1c27f9908d0c57a98b6ce7619d9ddd88a7ff62cf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ji=C5=99=C3=AD=20Techet?= <techet@gmail.com>
Date: Mon, 11 Apr 2022 20:59:44 +0200
Subject: [PATCH 1/2] Add VHDL unit tests from uctags and remove the giant
 test.vhd

The test.vhd file is more than 8000 LOCs, it seems to be multiple
concatenated VHDL sources and because of the large amount of tags,
it's hard to see the changes.
---
 tests/ctags/Makefile.am             |    6 +-
 tests/ctags/test.vhd                | 8174 ---------------------------
 tests/ctags/test.vhd.tags           |  358 --
 tests/ctags/vhdl-component.vhd      |   54 +
 tests/ctags/vhdl-component.vhd.tags |    6 +
 tests/ctags/vhdl-local.vhd          |  203 +
 tests/ctags/vhdl-local.vhd.tags     |   27 +
 tests/ctags/vhdl-port.vhd           |    5 +
 tests/ctags/vhdl-port.vhd.tags      |    2 +
 tests/ctags/vhdl-process.vhd        |   51 +
 tests/ctags/vhdl-process.vhd.tags   |    7 +
 tests/ctags/vhdl-type.vhd           |  325 ++
 tests/ctags/vhdl-type.vhd.tags      |   25 +
 tests/meson.build                   |    6 +-
 14 files changed, 715 insertions(+), 8534 deletions(-)
 delete mode 100644 tests/ctags/test.vhd
 delete mode 100644 tests/ctags/test.vhd.tags
 create mode 100644 tests/ctags/vhdl-component.vhd
 create mode 100644 tests/ctags/vhdl-component.vhd.tags
 create mode 100644 tests/ctags/vhdl-local.vhd
 create mode 100644 tests/ctags/vhdl-local.vhd.tags
 create mode 100644 tests/ctags/vhdl-port.vhd
 create mode 100644 tests/ctags/vhdl-port.vhd.tags
 create mode 100644 tests/ctags/vhdl-process.vhd
 create mode 100644 tests/ctags/vhdl-process.vhd.tags
 create mode 100644 tests/ctags/vhdl-type.vhd
 create mode 100644 tests/ctags/vhdl-type.vhd.tags

diff --git a/tests/ctags/Makefile.am b/tests/ctags/Makefile.am
index 278530b33d..10be08fa06 100644
--- a/tests/ctags/Makefile.am
+++ b/tests/ctags/Makefile.am
@@ -327,7 +327,6 @@ test_sources = \
 	test.erl						\
 	test.go							\
 	test.py							\
-	test.vhd						\
 	test_input.rs					\
 	test_input2.rs					\
 	titles.t2t						\
@@ -337,6 +336,11 @@ test_sources = \
 	union.f							\
 	value.f							\
 	var-and-return-type.cpp			\
+	vhdl-component.vhd				\
+	vhdl-local.vhd					\
+	vhdl-port.vhd					\
+	vhdl-process.vhd				\
+	vhdl-type.vhd					\
 	whitespaces.php					\
 	$(NULL)
 test_results = $(test_sources:=.tags)
diff --git a/tests/ctags/test.vhd b/tests/ctags/test.vhd
deleted file mode 100644
index 917f6015e3..0000000000
--- a/tests/ctags/test.vhd
+++ /dev/null
@@ -1,8174 +0,0 @@
-package body badger is
-end package body;
-
-package body badger2 is
-end package body badger2;
-
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity accumulator is port (
-  a: in std_logic_vector(3 downto 0);
-  clk, reset: in std_logic;
-  accum: out std_logic_vector(3 downto 0)
-  );
-end accumulator;
-
-architecture simple of accumulator is
-
-signal accumL: unsigned(3 downto 0);
-
-begin
-
-  accumulate: process (clk, reset) begin
-    if (reset = '1') then
-      accumL <= "0000";
-    elsif (clk'event and clk= '1') then
-      accumL <= accumL + to_unsigned(a);
-    end if;
-  end process;
-
-  accum <= std_logic_vector(accumL);
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity adder is port (
-  a,b : in std_logic_vector (15 downto 0);
-  sum: out std_logic_vector (15 downto 0)
-  );
-end adder;
-
-architecture dataflow of adder is
-
-begin
-
-  sum <= a + b;
-
-end dataflow;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pAdderAttr is
-  generic(n : integer := 8);
-  port (a    : in std_logic_vector(n - 1 downto 0);
-        b    : in std_logic_vector(n - 1 downto 0);
-        cin  : in std_logic;
-        sum  : out std_logic_vector(n - 1 downto 0);
-        cout : out std_logic);
-end pAdderAttr;
-
-
-architecture loopDemo of pAdderAttr is
-
-begin
-
-  process(a, b, cin)
-    variable carry: std_logic_vector(sum'length downto 0);
-    variable localSum: std_logic_vector(sum'high downto 0);
-
-  begin
-
-    carry(0) := cin;
-
-    for i in sum'reverse_range loop
-      localSum(i)  := (a(i) xor b(i)) xor carry(i);
-      carry(i + 1) := (a(i) and b(i)) or (carry(i) and (a(i) or b(i)));
-    end loop;
-
-    sum <= localSum;
-    cout <= carry(carry'high - 1);
-
-  end process;
-
-end loopDemo;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity adder is port (
-  a,b: in unsigned(3 downto 0);
-  sum: out unsigned(3 downto 0)
-  );
-end adder;
-
-architecture simple of adder is
-
-begin
-
-  sum <= a + b;
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity AND2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end AND2;
-
-architecture rtl of AND2 is
-
-begin
-
-  y <= '1' when i1 = '1' and i2 = '1' else '0';
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity asyncLoad is port (
-  loadVal, d: in std_logic_vector(3 downto 0);
-  clk, load: in std_logic;
-  q: out std_logic_vector(3 downto 0)
-  );
-end asyncLoad;
-
-architecture rtl of asyncLoad is
-
-begin
-
-  process (clk, load, loadVal) begin
-    if (load = '1') then
-      q <= loadVal;
-    elsif (clk'event and clk = '1' ) then
-      q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity BidirBuf is port (
-  OE: in std_logic;
-  input: in std_logic_vector;
-  output: out std_logic_vector
-  );
-end BidirBuf;
-
-architecture behavioral of BidirBuf is
-
-begin
-
-  bidirBuf: process (OE, input) begin
-    if (OE = '1') then
-      output <= input;
-    else
-      output <= (others => 'Z');
-    end if;
-  end process;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity BidirCnt is port (
-  OE: in std_logic;
-  CntEnable: in std_logic;
-  LdCnt: in std_logic;
-  Clk: in std_logic;
-  Rst: in std_logic;
-  Cnt: inout std_logic_vector(3 downto 0)
-  );
-end BidirCnt;
-
-architecture behavioral of BidirCnt is
-
-  component LoadCnt port (
-    CntEn: in std_logic;
-    LdCnt: in std_logic;
-    LdData: in std_logic_vector(3 downto 0);
-    Clk: in std_logic;
-    Rst: in std_logic;
-    CntVal: out std_logic_vector(3 downto 0)
-    );
-  end component;
-
-  component BidirBuf port (
-    OE: in std_logic;
-    input: in std_logic_vector;
-    output: inout std_logic_vector
-    );
-  end component;
-
-signal CntVal: std_logic_vector(3 downto 0);
-signal LoadVal: std_logic_vector(3 downto 0);
-
-begin
-
-  u1: loadcnt port map (CntEn => CntEnable,
-                        LdCnt => LdCnt,
-                        LdData => LoadVal,
-                        Clk => Clk,
-                        Rst => Rst,
-                        CntVal => CntVal
-                        );
-
-  u2: bidirbuf port map (OE => oe,
-                         input => CntVal,
-                         output => Cnt
-                        );
-
-  LoadVal <= Cnt;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity BIDIR is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op_fb: out std_logic;
-  op: inout std_logic
-  );
-end BIDIR;
-
-architecture rtl of BIDIR is
-
-begin
-
-  op <= ip when oe = '1' else 'Z';
-  op_fb <= op;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity bidirbuffer is port (
-  input: in std_logic;
-  enable: in std_logic;
-  feedback: out std_logic;
-  output: inout std_logic
-  );
-end bidirbuffer;
-
-architecture structural of bidirbuffer is
-
-begin
-
-  u1: bidir port map (ip => input,
-                      oe => enable,
-                      op_fb => feedback,
-                      op => output
-                      );
-
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity clkGen is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  ClkDiv2, ClkDiv4,
-  ClkDiv6,ClkDiv8: out std_logic
-  );
-end clkGen;
- 
-architecture behav of clkGen is
-
-subtype numClks is std_logic_vector(1 to 4);
-subtype numPatterns is integer range 0 to 11;
-
-type clkTableType is array (numpatterns'low to numPatterns'high) of numClks;
-
-constant clkTable: clkTableType := clkTableType'(
--- ClkDiv8______
--- ClkDiv6_____ |
--- ClkDiv4____ ||
--- ClkDiv2 __ |||
---           ||||
-            "1111",
-            "0111",
-            "1011",
-            "0001",
-            "1100",
-            "0100",
-            "1010",
-            "0010",
-            "1111",
-            "0001",
-            "1001",
-            "0101"); 
-
-signal index: numPatterns;
- 
-begin
-
-  lookupTable: process (clk, reset) begin
-    if reset = '1' then
-      index <= 0;
-    elsif (clk'event and clk = '1') then
-      if index = numPatterns'high then
-        index <= numPatterns'low;
-      else
-        index <= index + 1;
-      end if;
-    end if;
-  end process;
-
-  (ClkDiv2,ClkDiv4,ClkDiv6,ClkDiv8) <= clkTable(index);
-
-end behav;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  enable: in std_logic;
-  reset: in std_logic;
-  count: buffer unsigned(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-begin
-
-  increment: process (clk, reset) begin
-    if reset = '1' then
-      count <= "0000";
-    elsif(clk'event and clk = '1') then
-      if enable = '1' then
-        count <= count + 1;
-      else
-        count <= count;
-      end if;
-    end if;
-  end process;
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.scaleable.all;
-
-entity count8 is port (
-  clk: in std_logic;
-  rst: in std_logic;
-  count: out std_logic_vector(7 downto 0)
-  );
-end count8;
-
-architecture structural of count8 is
-
-begin
-
-  u1: scaleUpCnt port map (clk => clk,
-                           reset => rst,
-                           cnt => count
-                          );
-
-end structural;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(0 to 9)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(0 to 9);
-
-begin
-
-  increment: process (clk, reset) begin
-    if reset = '1' then
-      countL <= to_unsigned(3,10);
-    elsif(clk'event and clk = '1') then
-      countL <= countL + 1;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(9 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(9 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if reset = '1' then
-      countL <= to_unsigned(0,10);
-    elsif(clk'event and clk = '1') then
-      countL <= countL + 1;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  load: in std_logic;
-  enable: in std_logic;
-  data: in std_logic_vector(3 downto 0);
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if (reset = '1') then
-      countL <= "0000";
-    elsif(clk'event and clk = '1') then
-      if (load = '1') then
-        countL <= to_unsigned(data);
-      elsif (enable = '1') then
-        countL <= countL + 1;
-      end if;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  load: in std_logic;
-  data: in std_logic_vector(3 downto 0);
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if (reset = '1') then
-      countL <= "0000";
-    elsif(clk'event and clk = '1') then
-      if (load = '1') then
-        countL <= to_unsigned(data);
-      else
-        countL <= countL + 1;
-      end if;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity Cnt4Term is port (
-  clk: in std_logic;
-  Cnt: out std_logic_vector(3 downto 0);
-  TermCnt: out std_logic
-  );
-end Cnt4Term;
-
-architecture behavioral of Cnt4Term is
-
-signal CntL: unsigned(3 downto 0);
-
-begin
-
-  increment: process begin
-    wait until clk = '1';
-      CntL <= CntL + 1;
-  end process;
-
-  Cnt <= to_stdlogicvector(CntL);
-
-  TermCnt <= '1' when CntL = "1111" else '0';
-
-end behavioral;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity Counter is port (
-  clock: in std_logic;
-  Count: out std_logic_vector(3 downto 0)
-  );
-end Counter;
-
-architecture structural of Counter is
-
-  component Cnt4Term port (
-    clk: in std_logic;
-    Cnt: out std_logic_vector(3 downto 0);
-    TermCnt: out std_logic);
-  end component;
-
-begin
-
-  u1: Cnt4Term port map (clk => clock,
-                         Cnt => Count,
-                         TermCnt => open
-                    );
-
-end structural;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk) begin
-    if(clk'event and clk = '1') then
-      if (reset = '1') then
-        countL <= "0000";
-      else
-        countL <= countL + 1;
-      end if;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity convertArith is port (
-  truncate: out unsigned(3 downto 0);
-  extend: out unsigned(15 downto 0);
-  direction: out unsigned(0 to 7)
-  );
-end convertArith;
-
-architecture simple of convertArith is
-
-constant Const: unsigned(7 downto 0) := "00111010";
-
-begin
-
-  truncate  <= resize(Const, truncate'length);
-  extend    <= resize(Const, extend'length);
-  direction <= resize(Const, direction'length);
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-architecture concurrent of FEWGATES is
-
-constant THREE: std_logic_vector(1 downto 0) := "11";
-
-begin
-
-  y <= '1' when (a & b = THREE) or (c & d /= THREE) else '0';
-
-end concurrent;
--- incorporates Errata 12.1
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity typeConvert is port (
-  a: out unsigned(7 downto 0)
-  );
-end typeConvert;
-
-architecture simple of typeConvert is
-
-constant Const: natural := 43;
-
-begin
-
-  a <= To_unsigned(Const,8);
-
-end simple;
--- Incorporates Errata 5.4 
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk) begin
-    if (clk'event and clk = '1') then
-      countL <= countL + 1;
-    end if;
-  end process;
-
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(0 to 3)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(0 to 3);
-
-begin
-
-  increment: process (clk, reset) begin
-    if reset = '1' then
-      countL <= "1001";
-    elsif(clk'event and clk = '1') then
-      countL <= countL + 1;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if (reset = '1') then
-      countL <= "0000";
-    elsif(clk'event and clk = '1') then
-      countL <= countL + "001";
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if reset = '1' then
-      countL <= "1001";
-    elsif(clk'event and clk = '1') then
-      countL <= countL + 1;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity counter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end counter;
-
-architecture simple of counter is
-
-signal countL: unsigned(3 downto 0);
-
-begin
-
-  increment: process (clk, reset) begin
-    if (reset = '1') then
-      countL <= "1001";
-    elsif(clk'event and clk = '1') then
-      countL <= countL + "0001";
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.decProcs.all;
-
-entity decoder is port (
-  decIn: in std_logic_vector(1 downto 0);
-  decOut: out std_logic_vector(3 downto 0)
-  );
-end decoder;
-
-architecture simple of decoder is
-
-begin
-
-  DEC2x4(decIn,decOut);
-
-end simple;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:          in std_logic_vector(19 downto 0);
-
-  decOut_n:         out std_logic_vector(5 downto 0)
-
-);
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)    := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)    := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-  alias sio_dec_n: std_logic is        decOut_n(5);
-  alias rst_ctrl_rd_n: std_logic is    decOut_n(4);
-  alias atc_stat_rd_n: std_logic is    decOut_n(3);
-  alias mgmt_stat_rd_n: std_logic is   decOut_n(2);
-  alias io_int_stat_rd_n: std_logic is decOut_n(1);
-  alias int_ctrl_rd_n: std_logic is    decOut_n(0);
-
-  alias upper: std_logic_vector(2 downto 0) is dev_adr(19 downto 17);
-  alias CtrlBits: std_logic_vector(16 downto 0) is dev_adr(16 downto 0);
-
-begin
-
-  decoder: process (upper, CtrlBits)
-    begin 
-      -- Set defaults for outputs - for synthesis reasons.
-
-        sio_dec_n        <= '1';
-        int_ctrl_rd_n    <= '1';
-        io_int_stat_rd_n <= '1';
-        rst_ctrl_rd_n    <= '1';
-        atc_stat_rd_n    <= '1';
-        mgmt_stat_rd_n   <= '1';
-
-        case upper is 
-
-        when SuperIoRange =>
-          sio_dec_n <= '0';
-		
-        when CtrlRegRange =>
-
-          case CtrlBits is
-			
-            when IntCtrlReg =>
-              int_ctrl_rd_n <= '0';
-
-            when IoIntStatReg =>
-              io_int_stat_rd_n <= '0';
-
-            when RstCtrlReg =>
-              rst_ctrl_rd_n <= '0';
-
-            when AtcStatusReg =>
-              atc_stat_rd_n <= '0';
-
-            when MgmtStatusReg =>
-              mgmt_stat_rd_n <= '0';
-
-            when others =>
-              null;
-							
-            end case;
-
-          when others =>
-            null;                     
-					
-        end case;
-
-  end process decoder;
-
-end synthesis;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:          in std_logic_vector(19 downto 0);
-
-  sio_dec_n:        out std_logic;
-  rst_ctrl_rd_n:    out std_logic;
-  atc_stat_rd_n:    out std_logic;
-  mgmt_stat_rd_n:   out std_logic;
-  io_int_stat_rd_n: out std_logic;
-  int_ctrl_rd_n:    out std_logic
-);
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)    := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)    := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-begin
-
-  decoder: process (dev_adr)
-    begin 
-      -- Set defaults for outputs
-
-        sio_dec_n        <= '1';
-        int_ctrl_rd_n    <= '1';
-        io_int_stat_rd_n <= '1';
-        rst_ctrl_rd_n    <= '1';
-        atc_stat_rd_n    <= '1';
-        mgmt_stat_rd_n   <= '1';
-
-        case dev_adr(19 downto 17) is 
-
-        when SuperIoRange =>
-          sio_dec_n <= '0';
-		
-        when CtrlRegRange =>
-
-          case dev_adr(16 downto 0) is
-			
-            when IntCtrlReg =>
-              int_ctrl_rd_n <= '0';
-
-            when IoIntStatReg =>
-              io_int_stat_rd_n <= '0';
-
-            when RstCtrlReg =>
-              rst_ctrl_rd_n <= '0';
-
-            when AtcStatusReg =>
-              atc_stat_rd_n <= '0';
-
-            when MgmtStatusReg =>
-              mgmt_stat_rd_n <= '0';
-
-            when others =>
-              null;
-							
-            end case;
-
-          when others =>
-            null;                     
-					
-        end case;
-
-  end process decoder;
-
-end synthesis;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:         in std_logic_vector(19 downto 0);
-
-  sio_dec_n:       out std_logic;
-  rst_ctrl_rd_n:   out std_logic;
-  atc_stat_rd_n:   out std_logic;
-  mgmt_stat_rd_n:  out std_logic;
-  io_int_stat_rd_n:out std_logic;
-  int_ctrl_rd_n:   out std_logic
-  );
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)  := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)  := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-begin
-  sio_dec_n <= '0' when dev_adr (19 downto 17) = SuperIORange else '1';
-
-  int_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
-                        and (dev_adr(16 downto 0) = IntCtrlReg) else '1';
-
-  io_int_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
-                           and (dev_adr(16 downto 0) = IoIntStatReg) else '1';
-
-  rst_ctrl_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
-                        and (dev_adr(16 downto 0) = RstCtrlReg) else '1';
-
-  atc_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
-                        and (dev_adr(16 downto 0) = AtcStatusReg) else '1';
-
-  mgmt_stat_rd_n <= '0' when (dev_adr (19 downto 17) = CtrlRegRange)
-                         and (dev_adr(16 downto 0) = MgmtStatusReg) else '1';
-
-
-end synthesis;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:          in std_logic_vector(19 downto 0);
-  cs0_n:            in std_logic;
-
-  sio_dec_n:        out std_logic;
-  rst_ctrl_rd_n:    out std_logic;
-  atc_stat_rd_n:    out std_logic;
-  mgmt_stat_rd_n:   out std_logic;
-  io_int_stat_rd_n: out std_logic;
-  int_ctrl_rd_n:    out std_logic
-);
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)    := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)    := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-begin
-
-  decoder: process (dev_adr, cs0_n)
-    begin 
-      -- Set defaults for outputs - for synthesis reasons.
-
-        sio_dec_n        <= '1';
-        int_ctrl_rd_n    <= '1';
-        io_int_stat_rd_n <= '1';
-        rst_ctrl_rd_n    <= '1';
-        atc_stat_rd_n    <= '1';
-        mgmt_stat_rd_n   <= '1';
-
-        if (cs0_n = '0') then
-          case dev_adr(19 downto 17) is 
-
-          when SuperIoRange =>
-            sio_dec_n <= '0';
-		
-          when CtrlRegRange =>
-
-            case dev_adr(16 downto 0) is
-			
-              when IntCtrlReg =>
-                int_ctrl_rd_n <= '0';
-
-              when IoIntStatReg =>
-                io_int_stat_rd_n <= '0';
-
-              when RstCtrlReg =>
-                rst_ctrl_rd_n <= '0';
-
-              when AtcStatusReg =>
-                atc_stat_rd_n <= '0';
-
-              when MgmtStatusReg =>
-                mgmt_stat_rd_n <= '0';
-
-              when others =>
-                null;
-							
-              end case;
-
-            when others =>
-              null;                     
-                         
-          end case;
-        else
-          null;
-        end if;
-
-  end process decoder;
-
-end synthesis;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:          in std_logic_vector(19 downto 0);
-  cs0_n:            in std_logic;
-
-  sio_dec_n:        out std_logic;
-  rst_ctrl_rd_n:    out std_logic;
-  atc_stat_rd_n:    out std_logic;
-  mgmt_stat_rd_n:   out std_logic;
-  io_int_stat_rd_n: out std_logic;
-  int_ctrl_rd_n:    out std_logic
-);
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)    := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)    := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-  signal Lsio_dec_n:        std_logic;
-  signal Lrst_ctrl_rd_n:    std_logic;
-  signal Latc_stat_rd_n:    std_logic;
-  signal Lmgmt_stat_rd_n:   std_logic;
-  signal Lio_int_stat_rd_n: std_logic;
-  signal Lint_ctrl_rd_n:    std_logic;
-
-begin
-
-  decoder: process (dev_adr)
-    begin 
-      -- Set defaults for outputs - for synthesis reasons.
-
-        Lsio_dec_n        <= '1';
-        Lint_ctrl_rd_n    <= '1';
-        Lio_int_stat_rd_n <= '1';
-        Lrst_ctrl_rd_n    <= '1';
-        Latc_stat_rd_n    <= '1';
-        Lmgmt_stat_rd_n   <= '1';
-
-        case dev_adr(19 downto 17) is 
-
-        when SuperIoRange =>
-          Lsio_dec_n <= '0';
-		
-        when CtrlRegRange =>
-
-          case dev_adr(16 downto 0) is
-			
-            when IntCtrlReg =>
-              Lint_ctrl_rd_n <= '0';
-
-            when IoIntStatReg =>
-              Lio_int_stat_rd_n <= '0';
-
-            when RstCtrlReg =>
-              Lrst_ctrl_rd_n <= '0';
-
-            when AtcStatusReg =>
-              Latc_stat_rd_n <= '0';
-
-            when MgmtStatusReg =>
-              Lmgmt_stat_rd_n <= '0';
-
-            when others =>
-              null;
-							
-            end case;
-
-          when others =>
-            null;                     
-                         
-        end case;
-
-  end process decoder;
-
-  qualify: process (cs0_n) begin
-
-    sio_dec_n        <= '1';
-    int_ctrl_rd_n    <= '1';
-    io_int_stat_rd_n <= '1';
-    rst_ctrl_rd_n    <= '1';
-    atc_stat_rd_n    <= '1';
-    mgmt_stat_rd_n   <= '1';
-
-    if (cs0_n = '0') then
-      sio_dec_n        <= Lsio_dec_n;
-      int_ctrl_rd_n    <= Lint_ctrl_rd_n;
-      io_int_stat_rd_n <= Lio_int_stat_rd_n;
-      rst_ctrl_rd_n    <= Lrst_ctrl_rd_n;
-      atc_stat_rd_n    <= Latc_stat_rd_n;
-      mgmt_stat_rd_n   <= Lmgmt_stat_rd_n;
-    else
-      null;
-    end if;
-  end process qualify;
-
-end synthesis;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:          in std_logic_vector(19 downto 0);
-
-  sio_dec_n:        out std_logic;
-  rst_ctrl_rd_n:    out std_logic;
-  atc_stat_rd_n:    out std_logic;
-  mgmt_stat_rd_n:   out std_logic;
-  io_int_stat_rd_n: out std_logic;
-  int_ctrl_rd_n:    out std_logic
-);
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)    := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)    := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-begin
-
-  decoder: process ( dev_adr)
-    begin 
-      -- Set defaults for outputs - for synthesis reasons.
-
-        sio_dec_n        <= '1';
-        int_ctrl_rd_n    <= '1';
-        io_int_stat_rd_n <= '1';
-        rst_ctrl_rd_n    <= '1';
-        atc_stat_rd_n    <= '1';
-        mgmt_stat_rd_n   <= '1';
-
-        if dev_adr(19 downto 17) = SuperIOrange then
-
-          sio_dec_n <= '0';
-
-        elsif dev_adr(19 downto 17) = CtrlRegrange then
-
-          if dev_adr(16 downto 0) = IntCtrlReg then
-
-            int_ctrl_rd_n <= '0';
-
-          elsif dev_adr(16 downto 0)= IoIntStatReg then
-
-            io_int_stat_rd_n <= '0';
-
-          elsif dev_adr(16 downto 0) = RstCtrlReg then
-
-            rst_ctrl_rd_n <= '0';
-
-          elsif dev_adr(16 downto 0) = AtcStatusReg then
-
-            atc_stat_rd_n <= '0';
-
-          elsif dev_adr(16 downto 0) = MgmtStatusReg then
-
-            mgmt_stat_rd_n <= '0';
-
-          else
-
-            null;
-							
-          end if;
-
-        else
-
-          null;
-
-        end if;
-
-  end process decoder;
-
-end synthesis;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package decProcs is
-
-  procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
-                    decode: out std_logic_vector(3 downto 0)
-                   );
-end decProcs;
-
-package body decProcs is
-
-  procedure DEC2x4 (inputs : in std_logic_vector(1 downto 0);
-                    decode: out std_logic_vector(3 downto 0)
-                   ) is
-  begin
-    case inputs is
-      when "11" =>
-        decode := "1000";
-      when "10" =>
-        decode := "0100";
-      when "01" =>
-        decode := "0010";
-      when "00" =>
-        decode := "0001";
-      when others =>
-        decode := "0001";
-    end case;
-  end DEC2x4;
-
-end decProcs;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity isa_dec is port
-(
-  dev_adr:         in std_logic_vector(19 downto 0);
-
-  sio_dec_n:       out std_logic;
-  rst_ctrl_rd_n:   out std_logic;
-  atc_stat_rd_n:   out std_logic;
-  mgmt_stat_rd_n:  out std_logic;
-  io_int_stat_rd_n:out std_logic;
-  int_ctrl_rd_n:   out std_logic
-  );
-end isa_dec;
-
-
-architecture synthesis of isa_dec is
-
-  constant  CtrlRegRange: std_logic_vector(2 downto 0)  := "100";
-  constant  SuperIoRange: std_logic_vector(2 downto 0)  := "010";
-
-  constant  IntCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000000";
-  constant  IoIntStatReg: std_logic_vector(16 downto 0) := "00000000000000001";
-  constant  RstCtrlReg:   std_logic_vector(16 downto 0) := "00000000000000010";
-  constant  AtcStatusReg: std_logic_vector(16 downto 0) := "00000000000000011";
-  constant  MgmtStatusReg:std_logic_vector(16 downto 0) := "00000000000000100";
-
-begin
-  with dev_adr(19 downto 17) select
-    sio_dec_n <= '0' when SuperIORange,
-                 '1' when others;
-
-  with dev_adr(19 downto 0) select
-    int_ctrl_rd_n <= '0' when CtrlRegRange & IntCtrlReg,
-                     '1' when others;
-
-  with dev_adr(19 downto 0) select
-    io_int_stat_rd_n <= '0' when CtrlRegRange & IoIntStatReg,
-                        '1' when others;
-
-  with dev_adr(19 downto 0) select
-    rst_ctrl_rd_n <= '0' when CtrlRegRange & RstCtrlReg,
-                     '1' when others;
-
-  with dev_adr(19 downto 0) select
-    atc_stat_rd_n <= '0' when CtrlRegRange & AtcStatusReg,
-                     '1' when others;
-
-  with dev_adr(19 downto 0) select
-    mgmt_stat_rd_n <= '0' when CtrlRegRange & MgmtStatusReg,
-                      '1' when others;
-
-
-end synthesis;
--- Incorporates Errata 5.1 and 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity progPulse is port (
-  clk, reset: in std_logic;
-  loadLength,loadDelay: in std_logic;
-  data: in std_logic_vector(7 downto 0);
-  pulse: out std_logic
-  );
-end progPulse;
-
-architecture rtl of progPulse is
-
-signal delayCnt, pulseCnt: unsigned(7 downto 0);
-signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
-signal startPulse, endPulse: std_logic;
-
-begin
-
-  delayReg: process (clk, reset) begin
-    if reset = '1' then
-      delayCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadDelay = '1' then
-        delayCntVal <= unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  lengthReg: process (clk, reset) begin
-    if reset = '1' then
-      pulseCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadLength = '1' then -- changed loadLength to loadDelay (Errata 5.1)
-        pulseCntVal <= unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  pulseDelay: process (clk, reset) begin
-    if (reset = '1') then
-      delayCnt <= "11111111";
-    elsif(clk'event and clk = '1') then
-      if (loadDelay = '1' or loadLength = '1' or endPulse = '1') then -- changed startPulse to endPulse (Errata 5.1)
-        delayCnt <= delayCntVal;
-      elsif endPulse = '1' then
-        delayCnt <= delayCnt - 1;
-      end if;
-    end if;
-  end process;
-
-  startPulse <= '1' when delayCnt = "00000000" else '0';
-
-  pulseLength: process (clk, reset) begin
-    if (reset = '1') then
-      pulseCnt <= "11111111";
-    elsif (clk'event and clk = '1') then
-      if (loadLength = '1') then
-        pulseCnt <= pulseCntVal;
-      elsif (startPulse = '1' and endPulse = '1') then
-        pulseCnt <= pulseCntVal;
-      elsif (endPulse = '1') then
-        pulseCnt <= pulseCnt;
-      else
-        pulseCnt <= pulseCnt - 1;
-      end if;
-    end if;
-  end process;
-
-  endPulse <= '1' when pulseCnt = "00000000" else '0';
-
-  pulseOutput: process (clk, reset) begin
-    if (reset = '1') then
-      pulse <= '0';
-    elsif (clk'event and clk = '1') then
-      if (startPulse = '1') then
-        pulse <= '1';
-      elsif (endPulse = '1') then
-        pulse <= '0';
-      end if;
-    end if;
-  end process;
-        
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    arst : in std_logic;
-    q: out std_logic;
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    if arst = '1' then
-      q <= '0';
-    elsif clk'event and clk = '1' then
-        q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    a,b,c : in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk, a,b,c) begin
-    if ((a = '1' and b = '1') or c = '1') then
-      q <= '0';
-    elsif clk'event and clk = '1' then
-        q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    a,b,c : in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-signal localRst: std_logic;
-
-begin
-
-  localRst <= '1' when (( a = '1' and b = '1') or c = '1') else '0';
-
-  process (clk, localRst) begin
-    if localRst = '1' then
-      q <= '0';
-    elsif clk'event and clk = '1' then
-        q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    arst: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk, arst) begin
-    if arst = '1' then
-      q <= '0';
-    elsif clk'event and clk = '1' then
-        q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    aset : in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk, aset) begin
-    if aset = '1' then
-      q <= '1';
-    elsif clk'event and clk = '1' then
-        q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d1, d2: in std_logic;
-    clk: in std_logic;
-    arst : in std_logic;
-    q1, q2: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk, arst) begin
-    if arst = '1' then
-      q1 <= '0';
-      q2 <= '1';
-    elsif clk'event and clk = '1' then
-      q1 <= d1;
-      q2 <= d2;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process begin
-    if clk'event and clk = '1' then
-      if en = '1' then
-        q <= d;
-      end if;
-    end if;
-    wait on clk;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFFE is port (
-    d: in std_logic;
-    en: in std_logic;
-    clk: in std_logic;
-    q: out std_logic
-    );
-end DFFE;
-
-architecture rtl of DFFE is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      if en = '1' then
-        q <= d;
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    envector: in std_logic_vector(7 downto 0);
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    if clk'event and clk = '1' then
-      if envector = "10010111" then
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    if clk'event and clk = '1' then
-      if en = '1' then
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFFE_SR is port (
-    d: in std_logic;
-    en: in std_logic;
-    clk: in std_logic;
-    rst: in std_logic;
-    prst: in std_logic;
-    q: out std_logic
-    );
-end DFFE_SR;
-
-architecture rtl of DFFE_SR is
-
-begin
-
-  process (clk, rst, prst) begin
-    if (prst = '1') then
-      q <= '1';
-    elsif (rst = '1') then
-      q <= '0';
-    elsif (clk'event and clk = '1') then
-      if (en = '1') then
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity flipFlop is port (
-  clock, input: in std_logic;
-  ffOut: out std_logic
-  );
-end flipFlop;
-
-architecture simple of flipFlop is
-
-  procedure dff (signal clk: in std_logic;
-                 signal d: in std_logic;
-                 signal q: out std_logic
-                ) is
-  begin
-    if clk'event and clk = '1' then
-      q <= d;
-    end if;
-  end procedure dff;
-
-begin
-
-  dff(clock, input, ffOut);
-
-end simple;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    end: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process begin
-    wait until rising_edge(clk);
-      if en = '1' then
-        q <= d;
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d1, d2: in std_logic;
-    clk: in std_logic;
-    srst : in std_logic;
-    q1, q2: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    if clk'event and clk = '1' then
-      if srst = '1' then
-	q1 <= '0';
-	q2 <= '1';
-      else
-        q1 <= d1;
-        q2 <= d2;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFFE_SR is port (
-    d: in std_logic;
-    en: in std_logic;
-    clk: in std_logic;
-    rst: in std_logic;
-    prst: in std_logic;
-    q: out std_logic
-    );
-end DFFE_SR;
-
-architecture rtl of DFFE_SR is
-
-begin
-
-  process (clk, rst, prst) begin
-    if (rst = '1') then
-      q <= '0';
-    elsif (prst = '1') then
-      q <= '1';
-    elsif (clk'event and clk = '1') then
-      if (en = '1') then
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    srst : in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      if srst = '1' then
-	q <= '0';
-      else
-        q <= d;
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity struct_dffe_sr is port (
-  d: in std_logic;
-  clk: in std_logic;
-  en: in std_logic;
-  rst,prst: in std_logic;
-  q: out std_logic
-  );
-end struct_dffe_sr;
-
-use work.primitive.all;
-
-architecture instance of struct_dffe_sr is
-
-begin
-
-  ff: dffe_sr port map (
-	d => d,
-	clk => clk,
-	en => en,
-        rst => rst,
-        prst => prst,
-	q => q
-    );
-
-end instance;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    srst : in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    if clk'event and clk = '1' then
-      if srst = '1' then
-	q <= '0';
-      else
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity struct_dffe is port (
-  d: in std_logic;
-  clk: in std_logic;
-  en: in std_logic;
-  q: out std_logic
-  );
-end struct_dffe;
-
-use work.primitive.all;
-
-architecture instance of struct_dffe is
-
-begin
-
-  ff: dffe port map (
-	d => d,
-	clk => clk,
-	en => en,
-	q => q
-      );
-
-end instance;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity dffTri is
-  generic (size: integer := 8);
-  port (
-  data: in std_logic_vector(size - 1 downto 0);
-  clock: in std_logic;
-  ff_enable: in std_logic;
-  op_enable: in std_logic;
-  qout: out std_logic_vector(size - 1 downto 0)
-  );
-end dffTri;
-
-architecture parameterize of dffTri is
-
-type tribufType is record
-  ip: std_logic;
-  oe: std_logic;
-  op: std_logic;
-end record;
-
-type tribufArrayType is array (integer range <>) of tribufType;
-
-signal tri: tribufArrayType(size - 1 downto 0);
-
-begin
-
-  g0: for i in 0 to size - 1 generate
-    u1: DFFE port map (data(i), tri(i).ip, ff_enable, clock);
-  end generate;
-
-  g1: for i in 0 to size - 1 generate
-    u2: TRIBUF port map (tri(i).ip, tri(i).oe, tri(i).op);
-    tri(i).oe <= op_enable;
-    qout(i) <= tri(i).op;
-  end generate;
-
-end parameterize;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      if en = '1' then
-        q <= d;
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op: out std_logic bus
-  );
-end TRIBUF;
-
-architecture sequential of TRIBUF is
-
-begin
-
-  enable: process (ip,oe) begin
-    if (oe = '1') then
-      op <= ip;
-    else
-      op <= null;
-    end if;
-  end process;
-
-end sequential;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DLATCHH is port (
-    d: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DLATCHH;
-
-architecture rtl of DLATCHH is
-
-signal qLocal: std_logic;
-
-begin
-
-  qLocal <= d when en = '1' else qLocal;
-
-  q <= qLocal;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DLATCHH is port (
-    d: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DLATCHH;
-
-architecture rtl of DLATCHH is
-
-begin
-
-  process (en, d) begin
-    if en = '1' then
-      q <= d;
-    end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity struct_dlatch is port (
-  d: in std_logic;
-  en: in std_logic;
-  q: out std_logic
-  );
-end struct_dlatch;
-
-use work.primitive.all;
-
-architecture instance of struct_dlatch is
-
-begin
-
-  latch: dlatchh port map (
-	d => d,
-	en => en,
-	q => q
-      );
-
-end instance;
--- Incorporates Errata 5.4
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity downCounter is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  count: out std_logic_vector(3 downto 0)
-  );
-end downCounter;
-
-architecture simple of downCounter is
-
-signal countL: unsigned(3 downto 0);
-signal termCnt: std_logic;
-
-begin
-
-  decrement: process (clk, reset) begin
-    if (reset = '1') then
-      countL <= "1011";          -- Reset to 11
-      termCnt <= '1';
-    elsif(clk'event and clk = '1') then
-      if (termCnt = '1') then
-        countL <= "1011";        -- Count rolls over to 11
-      else
-        countL <= countL - 1;
-      end if;
-
-      if (countL = "0001") then  -- Terminal count decoded 1 cycle earlier
-        termCnt <= '1';
-      else
-        termCnt <= '0';
-      end if;
-    end if;
-  end process;
-  
-  count <= std_logic_vector(countL);
-
-end simple;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity compareDC is port (
-  addressBus: in std_logic_vector(31 downto 0);
-  addressHit: out std_logic
-  );
-end compareDC;
-
-architecture wontWork of compareDC is
-
-begin
-
-  compare: process(addressBus) begin
-    if (addressBus = "011110101011--------------------") then
-      addressHit <= '1';
-    else
-      addressHit <= '0';
-    end if;
-  end process compare;
-
-end wontWork;
-library ieee;
-use ieee.std_logic_1164.all;
-entity encoder is
-        port (invec: in std_logic_vector(7 downto 0);
-              enc_out: out std_logic_vector(2 downto 0)
-             );
-end encoder;
-
-architecture rtl of encoder is
-
-begin
-
-  encode: process (invec) begin
-    case invec is
-      when "00000001" =>
-        enc_out <= "000";
-
-      when "00000010" =>
-        enc_out <= "001";
-
-      when "00000100" =>
-        enc_out <= "010";
-
-      when "00001000" =>
-        enc_out <= "011";
-
-      when "00010000" =>
-        enc_out <= "100";
-
-      when "00100000" =>
-        enc_out <= "101";
-
-      when "01000000" =>
-        enc_out <= "110";
-
-      when "10000000" =>
-        enc_out <= "111";
-
-      when others =>
-        enc_out <= "000";
-
-      end case;
-    end process;
-
-end rtl;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity encoder is
-  port (invec:in std_logic_vector(7 downto 0);
-        enc_out:out  std_logic_vector(2 downto 0)
-       );
-end encoder;
-
-architecture rtl of encoder is
-begin
-  process (invec)
-    begin
-      if invec(7) = '1' then
-        enc_out <= "111";
-
-      elsif invec(6) = '1' then
-        enc_out <= "110";
-
-      elsif invec(5) = '1' then
-        enc_out <= "101";
-
-      elsif invec(4) = '1' then
-        enc_out <= "100";
-
-      elsif invec(3) = '1' then
-        enc_out <= "011";
-
-      elsif invec(2) = '1' then
-        enc_out <= "010";
-
-      elsif invec(1) = '1' then
-        enc_out <= "001";
-
-      elsif invec(0) = '1' then
-        enc_out <= "000";
-
-      else 
-        enc_out <= "000";
-      end if; 
-    end process;
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-entity encoder is
-  port (invec: in std_logic_vector(7 downto 0);
-        enc_out: out std_logic_vector(2 downto 0)
-        );
-end encoder;
-
-architecture rtl of encoder is
-
-begin
-  enc_out <= "111" when invec(7) = '1' else
-             "110" when invec(6) = '1' else
-             "101" when invec(5) = '1' else
-             "100" when invec(4) = '1' else
-             "011" when invec(3) = '1' else
-             "010" when invec(2) = '1' else
-             "001" when invec(1) = '1' else
-             "000" when invec(0) = '1' else
-             "000";
-
-end rtl;
--- includes Errata 5.2
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all; -- errata 5.2
-
-entity compare is port (
-  ina: in std_logic_vector (3 downto 0);
-  inb: in std_logic_vector (2 downto 0);
-  equal: out std_logic
-  );
-end compare;
-
-architecture simple of compare is
-
-begin
-
-  equalProc: process (ina, inb) begin
-    if (ina = inb ) then
-      equal <= '1';
-    else
-      equal <= '0';
-    end if;
-  end process;
-
-end simple;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity LogicFcn is port (
-  A: in std_logic;
-  B: in std_logic;
-  C: in std_logic;
-  Y: out std_logic
-  );
-end LogicFcn;
-
-architecture behavioral of LogicFcn is
-
-begin
-
-  fcn: process (A,B,C) begin
-
-    if (A = '0' and B = '0') then
-      Y <= '1';
-    elsif C = '1' then
-      Y <= '1';
-    else
-      Y <= '0';
-    end if;
-
-  end process;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity LogicFcn is port (
-  A: in std_logic;
-  B: in std_logic;
-  C: in std_logic;
-  Y: out std_logic
-  );
-end LogicFcn;
-
-architecture dataflow of LogicFcn is
-
-begin
-
-  Y <= '1' when (A = '0' AND B = '0') OR
-                (C = '1')
-           else '0';
-
-end dataflow;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.primitive.all;
-
-entity LogicFcn is port (
-  A: in std_logic;
-  B: in std_logic;
-  C: in std_logic;
-  Y: out std_logic
-  );
-end LogicFcn;
-
-architecture structural of LogicFcn is
-
-signal notA, notB, andSignal: std_logic;
-
-begin
-
-  i1: inverter port map (i => A,
-                         o => notA);
-
-  i2: inverter port map (i => B,
-                         o => notB);
-
-  a1: and2 port map (i1 => notA,
-                     i2 => notB,
-                     y => andSignal);
-
-  o1: or2 port map (i1 => andSignal,
-                    i2 => C,
-                    y => Y);
-
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SimDFF is port (
-  D, Clk: in std_logic;
-  Q: out std_logic
-  );
-end SimDff;
-
-architecture SimModel of SimDFF is
-
-constant tCQ: time := 8 ns;
-constant tS:  time := 4 ns;
-constant tH:  time := 3 ns;
-
-begin
-
-  reg: process (Clk, D) begin
-
-    -- Assign output tCQ after rising clock edge
-    if (Clk'event and Clk = '1') then
-      Q <= D after tCQ;
-    end if;
-
-    -- Check setup time
-    if (Clk'event and Clk = '1') then
-      assert (D'last_event >= tS)
-        report "Setup time violation"
-        severity Warning;
-    end if;
-
-    -- Check hold time
-    if (D'event and Clk'stable and Clk = '1') then
-      assert (D'last_event - Clk'last_event > tH)
-        report "Hold Time Violation"
-        severity Warning;
-    end if;
-
-  end process;
-
-end simModel;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process (clk) begin
-    wait until clk = '1';
-      q <= d;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d: in std_logic;
-    clk: in std_logic;
-    q: out std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      q <= d;
-
-    wait on clk;
-  end process;
-
-end rtl;
-configuration SimpleGatesCfg of FEWGATES is
-
-  for structural
-
-    for all: AND2
-      use entity work.and2(rtl);
-    end for;
-
-    for u3: inverter
-      use entity work.inverter(rtl);
-    end for;
-
-    for u4: or2
-      use entity work.or2(rtl);
-    end for;
-
-  end for;
-
-end SimpleGatesCfg;
-configuration SimpleGatesCfg of FEWGATES is
-
-  for structural
-
-    for u1: and2
-      use entity work.and2(rtl);
-    end for;
-
-    for u2: and2
-      use entity work.and2(rtl);
-    end for;
-
-    for u3: inverter
-      use entity work.inverter(rtl);
-    end for;
-
-    for u4: or2
-      use entity work.or2(rtl);
-    end for;
-
-  end for;
-
-end SimpleGatesCfg;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-use work.and2;
-use work.or2;
-use work.inverter;
-
-architecture structural of FEWGATES is
-
-  component AND2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component OR2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component INVERTER port (
-    i: in std_logic;
-    o: out std_logic
-    );
-  end component;
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
-begin
-
-  u1: and2 port map (i1 => a ,
-                     i2 => b,
-                     y => a_and_b
-                     );
-
-  u2: and2 port map (i1 => c,
-                     i2 => d,
-                     y => c_and_d
-                     );
-
-  u3: inverter port map (i => c_and_d,
-                         o => not_c_and_d);
-
-  u4: or2 port map (i1 => a_and_b,
-                    i2 => not_c_and_d,
-                    y => y
-                    );
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-use work.and2;
-use work.or2;
-use work.inverter;
-
-architecture structural of FEWGATES is
-
-  component AND2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component OR2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component INVERTER port (
-    i: in std_logic;
-    o: out std_logic
-    );
-  end component;
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
--- Configution specifications
-
-for all: and2 use entity work.and2(rtl);
-for u3: inverter use entity work.inverter(rtl);
-for u4: or2 use entity work.or2(rtl);
-
-begin
-
-  u1: and2 port map (i1 => a, i2 => b,
-                     y => a_and_b
-                     );
-
-  u2: and2 port map (i1 => c, i2 => d,
-                     y => c_and_d
-                     );
-
-  u3: inverter port map (i => c_and_d,
-                         o => not_c_and_d);
-
-  u4: or2 port map (i1 => a_and_b, i2 => not_c_and_d,
-                    y => y
-                    );
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-use work.GatesPkg.all;
-
-architecture structural of FEWGATES is
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
-begin
-
-  u1: and2 port map (i1 => a ,
-                     i2 => b,
-                     y => a_and_b
-                     );
-
-  u2: and2 port map (i1 => c,
-                     i2 => d,
-                     y => c_and_d
-                     );
-
-  u3: inverter port map (i => c_and_d,
-                         o => not_c_and_d);
-
-  u4: or2 port map (i1 => a_and_b,
-                    i2 => not_c_and_d,
-                    y => y
-                    );
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-architecture concurrent of FEWGATES is
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
-begin
-
-  a_and_b <= '1' when a = '1' and b = '1' else '0';
-  c_and_d <= '1' when c = '1' and d = '1' else '0';
-
-  not_c_and_d <= not c_and_d;
-
-  y <= '1' when a_and_b = '1' or not_c_and_d = '1' else '0';
-
-end concurrent;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package GatesPkg is
-
-  component AND2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component OR2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component INVERTER port (
-    i: in std_logic;
-    o: out std_logic
-    );
-  end component;
-
-end GatesPkg;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-architecture structural of FEWGATES is
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
-begin
-
-  u1: and2 port map (i1 => a ,
-                     i2 => b,
-                     y => a_and_b
-                     );
-
-  u2: and2 port map (i1 =>c,
-                     i2 => d,
-                     y => c_and_d
-                     );
-
-  u3: inverter port map (a => c_and_d,
-                         y => not_c_and_d);
-
-  u4: or2 port map (i1 => a_and_b,
-                    i2 => not_c_and_d,
-                    y => y
-                    );
-
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity AND2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end AND2;
-
-architecture rtl of AND2 is
-
-begin
-
-  y <= '1' when i1 = '1' and i2 = '1' else '0';
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity OR2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end OR2;
-
-architecture rtl of OR2 is
-
-begin
-
-  y <= '1' when i1 = '1' or i2 = '1' else '0';
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity INVERTER is port (
-    i: in std_logic;
-    o: out std_logic
-    );
-end INVERTER;
-
-architecture rtl of INVERTER is
-
-begin
-
-  o <= not i;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity FEWGATES is port (
-  a,b,c,d: in std_logic;
-  y: out std_logic
-  );
-end FEWGATES;
-
-architecture structural of FEWGATES is
-
-  component AND2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component OR2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component INVERTER port (
-    i: in std_logic;
-    o: out std_logic
-    );
-  end component;
-
-signal a_and_b, c_and_d, not_c_and_d: std_logic;
-
-begin
-
-  u1: and2 port map (i1 => a ,
-                     i2 => b,
-                     y => a_and_b
-                     );
-
-  u2: and2 port map (i1 => c,
-                     i2 => d,
-                     y => c_and_d
-                     );
-
-  u3: inverter port map (i => c_and_d,
-                         o => not_c_and_d);
-
-  u4: or2 port map (i1 => a_and_b,
-                    i2 => not_c_and_d,
-                    y => y
-                    );
-end structural;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.simPrimitives.all;
-
-entity simHierarchy is port (
-  A, B, Clk: in std_logic;
-  Y: out std_logic
-  );
-end simHierarchy;
-
-architecture hierarchical of simHierarchy is
-
-signal ADly, BDly, OrGateDly, ClkDly: std_logic;
-signal OrGate, FlopOut: std_logic;
-
-begin
-
-  ADly <= transport A after 2 ns;
-  BDly <= transport B after 2 ns;
-  OrGateDly <= transport OrGate after 1.5 ns;
-  ClkDly <= transport Clk after 1 ns;
-
-  u1: OR2 generic map (tPD => 10 ns)
-          port map ( I1 => ADly,
-                     I2 => BDly,
-                     Y => OrGate
-                   );
-
-  u2: simDFF generic map ( tS => 4 ns,
-                           tH => 3 ns,
-                           tCQ => 8 ns
-                         )
-             port map ( D => OrGateDly,
-                        Clk => ClkDly,
-                        Q => FlopOut
-                      );
-
-  Y <= transport FlopOut after 2 ns;
-
-end hierarchical;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity INVERTER is port (
-    i: in std_logic;
-    o: out std_logic
-    );
-end INVERTER;
-
-architecture rtl of INVERTER is
-
-begin
-
-  o <= not i;
-
-end rtl;
---------------------------------------------------------------------------------
---| File name   : $RCSfile: io1164.vhd $
---| Library     : SUPPORT
---| Revision    : $Revision: 1.1 $
---| Author(s)   : Vantage Analysis Systems, Inc; Des Young
---| Integration : Des Young
---| Creation    : Nov 1995
---| Status      : $State: Exp $
---|
---| Purpose     : IO routines for std_logic_1164.
---| Assumptions : Numbers use radixed character set with no prefix.
---| Limitations : Does not read VHDL pound-radixed numbers.
---| Known Errors: none
---|
---| Description:
---| This is a modified library. The source is basically that donated by
---| Vantage to libutil. Des Young removed std_ulogic_vector support (to
---| conform to synthesizable libraries), and added read_oct/hex to integer.
---|
---| =======================================================================
---| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights
---| reserved. This package is provided by Vantage Analysis Systems.
---| The package may not be sold without the express written consent of
---| Vantage Analysis Systems, Inc.
---|
---| The VHDL for this package may be copied and/or distributed as long as
---| this copyright notice is retained in the source and any modifications
---| are clearly marked in the History: list.
---|
---| Title       : IO1164 package VHDL source
---| Package Name: somelib.IO1164
---| File Name   : io1164.vhdl
---| Author(s)   : dbb
---| Purpose     : * Overloads procedures READ and WRITE for STD_LOGIC types
---|                 in manner consistent with TEXTIO package.
---|               * Provides procedures to read and write logic values as
---|                 binary, octal, or hexadecimal values ('X' as appropriate).
---|                 These should be particularly useful for models
---|                 to read in stimulus as 0/1/x or octal or hex.
---| Subprograms :
---| Notes       : 
---| History     : 1. Donated to libutil by Dave Bernstein 15 Jun 94
---|               2. Removed all std_ulogic_vector support, Des Young, 14 Nov 95
---|                  (This is because that type is not supported for synthesis).
---|               3. Added read_oct/hex to integer, Des Young, 20 Nov 95
---|
---| =======================================================================
---| Extra routines by Des Young, des@alantec.com. 1995. GNU copyright.
---| =======================================================================
---|
---------------------------------------------------------------------------------
-
-library ieee;
-package io1164 is
-
-    --$ !VANTAGE_METACOMMENTS_ON
-    --$ !VANTAGE_DNA_ON
-
-    -- import std_logic package
-    use ieee.std_logic_1164.all;
-
-    -- import textio package
-    use std.textio.all;
-
-    --
-    -- the READ and WRITE procedures act similarly to the procedures in the
-    -- STD.TEXTIO package.  for each type, there are two read procedures and
-    -- one write procedure for converting between character and internal
-    -- representations of values.  each value is represented as the string of
-    -- characters that you would use in VHDL code.  (remember that apostrophes
-    -- and quotation marks are not used.)  input is case-insensitive.  output
-    -- is in upper case.  see the following LRM sections for more information:
-    --
-    --      2.3   - Subprogram Overloading
-    --      3.3   - Access Types             (STD.TEXTIO.LINE is an access type)
-    --      7.3.6 - Allocators               (allocators create access values)
-    --     14.3   - Package TEXTIO
-    --
-
-    -- Note that the procedures for std_ulogic will match calls with the value
-    -- parameter of type std_logic.
-
-    --
-    -- declare READ procedures to overload like in TEXTIO
-    --
-    procedure read(l: inout line; value: out std_ulogic       ; good: out boolean);
-    procedure read(l: inout line; value: out std_ulogic                          );
-    procedure read(l: inout line; value: out std_logic_vector ; good: out boolean);
-    procedure read(l: inout line; value: out std_logic_vector                    );
-
-    --
-    -- declare WRITE procedures to overload like in TEXTIO
-    --
-    procedure write(l        : inout line                  ;
-                    value    : in    std_ulogic            ;
-                    justified: in    side          := right;
-                    field    : in    width         := 0   );
-    procedure write(l        : inout line                  ;
-                    value    : in    std_logic_vector      ;
-                    justified: in    side          := right;
-                    field    : in    width         := 0   );
-
-    --
-    -- declare procedures to convert between logic values and octal
-    -- or hexadecimal ('X' where appropriate).
-    --
-
-    -- octal / std_logic_vector
-    procedure read_oct (l         : inout line                    ;
-                        value     : out   std_logic_vector        ;
-                        good      : out   boolean                );
-    procedure read_oct (l         : inout line                    ;
-                        value     : out   std_logic_vector       );
-    procedure write_oct(l         : inout line                    ;
-                        value     : in    std_logic_vector        ;
-                        justified : in    side            := right;
-                        field     : in    width           := 0   );
-
-    -- hexadecimal / std_logic_vector
-    procedure read_hex (l         : inout line                    ;
-                        value     : out   std_logic_vector        ;
-                        good      : out   boolean                );
-    procedure read_hex (l         : inout line                    ;
-                        value     : out   std_logic_vector       );
-    procedure write_hex(l         : inout line                    ;
-                        value     : in    std_logic_vector        ;
-                        justified : in    side            := right;
-                        field     : in    width           := 0   );
-
-    -- read a number into an integer
-    procedure read_oct(l     : inout line;
-                       value : out   integer;
-                       good  : out   boolean);
-    procedure read_oct(l     : inout line;
-                       value : out   integer);
-    procedure read_hex(l     : inout line;
-                       value : out   integer;
-                       good  : out   boolean);
-    procedure read_hex(l     : inout line;
-                       value : out   integer);
-
-end io1164;
-
---------------------------------------------------------------------------------
---| Copyright (c) 1992-1994 Vantage Analysis Systems, Inc., all rights reserved
---| This package is provided by Vantage Analysis Systems.
---| The package may not be sold without the express written consent of
---| Vantage Analysis Systems, Inc.
---|
---| The VHDL for this package may be copied and/or distributed as long as
---| this copyright notice is retained in the source and any modifications
---| are clearly marked in the History: list.
---|
---| Title       : IO1164 package body VHDL source
---| Package Name: VANTAGE_LOGIC.IO1164
---| File Name   : io1164.vhdl
---| Author(s)   : dbb
---| Purpose     : source for IO1164 package body
---| Subprograms :
---| Notes       : see package declaration
---| History     : see package declaration
---------------------------------------------------------------------------------
-
-package body io1164 is
-
-
-    --$ !VANTAGE_METACOMMENTS_ON
-    --$ !VANTAGE_DNA_ON
-
-    -- define lowercase conversion of characters for canonical comparison
-    type char2char_t is array (character'low to character'high) of character;
-    constant lowcase: char2char_t := (
-        nul, soh, stx, etx, eot, enq, ack, bel,
-        bs,  ht,  lf,  vt,  ff,  cr,  so,  si,
-        dle, dc1, dc2, dc3, dc4, nak, syn, etb,
-        can, em,  sub, esc, fsp, gsp, rsp, usp, 
-
-        ' ', '!', '"', '#', '$', '%', '&', ''',
-        '(', ')', '*', '+', ',', '-', '.', '/',
-        '0', '1', '2', '3', '4', '5', '6', '7',
-        '8', '9', ':', ';', '<', '=', '>', '?',
-
-        '@', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-        'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
-        'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-        'x', 'y', 'z', '[', '\', ']', '^', '_',
-
-        '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
-        'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
-        'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
-        'x', 'y', 'z', '{', '|', '}', '~', del);
-
-    -- define conversions between various types
-
-    -- logic    -> character
-    type f_logic_to_character_t is 
-        array (std_ulogic'low to std_ulogic'high) of character;
-    constant f_logic_to_character : f_logic_to_character_t := 
-        ( 
-          'U' => 'U', 
-          'X' => 'X',
-          '0' => '0',
-          '1' => '1',
-          'Z' => 'Z',
-          'W' => 'W',
-          'L' => 'L',
-          'H' => 'H',
-          '-' => '-'
-        );
-
-    -- character, integer, logic
-
-    constant x_charcode     : integer := -1;
-    constant maxoct_charcode: integer := 7;
-    constant maxhex_charcode: integer := 15;
-    constant bad_charcode   : integer := integer'left;
-
-    type digit2int_t is 
-        array ( character'low to character'high ) of integer;
-    constant octdigit2int: digit2int_t := (
-          '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
-          '5' => 5, '6' => 6, '7' => 7,
-          'X' | 'x' => x_charcode, others => bad_charcode );
-    constant hexdigit2int: digit2int_t := (
-          '0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4,
-          '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 
-          'A' | 'a' => 10, 'B' | 'b' => 11, 'C' | 'c' => 12,
-          'D' | 'd' => 13, 'E' | 'e' => 14, 'F' | 'f' => 15,
-          'X' | 'x' => x_charcode, others => bad_charcode  );
-
-    constant oct_bits_per_digit: integer := 3;
-    constant hex_bits_per_digit: integer := 4;
-
-    type     int2octdigit_t is 
-        array ( 0 to maxoct_charcode ) of character;
-    constant int2octdigit: int2octdigit_t :=
-        (  0 => '0',  1 => '1',  2 => '2',  3 => '3',
-           4 => '4',  5 => '5',  6 => '6',  7 => '7' );
-
-    type     int2hexdigit_t is 
-        array ( 0 to maxhex_charcode ) of character;
-    constant int2hexdigit: int2hexdigit_t :=
-        (  0 => '0',  1 => '1',  2 => '2',  3 => '3',
-           4 => '4',  5 => '5',  6 => '6',  7 => '7',
-           8 => '8',  9 => '9', 10 => 'A', 11 => 'B',
-          12 => 'C', 13 => 'D', 14 => 'E', 15 => 'F' );
-
-    type     oct_logic_vector_t is
-        array(1 to oct_bits_per_digit) of std_ulogic;
-    type     octint2logic_t is 
-        array (x_charcode to maxoct_charcode) of oct_logic_vector_t;
-    constant octint2logic  : octint2logic_t := (
-        ( 'X', 'X', 'X' ),
-        ( '0', '0', '0' ),
-        ( '0', '0', '1' ),
-        ( '0', '1', '0' ),
-        ( '0', '1', '1' ),
-        ( '1', '0', '0' ),
-        ( '1', '0', '1' ),
-        ( '1', '1', '0' ),
-        ( '1', '1', '1' )
-    );
-
-    type     hex_logic_vector_t is
-        array(1 to hex_bits_per_digit) of std_ulogic;
-    type     hexint2logic_t is 
-        array (x_charcode to maxhex_charcode) of hex_logic_vector_t;
-    constant hexint2logic  : hexint2logic_t := (
-        ( 'X', 'X', 'X', 'X' ),
-        ( '0', '0', '0', '0' ),
-        ( '0', '0', '0', '1' ),
-        ( '0', '0', '1', '0' ),
-        ( '0', '0', '1', '1' ),
-        ( '0', '1', '0', '0' ),
-        ( '0', '1', '0', '1' ),
-        ( '0', '1', '1', '0' ),
-        ( '0', '1', '1', '1' ),
-        ( '1', '0', '0', '0' ),
-        ( '1', '0', '0', '1' ),
-        ( '1', '0', '1', '0' ),
-        ( '1', '0', '1', '1' ),
-        ( '1', '1', '0', '0' ),
-        ( '1', '1', '0', '1' ),
-        ( '1', '1', '1', '0' ),
-        ( '1', '1', '1', '1' )
-    );
-
-    ----------------------------------------------------------------------------
-    -- READ procedure bodies
-    --
-    --     The strategy for duplicating TEXTIO's overloading of procedures
-    --     with and without GOOD parameters is to put all the logic in the
-    --     version with the GOOD parameter and to have the version without
-    --     GOOD approximate a runtime error by use of an assertion.
-    --
-    ----------------------------------------------------------------------------
-
-    --
-    -- std_ulogic
-    --     note: compatible with std_logic
-    --
-
-    procedure read( l: inout line; value: out std_ulogic; good : out boolean ) is
-
-        variable c      : character;        -- char read while looping
-        variable m      : line;             -- safe copy of L
-        variable success: boolean := false; -- readable version of GOOD
-        variable done   : boolean := false; -- flag to say done reading chars
-
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     if there are characters in the line
-        --         save a copy of the line
-        --         get the next character
-        --         if got one
-        --             set value
-        --         if all ok
-        --             free temp copy
-        --         else
-        --             free passed in line
-        --             assign copy back to line
-        --         set GOOD
-        --     
-
-        -- only operate on lines that contain characters
-        if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-
-            -- save a copy of string in case read fails
-            m := new string'( l.all );
-    
-            -- grab the next character
-            read( l, c, success );
-
-            -- if read ok    
-            if success then
-
---
--- an issue here is whether lower-case values should be accepted or not
---
-
-                -- determine the value    
-                case c is
-                    when 'U' | 'u' => value := 'U';
-                    when 'X' | 'x' => value := 'X';
-                    when '0'       => value := '0';
-                    when '1'       => value := '1';
-                    when 'Z' | 'z' => value := 'Z';
-                    when 'W' | 'w' => value := 'W';
-                    when 'L' | 'l' => value := 'L';
-                    when 'H' | 'h' => value := 'H';
-                    when '-'       => value := '-';
-                    when others    => success := false;
-                end case;
-
-            end if;
-
-            -- free working storage
-            if success then
-                deallocate( m );
-            else
-                deallocate( l );
-                l := m;
-            end if;
-
-        end if; -- non null access, non empty string
-
-        -- set output parameter
-        good := success;
-
-    end read;
-
-    procedure read( l: inout line; value: out std_ulogic ) is
-        variable success: boolean;  -- internal good flag
-    begin
-        read( l, value, success );  -- use safe version
-        assert success 
-            report "IO1164.READ: Unable to read STD_ULOGIC value." 
-            severity error;
-    end read;
-
-    --
-    -- std_logic_vector
-    --     note: NOT compatible with std_ulogic_vector
-    --
-
-    procedure read(l    : inout line           ; 
-                   value: out   std_logic_vector;
-                   good : out   boolean        ) is
-
-        variable m           : line           ; -- saved copy of L
-        variable success     : boolean := true; -- readable GOOD
-        variable logic_value : std_logic      ; -- value for one array element
-        variable c           : character      ; -- read a character
-
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     this procedure strips off leading whitespace, and then calls the
-        --     READ procedure for each single logic value element in the output
-        --     array.
-        --     
-
-        -- only operate on lines that contain characters
-        if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-
-            -- save a copy of string in case read fails
-            m := new string'( l.all );
-
-            -- loop for each element in output array
-            for i in value'range loop
-
-                -- prohibit internal blanks
-                if i /= value'left then
-                    if l.all'length = 0 then
-                        success := false;
-                        exit;
-                    end if;
-                    c := l.all(l.all'left);
-                    if c = ' ' or c = ht then
-                        success := false;
-                        exit;
-                    end if;
-                end if;
-
-                -- read the next logic value
-                read( l, logic_value, success );
-
-                -- stuff the value in if ok, else bail out
-                if success then
-                    value( i ) := logic_value;
-                else
-                    exit;
-                end if;
-
-            end loop; -- each element in output array
-
-            -- free working storage
-            if success then
-                deallocate( m );
-            else
-                deallocate( l );
-                l := m;
-            end if;
-
-        elsif ( value'length /= 0 ) then
-            -- string is empty but the  return array has 1+ elements
-            success := false;
-        end if;
-
-        -- set output parameter
-        good := success;
-
-    end read;
-
-    procedure read(l: inout line; value: out std_logic_vector ) is
-        variable success: boolean;
-    begin
-        read( l, value, success );
-        assert success 
-            report "IO1164.READ: Unable to read T_WLOGIC_VECTOR value." 
-            severity error;
-    end read;
-
-    ----------------------------------------------------------------------------
-    -- WRITE procedure bodies
-    ----------------------------------------------------------------------------
-
-    --
-    -- std_ulogic
-    --     note: compatible with std_logic
-    --
-
-    procedure write(l        : inout line          ;
-                    value    : in    std_ulogic    ;
-                    justified: in    side  := right;
-                    field    : in    width := 0    ) is
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     just write out the string associated with the enumerated
-        --     value.
-        --     
-
-        case value is
-            when 'U' => write( l, character'('U'), justified, field );
-            when 'X' => write( l, character'('X'), justified, field );
-            when '0' => write( l, character'('0'), justified, field );
-            when '1' => write( l, character'('1'), justified, field );
-            when 'Z' => write( l, character'('Z'), justified, field );
-            when 'W' => write( l, character'('W'), justified, field );
-            when 'L' => write( l, character'('L'), justified, field );
-            when 'H' => write( l, character'('H'), justified, field );
-            when '-' => write( l, character'('-'), justified, field );
-        end case;
-    end write;
-
-    --
-    -- std_logic_vector
-    --     note: NOT compatible with std_ulogic_vector
-    --
-
-    procedure write(l        : inout line                   ;
-                    value    : in    std_logic_vector       ;
-                    justified: in    side           := right;
-                    field    : in    width          := 0    ) is
-
-        variable m: line; -- build up intermediate string
-
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     for each value in array
-        --         add string representing value to intermediate string
-        --     write intermediate string to line parameter
-        --     free intermediate string
-        --     
-
-        -- for each value in array
-        for i in value'range loop
-
-            -- add string representing value to intermediate string
-            write( m, value( i ) );
-
-        end loop;
-
-        -- write intermediate string to line parameter
-        write( l, m.all, justified, field );
-
-        -- free intermediate string
-        deallocate( m );
-
-    end write;
-
-
---------------------------------------------------------------------------------
-
-    ----------------------------------------------------------------------------
-    -- procedure bodies for octal and hexadecimal read and write
-    ----------------------------------------------------------------------------
-
-    --
-    -- std_logic_vector/octal
-    --     note: NOT compatible with std_ulogic_vector
-    --
-
-    procedure read_oct(l         : inout line            ; 
-                       value     : out   std_logic_vector; 
-                       good      : out   boolean         ) is
-
-        variable m               : line                      ; -- safe L
-        variable success         : boolean            := true; -- readable GOOD
-        variable logic_value     : std_logic                 ; -- elem value
-        variable c               : character                 ; -- char read
-        variable charcode        : integer                   ; -- char->int
-        variable oct_logic_vector: oct_logic_vector_t        ; -- for 1 digit
-        variable bitpos          : integer                   ; -- in state vec.
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     skip over leading blanks, then read a digit
-        --     and do a conversion into a logic value
-        --     for each element in array
-        --     
-
-        -- make sure logic array is right size to read this base
-        success := ( ( value'length rem oct_bits_per_digit ) = 0 );
-        if success then
-
-            -- only operate on non-empty strings
-            if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-
-                -- save old copy of string in case read fails
-                m := new string'( l.all );
-
-                -- pick off leading white space and get first significant char
-                c := ' ';
-                while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
-                    read( l, c, success );
-                end loop;
-
-                -- turn character into integer
-                charcode := octdigit2int( c );
-
-                -- not doing any bits yet
-                bitpos := 0;
-
-                -- check for bad first character
-                if charcode = bad_charcode then
-                    success := false;
-                else
-                    -- loop through each value in array
-                    oct_logic_vector := octint2logic( charcode );
-                    for i in value'range loop
-    
-                        -- doing the next bit
-                        bitpos := bitpos + 1;
-    
-                        -- stick the value in
-                        value( i ) := oct_logic_vector( bitpos );
-                        
-                        -- read the next character if we're not at array end
-                        if ( bitpos = oct_bits_per_digit ) and ( i /= value'right ) then
-                            read( l, c, success );
-                            if not success then
-                                exit;
-                            end if;
-                            -- turn character into integer
-                            charcode := octdigit2int( c );
-                            -- check for bad char
-                            if charcode = bad_charcode then
-                                success := false;
-                                exit;
-                            end if;
-                            -- reset bit position
-                            bitpos := 0;
-                            -- turn character code into state array 
-                            oct_logic_vector := octint2logic( charcode );
-                        end if;
-                        
-                    end loop; -- each index in return array
- 
-                end if; -- if bad first character
-
-                -- clean up working storage
-                if success then
-                    deallocate( m );
-                else
-                    deallocate( l );
-                    l := m;
-                end if;
-
-            -- no characters to read for return array that isn't null slice
-            elsif ( value'length /= 0 ) then
-                success := false;
-            end if; -- non null access, non empty string
-
-        end if;
-
-        -- set out parameter of success
-        good := success;
-
-    end read_oct;
-
-
-    procedure read_oct(l         : inout line            ; 
-                       value     : out   std_logic_vector) is
-        variable success: boolean;                 -- internal good flag
-    begin                                                              
-        read_oct( l, value, success ); -- use safe version  
-        assert success 
-            report "IO1164.READ_OCT: Unable to read T_LOGIC_VECTOR value." 
-            severity error;
-    end read_oct;
-
-    procedure write_oct(l        : inout line                   ;
-                        value    : in    std_logic_vector       ;
-                        justified: in    side           := right;
-                        field    : in    width          := 0    ) is
-
-        variable m            : line     ; -- safe copy of L
-        variable goodlength   : boolean  ; -- array is ok len for this base
-        variable isx          : boolean  ; -- an X in this digit
-        variable integer_value: integer  ; -- accumulate integer value
-        variable c            : character; -- character read
-        variable charpos      : integer  ; -- index string being contructed
-        variable bitpos       : integer  ; -- bit index inside digit
-
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        -- make sure this array can be written in this base
-        -- create a string to place intermediate results
-        -- initialize counters and flags to beginning of string
-        -- for each item in array
-        --     note unknown, else accumulate logic into integer
-        --         if at this digit's last bit
-        --             stuff digit just computed into intermediate result
-        --             reset flags and counters except for charpos
-        -- write intermediate result into line
-        -- free work storage
-        --     
-
-        -- make sure this array can be written in this base
-        goodlength := ( ( value'length rem oct_bits_per_digit ) = 0 );
-        assert goodlength
-            report "IO1164.WRITE_OCT: VALUE'Length is not a multiple of 3."
-            severity error;
-        if goodlength then
-
-            -- create a string to place intermediate results
-            m := new string(1 to ( value'length / oct_bits_per_digit ) );
-
-            -- initialize counters and flags to beginning of string
-            charpos := 0;
-            bitpos := 0;
-            isx := false;
-            integer_value := 0;
-
-            -- for each item in array
-            for i in value'range loop
-
-                -- note unknown, else accumulate logic into integer
-                case value(i) is
-                    when '0' | 'L' =>
-                        integer_value := integer_value * 2;
-                    when '1' | 'H' =>
-                        integer_value := ( integer_value * 2 ) + 1;
-                    when others =>
-                        isx := true;
-                end case;
-
-                -- see if we've done this digit's last bit
-                bitpos := bitpos + 1;
-                if bitpos = oct_bits_per_digit then
-
-                    -- stuff the digit just computed into the intermediate result
-                    charpos := charpos + 1;
-                    if isx then
-                        m.all(charpos) := 'X';
-                    else
-                        m.all(charpos) := int2octdigit( integer_value );
-                    end if;
-
-                    -- reset flags and counters except for location in string being constructed
-                    bitpos := 0;
-                    isx := false;
-                    integer_value := 0;
-
-                end if;
-
-            end loop;
-
-            -- write intermediate result into line
-            write( l, m.all, justified, field );
-
-            -- free work storage
-            deallocate( m );
-
-        end if;
-
-    end write_oct;
-
-    --
-    -- std_logic_vector/hexadecimal
-    --     note: NOT compatible with std_ulogic_vector
-    --
-
-    procedure read_hex(l         : inout line            ; 
-                       value     : out   std_logic_vector; 
-                       good      : out   boolean         ) is
-
-        variable m               : line                      ; -- safe L
-        variable success         : boolean            := true; -- readable GOOD
-        variable logic_value     : std_logic                 ; -- elem value
-        variable c               : character                 ; -- char read
-        variable charcode        : integer                   ; -- char->int
-        variable hex_logic_vector: hex_logic_vector_t        ; -- for 1 digit
-        variable bitpos          : integer                   ; -- in state vec.
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        --     skip over leading blanks, then read a digit
-        --     and do a conversion into a logic value
-        --     for each element in array
-        --     
-
-        -- make sure logic array is right size to read this base
-        success := ( ( value'length rem hex_bits_per_digit ) = 0 );
-        if success then
-
-            -- only operate on non-empty strings
-            if ( ( l /= null ) and ( l.all'length /= 0 ) ) then
-
-                -- save old copy of string in case read fails
-                m := new string'( l.all );
-
-                -- pick off leading white space and get first significant char
-                c := ' ';
-                while success and ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = ht ) ) loop
-                    read( l, c, success );
-                end loop;
-
-                -- turn character into integer
-                charcode := hexdigit2int( c );
-
-                -- not doing any bits yet
-                bitpos := 0;
-
-                -- check for bad first character
-                if charcode = bad_charcode then
-                    success := false;
-                else
-                    -- loop through each value in array
-                    hex_logic_vector := hexint2logic( charcode );
-                    for i in value'range loop
-    
-                        -- doing the next bit
-                        bitpos := bitpos + 1;
-    
-                        -- stick the value in
-                        value( i ) := hex_logic_vector( bitpos );
-                        
-                        -- read the next character if we're not at array end
-                        if ( bitpos = hex_bits_per_digit ) and ( i /= value'right ) then
-                            read( l, c, success );
-                            if not success then
-                                exit;
-                            end if;
-                            -- turn character into integer
-                            charcode := hexdigit2int( c );
-                            -- check for bad char
-                            if charcode = bad_charcode then
-                                success := false;
-                                exit;
-                            end if;
-                            -- reset bit position
-                            bitpos := 0;
-                            -- turn character code into state array 
-                            hex_logic_vector := hexint2logic( charcode );
-                        end if;
-                        
-                    end loop; -- each index in return array
- 
-                end if; -- if bad first character
-
-                -- clean up working storage
-                if success then
-                    deallocate( m );
-                else
-                    deallocate( l );
-                    l := m;
-                end if;
-
-            -- no characters to read for return array that isn't null slice
-            elsif ( value'length /= 0 ) then
-                success := false;
-            end if; -- non null access, non empty string
-
-        end if;
-
-        -- set out parameter of success
-        good := success;
-
-    end read_hex;
-
-
-    procedure read_hex(l         : inout line            ; 
-                       value     : out   std_logic_vector) is
-        variable success: boolean;                 -- internal good flag
-    begin                                                              
-        read_hex( l, value, success ); -- use safe version  
-        assert success 
-            report "IO1164.READ_HEX: Unable to read T_LOGIC_VECTOR value." 
-            severity error;
-    end read_hex;
-
-    procedure write_hex(l        : inout line                   ;
-                        value    : in    std_logic_vector       ;
-                        justified: in    side           := right;
-                        field    : in    width          := 0    ) is
-
-        variable m            : line     ; -- safe copy of L
-        variable goodlength   : boolean  ; -- array is ok len for this base
-        variable isx          : boolean  ; -- an X in this digit
-        variable integer_value: integer  ; -- accumulate integer value
-        variable c            : character; -- character read
-        variable charpos      : integer  ; -- index string being contructed
-        variable bitpos       : integer  ; -- bit index inside digit
-
-    begin
-
-        --
-        -- algorithm:
-        -- 
-        -- make sure this array can be written in this base
-        -- create a string to place intermediate results
-        -- initialize counters and flags to beginning of string
-        -- for each item in array
-        --     note unknown, else accumulate logic into integer
-        --         if at this digit's last bit
-        --             stuff digit just computed into intermediate result
-        --             reset flags and counters except for charpos
-        -- write intermediate result into line
-        -- free work storage
-        --     
-
-        -- make sure this array can be written in this base
-        goodlength := ( ( value'length rem hex_bits_per_digit ) = 0 );
-        assert goodlength
-            report "IO1164.WRITE_HEX: VALUE'Length is not a multiple of 4."
-            severity error;
-        if goodlength then
-
-            -- create a string to place intermediate results
-            m := new string(1 to ( value'length / hex_bits_per_digit ) );
-
-            -- initialize counters and flags to beginning of string
-            charpos := 0;
-            bitpos := 0;
-            isx := false;
-            integer_value := 0;
-
-            -- for each item in array
-            for i in value'range loop
-
-                -- note unknown, else accumulate logic into integer
-                case value(i) is
-                    when '0' | 'L' =>
-                        integer_value := integer_value * 2;
-                    when '1' | 'H' =>
-                        integer_value := ( integer_value * 2 ) + 1;
-                    when others =>
-                        isx := true;
-                end case;
-
-                -- see if we've done this digit's last bit
-                bitpos := bitpos + 1;
-                if bitpos = hex_bits_per_digit then
-
-                    -- stuff the digit just computed into the intermediate result
-                    charpos := charpos + 1;
-                    if isx then
-                        m.all(charpos) := 'X';
-                    else
-                        m.all(charpos) := int2hexdigit( integer_value );
-                    end if;
-
-                    -- reset flags and counters except for location in string being constructed
-                    bitpos := 0;
-                    isx := false;
-                    integer_value := 0;
-
-                end if;
-
-            end loop;
-
-            -- write intermediate result into line
-            write( l, m.all, justified, field );
-
-            -- free work storage
-            deallocate( m );
-
-        end if;
-
-    end write_hex;
-
-------------------------------------------------------------------------------
-
-    ------------------------------------
-    -- Read octal/hex numbers to integer
-    ------------------------------------
-
-    --
-    -- Read octal to integer
-    --
-    
-    procedure read_oct(l     : inout line;
-                       value : out integer;
-                       good  : out boolean) is
-
-        variable pos     : integer;
-        variable digit   : integer;
-        variable result  : integer := 0;
-        variable success : boolean := true;
-        variable c       : character;
-        variable old_l   : line := l;
-
-    begin
-        -- algorithm:
-        --
-        --  skip leading white space, read digit, convert
-        --  into integer
-        --
-        if (l /= NULL) then
-            -- set pos to start of actual number by skipping white space
-            pos := l'LEFT;
-            c := l(pos);
-            while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
-                pos := pos + 1;
-                c := l(pos);
-            end loop;
-            
-            -- check for start of valid number
-            digit := octdigit2int(l(pos));
-
-            if ((digit = bad_charcode) or (digit = x_charcode)) then
-                good := FALSE;
-                return;
-            else
-                -- calculate integer value
-                for i in pos to l'RIGHT loop
-                    digit := octdigit2int(l(pos));
-                    exit when (digit = bad_charcode) or (digit = x_charcode);
-                    result := (result * 8) + digit;
-                    pos := pos + 1;
-                end loop;
-                value := result;
-                -- shrink line
-                if (pos > 1) then
-                    l := new string'(old_l(pos to old_l'HIGH));
-                    deallocate(old_l);
-                end if;
-                good := TRUE;
-                return;
-            end if;
-        else
-            good := FALSE;
-        end if;
-
-    end read_oct;
-
-    -- simple version
-    procedure read_oct(l     : inout line;
-                       value : out   integer) is
-
-        variable success: boolean;                 -- internal good flag
-
-    begin                                                              
-        read_oct( l, value, success ); -- use safe version  
-        assert success 
-            report "IO1164.READ_OCT: Unable to read octal integer value." 
-            severity error;
-    end read_oct;
-
-
-    --
-    -- Read hex to integer
-    --
-    
-    procedure read_hex(l     : inout line;
-                       value : out integer;
-                       good  : out boolean) is
-
-        variable pos     : integer;
-        variable digit   : integer;
-        variable result  : integer := 0;
-        variable success : boolean := true;
-        variable c       : character;
-        variable old_l   : line := l;
-
-    begin
-        -- algorithm:
-        --
-        --  skip leading white space, read digit, convert
-        --  into integer
-        --
-        if (l /= NULL) then
-            -- set pos to start of actual number by skipping white space
-            pos := l'LEFT;
-            c := l(pos);
-            while ( l.all'length > 0 ) and ( ( c = ' ' ) or ( c = HT ) ) loop
-                pos := pos + 1;
-                c := l(pos);
-            end loop;
-            
-            -- check for start of valid number
-            digit := hexdigit2int(l(pos));
-
-            if ((digit = bad_charcode) or (digit = x_charcode)) then
-                good := FALSE;
-                return;
-            else
-                -- calculate integer value
-                for i in pos to l'RIGHT loop
-                    digit := hexdigit2int(l(pos));
-                    exit when (digit = bad_charcode) or (digit = x_charcode);
-                    result := (result * 16) + digit;
-                    pos := pos + 1;
-                end loop;
-                value := result;
-                -- shrink line
-                if (pos > 1) then
-                    l := new string'(old_l(pos to old_l'HIGH));
-                    deallocate(old_l);
-                end if;
-                good := TRUE;
-                return;
-            end if;
-        else
-            good := FALSE;
-        end if;
-
-    end read_hex;
-
-    -- simple version
-    procedure read_hex(l     : inout line;
-                       value : out   integer) is
-
-        variable success: boolean;                 -- internal good flag
-
-    begin                                                              
-        read_hex( l, value, success ); -- use safe version  
-        assert success 
-            report "IO1164.READ_HEX: Unable to read hex integer value." 
-            severity error;
-    end read_hex;
-
-end io1164;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity asyncLdCnt is port (
-  loadVal: in std_logic_vector(3 downto 0);
-  clk, load: in std_logic;
-  q: out std_logic_vector(3 downto 0)
-  );
-end asyncLdCnt;
-
-architecture rtl of asyncLdCnt is
-
-signal qLocal: unsigned(3 downto 0);
-
-begin
-
-  process (clk, load, loadVal) begin
-    if (load = '1') then
-      qLocal <= to_unsigned(loadVal);
-    elsif (clk'event and clk = '1' ) then
-      qLocal <= qLocal + 1;
-    end if;
-  end process;
-
-  q <= to_stdlogicvector(qLocal);
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity LoadCnt is port (
-  CntEn: in std_logic;
-  LdCnt: in std_logic;
-  LdData: in std_logic_vector(3 downto 0);
-  Clk: in std_logic;
-  Rst: in std_logic;
-  CntVal: out std_logic_vector(3 downto 0)
-  );
-end LoadCnt;
-
-architecture behavioral of LoadCnt is
-
-signal Cnt: std_logic_vector(3 downto 0);
-
-begin
-
-  counter: process (Clk, Rst) begin
-    if Rst = '1' then
-      Cnt <= (others => '0');
-    elsif (Clk'event and Clk = '1') then
-      if (LdCnt = '1') then
-        Cnt <= LdData;
-      elsif (CntEn = '1') then
-        Cnt <= Cnt + 1;
-      else
-        Cnt <= Cnt;
-      end if;
-    end if;
-  end process;
-
-  CntVal <= Cnt;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-library UTILS;
-use UTILS.io1164.all;
-use std.textio.all;
-
-entity loadCntTB is
-end loadCntTB;
-
-architecture testbench of loadCntTB is
-
-  component loadCnt port (
-    data: in std_logic_vector (7 downto 0);
-    load: in std_logic;
-    clk: in std_logic;
-    rst: in std_logic;
-    q: out std_logic_vector (7 downto 0)
-    );
-  end component;
-
-file vectorFile: text is in "vectorfile";
-type vectorType is record
-  data: std_logic_vector(7 downto 0);
-  load: std_logic;
-  rst: std_logic;
-  q: std_logic_vector(7 downto 0);
-end record;
-
-signal testVector: vectorType;
-signal TestClk: std_logic := '0';
-signal Qout: std_logic_vector(7 downto 0);
-
-constant ClkPeriod: time := 100 ns;
-
-for all: loadCnt use entity work.loadcnt(rtl);
-
-begin
-
--- File reading and stimulus application
-  readVec: process
-    variable VectorLine: line;
-    variable VectorValid: boolean;
-    variable vRst: std_logic;
-    variable vLoad: std_logic;
-    variable vData: std_logic_vector(7 downto 0);
-    variable vQ: std_logic_vector(7 downto 0);
-    
-  begin
-    while not endfile (vectorFile) loop
-      readline(vectorFile, VectorLine);
-
-      read(VectorLine, vRst, good => VectorValid);
-      next when not VectorValid;
-      read(VectorLine, vLoad);
-      read(VectorLine, vData);
-      read(VectorLine, vQ);
-
-      wait for ClkPeriod/4;
-
-      testVector.Rst <= vRst;
-      testVector.Load <= vLoad;
-      testVector.Data <= vData;
-      testVector.Q <= vQ;
-
-      wait for (ClkPeriod/4) * 3;
-
-    end loop;
-
-  assert false
-    report "Simulation complete"
-    severity note;
-
-  wait;
-
-  end process;
-
--- Free running test clock
-  TestClk <= not TestClk after ClkPeriod/2;
-
--- Instance of design being tested
-  u1: loadCnt port map (Data => testVector.Data,
-                        load => testVector.Load,
-                        clk => TestClk,
-                        rst => testVector.Rst,
-                        q => Qout
-                       );
-
--- Process to verify outputs
-  verify: process (TestClk)
-  variable ErrorMsg: line;
-  begin
-    if (TestClk'event and TestClk = '0') then
-      if Qout /= testVector.Q then
-        write(ErrorMsg, string'("Vector failed "));
-        write(ErrorMsg, now);
-        writeline(output, ErrorMsg);
-      end if;
-    end if;
-  end process;
-                        
-
-end testbench;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity loadCnt is port (
-  data: in std_logic_vector (7 downto 0);
-  load: in std_logic;
-  clk: in std_logic;
-  rst: in std_logic;
-  q: out std_logic_vector (7 downto 0)
-  );
-end loadCnt;
-
-architecture rtl of loadCnt is
-
-signal cnt: std_logic_vector (7 downto 0);
-
-begin
-
-  counter: process (clk, rst) begin
-    if (rst = '1') then
-      cnt <= (others => '0');
-    elsif (clk'event and clk = '1') then
-      if (load = '1') then
-        cnt <= data;
-      else
-        cnt <= cnt + 1;
-      end if;
-    end if;
-  end process;
-
-  q <= cnt;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity multiplier is port (
-  a,b : in std_logic_vector (15 downto 0);
-  product: out std_logic_vector (31 downto 0)
-  );
-end multiplier;
-
-architecture dataflow of multiplier is
-
-begin
-
-  product <= a * b;
-
-end dataflow;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity mux is port (
-  A, B, Sel: in std_logic;
-  Y: out std_logic
-  );
-end mux;
-
-architecture simModel of mux is
-
--- Delay Constants
-constant tPD_A:   time := 10 ns;
-constant tPD_B:   time := 15 ns;
-constant tPD_Sel: time := 5 ns;
-
-begin
-
-  DelayMux: process (A, B, Sel)
-
-  variable localY: std_logic; -- Zero delay place holder for Y
-
-  begin
-
-  -- Zero delay model
-    case Sel is
-      when '0' =>
-        localY := A;
-      when others =>
-        localY := B;
-    end case;
-
-  -- Delay calculation
-    if (B'event) then
-      Y <= localY after tPD_B;
-    elsif (A'event) then
-      Y <= localY after tPD_A;
-    else
-      Y <= localY after tPD_Sel;
-    end if;
-
-  end process;
-
-
-end simModel;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity ForceShare is port (
-  a,b,c,d,e,f: in std_logic_vector (7 downto 0);
-  result: out std_logic_vector(7 downto 0)
-  );
-end ForceShare;
-
-architecture behaviour of ForceShare is
-
-begin
-
-  sum: process (a,c,b,d,e,f)
-  begin
-
-    if (a + b = "10011010") then
-      result <= c;
-    elsif (a + b = "01011001") then
-          result <= d;
-    elsif (a + b = "10111011") then
-      result <= e;
-    else
-      result <= f;
-    end if;
-  end process;
-
-end behaviour;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF8 is port (
-  ip: in std_logic_vector(7 downto 0);
-  oe: in std_logic;
-  op: out std_logic_vector(7 downto 0)
-  );
-end TRIBUF8;
-
-architecture concurrent of TRIBUF8 is
-
-begin
-
-  op <= ip when oe = '1' else (others => 'Z');
-
-end concurrent;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op: out std_logic
-  );
-end TRIBUF;
-
-architecture concurrent of TRIBUF is
-
-begin
-
-  op <= ip when oe = '1' else 'Z';
-
-end concurrent;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF8 is port (
-  ip: in std_logic_vector(7 downto 0);
-  oe: in std_logic;
-  op: out std_logic_vector(7 downto 0)
-  );
-end TRIBUF8;
-
-architecture sequential of TRIBUF8 is
-
-begin
-
-  enable: process (ip,oe) begin
-    if (oe = '1') then
-      op <= ip;
-    else
-      op <= (others => 'Z');
-    end if;
-  end process;
-
-end sequential;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF is port (
-  ip: in bit;
-  oe: in bit;
-  op: out bit
-  );
-end TRIBUF;
-
-architecture sequential of TRIBUF is
-
-begin
-
-  enable: process (ip,oe) begin
-    if (oe = '1') then
-      op <= ip;
-    else
-      op <= null;
-    end if;
-  end process;
-
-end sequential;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op: out std_logic
-  );
-end TRIBUF;
-
-architecture sequential of TRIBUF is
-
-begin
-
-  enable: process (ip,oe) begin
-    if (oe = '1') then
-      op <= ip;
-    else
-      op <= 'Z';
-    end if;
-  end process;
-
-end sequential;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity tribuffer is port (
-  input: in std_logic;
-  enable: in std_logic;
-  output: out std_logic
-  );
-end tribuffer;
-
-architecture structural of tribuffer is
-
-begin
-
-  u1: tribuf port map (ip => input,
-                       oe => enable,
-                       op => output
-                      );
-
-end structural;
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity oddParityGen is
-  generic ( width : integer := 8 );
-  port (ad: in std_logic_vector (width - 1 downto 0);
-        oddParity : out std_logic ) ;
-end oddParityGen; 
-
-architecture scaleable of oddParityGen is
-
-signal genXor: std_logic_vector(ad'range);
-
-begin
-
-  genXOR(0) <= '0';
-
-  parTree: for i in 1 to ad'high generate
-    x1: xor2 port map (i1 => genXor(i - 1),
-                       i2 => ad(i - 1),
-                       y  => genXor(i)
-                      );
-  end generate;
-
- oddParity <= genXor(ad'high) ;
-
-end scaleable ;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity oddParityLoop is
-  generic ( width : integer := 8 );
-  port (ad: in std_logic_vector (width - 1 downto 0);
-        oddParity : out std_logic ) ;
-end oddParityLoop ; 
-
-architecture scaleable of oddParityLoop is
-begin
-
-  process (ad) 
-    variable loopXor: std_logic;
-  begin
-    loopXor := '0';
-
-    for i in 0 to width -1 loop
-        loopXor := loopXor xor ad( i ) ;
-    end loop ;
-
-    oddParity <= loopXor ;
-
-  end process;
-
-end scaleable ;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity OR2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end OR2;
-
-architecture rtl of OR2 is
-
-begin
-
-  y <= '1' when i1 = '1' or i2 = '1' else '0';
-
-end rtl;
-library IEEE;
-USE IEEE.std_logic_1164.all;
-
-
-entity OR2 is port (
-  I1, I2: in std_logic;
-  Y: out std_logic
-  );
-end OR2;
-
-architecture simple of OR2 is
-
-begin
-
-  Y <= I1 OR I2 after 10 ns;
-
-end simple;
-library IEEE;
-USE IEEE.std_logic_1164.all;
-
-package simPrimitives is
-
-  component OR2
-    generic (tPD: time := 1 ns);
-
-    port (I1, I2: in std_logic;
-      Y: out std_logic
-      );
-  end component;
-
-end simPrimitives;
-
-
-library IEEE;
-USE IEEE.std_logic_1164.all;
-
-entity OR2 is
-  generic (tPD: time := 1 ns);
-
-  port (I1, I2: in std_logic;
-    Y: out std_logic
-    );
-end OR2;
-
-architecture simple of OR2 is
-
-begin
-
-  Y <= I1 OR I2 after tPD;
-
-end simple;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity adder is port (
-  a,b: in std_logic_vector(3 downto 0);
-  sum: out std_logic_vector(3 downto 0);
-  overflow: out std_logic
-  );
-end adder;
-
-architecture concat of adder is
-
-signal localSum: std_logic_vector(4 downto 0);
-
-begin
-
-  localSum <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
-
-  sum <= localSum(3 downto 0);
-  overflow <= localSum(4);
-
-end concat;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity paramDFF is
-  generic (size: integer := 8);
-  port (
-  data: in std_logic_vector(size - 1 downto 0);
-  clock: in std_logic;
-  reset: in std_logic;
-  ff_enable: in std_logic;
-  op_enable: in std_logic;
-  qout: out std_logic_vector(size - 1 downto 0)
-  );
-end paramDFF;
-
-architecture parameterize of paramDFF is
-
-signal reg: std_logic_vector(size - 1 downto 0);
-
-begin
-
-  u1: pDFFE generic map (n => size)
-            port map    (d => data,
-                         clk =>clock,
-                         rst => reset,
-                         en => ff_enable,
-                         q => reg
-                        );
-  u2: pTRIBUF generic map (n => size)
-              port map    (ip => reg,
-                           oe => op_enable,
-                           op => qout
-                          );
-
-end paramterize;
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity oddParityGen is
-  generic ( width : integer := 32 );
-  port (ad: in std_logic_vector (width - 1 downto 0);
-        oddParity : out std_logic ) ;
-end oddParityGen; 
-
-architecture scaleable of oddParityGen is
-
-signal genXor: std_logic_vector(ad'range);
-
-signal one: std_logic := '1';
-
-begin
-
-  parTree: for i in ad'range generate
-    g0: if i = 0 generate
-      x0: xor2 port map (i1 => one,
-                         i2 => one,
-                         y => genXor(0)
-                        );
-    end generate;
-
-    g1: if i > 0 and i <= ad'high generate
-      x1: xor2 port map (i1 => genXor(i - 1),
-                         i2 => ad(i - 1),
-                         y  => genXor(i)
-                        );
-    end generate;
-
-  end generate;
-
- oddParity <= genXor(ad'high) ;
-
-end scaleable ;
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity oddParityGen is
-  generic ( width : integer := 32 ); -- (2 <= width <= 32) and a power of 2
-  port (ad: in std_logic_vector (width - 1 downto 0);
-        oddParity : out std_logic ) ;
-end oddParityGen; 
-
-architecture scaleable of oddParityGen is
-
-signal stage0: std_logic_vector(31 downto 0);
-signal stage1: std_logic_vector(15 downto 0);
-signal stage2: std_logic_vector(7 downto 0);
-signal stage3: std_logic_vector(3 downto 0);
-signal stage4: std_logic_vector(1 downto 0);
-
-begin
-
-  g4: for i in stage4'range generate
-    g41: if (ad'length > 2) generate
-         x4: xor2 port map (stage3(i), stage3(i + stage4'length), stage4(i));
-    end generate;
-  end generate;
-
-  g3: for i in stage3'range generate
-    g31: if (ad'length > 4) generate
-         x3: xor2 port map (stage2(i), stage2(i + stage3'length), stage3(i));
-    end generate;
-  end generate;
-
-  g2: for i in stage2'range generate
-    g21: if (ad'length > 8) generate
-         x2: xor2 port map (stage1(i), stage1(i + stage2'length), stage2(i));
-    end generate;
-  end generate;
-
-  g1: for i in stage1'range generate
-    g11: if (ad'length > 16) generate
-         x1: xor2 port map (stage0(i), stage0(i + stage1'length), stage1(i));
-    end generate;
-  end generate;
-
-
-  s1: for i in ad'range generate
-    s14: if (ad'length = 2) generate
-         stage4(i) <= ad(i);
-    end generate;
-
-    s13: if (ad'length = 4) generate
-         stage3(i) <= ad(i);
-    end generate;
-
-    s12: if (ad'length = 8) generate
-         stage2(i) <= ad(i);
-    end generate;
-
-    s11: if (ad'length = 16) generate
-         stage1(i) <= ad(i);
-    end generate;
-
-    s10: if (ad'length = 32) generate
-         stage0(i) <= ad(i);
-    end generate;
-
-  end generate;
-
-
-  genPar: xor2 port map (stage4(0), stage4(1), oddParity);
-
-end scaleable ;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity powerOfFour is port(
-  clk      : in  std_logic; 
-  inputVal : in  unsigned(3 downto 0);
-  power    : out unsigned(15 downto 0)
-  );
-end powerOfFour;
-
-architecture behavioral of powerOfFour is
-
-   function Pow( N, Exp : integer )  return integer is
-      Variable Result   : integer := 1;
-
-   begin
-      for i in 1 to Exp loop
-         Result := Result * N;
-      end loop;
-      return( Result );
-   end Pow;
-
-signal inputValInt: integer range 0 to 15;
-signal powerL: integer range 0 to 65535;
-   
-begin
-
-   inputValInt <= to_integer(inputVal);
-   power <= to_unsigned(powerL,16);
-
-   process begin
-     wait until Clk = '1';
-
-       powerL <= Pow(inputValInt,4);
-   
-   end process;
-
-end behavioral;
-package PowerPkg is  
-  component Power port(
-      Clk                   : in  bit; 
-      inputVal              : in  bit_vector(0 to 3);
-      power                 : out bit_vector(0 to 15) );
-   end component;
-end          PowerPkg;
-
-use work.bv_math.all;
-use work.int_math.all;
-use work.PowerPkg.all;
-
-entity Power is port(
-   Clk                   : in  bit; 
-   inputVal              : in  bit_vector(0 to 3);
-   power                 : out bit_vector(0 to 15) );
-end    Power;
-
-
-
-
-architecture funky of Power is
-   
-   function Pow( N, Exp : integer )  return integer is
-      Variable Result   : integer := 1;
-      Variable i        : integer := 0;
-   begin
-      while( i < Exp ) loop
-         Result := Result * N;
-         i      := i      + 1;
-      end loop;
-      return( Result );
-   end Pow;
-   
-   
-   function RollVal(  CntlVal : integer )  return integer is
-   begin
-      return( Pow( 2, CntlVal ) + 2 );
-   end RollVal;
-   
-   
-begin
-   process 
-   begin
-      wait until Clk = '1';
-         
-        power <= i2bv(Rollval(bv2I(inputVal)),16);
-   
-   end process;
-end funky;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity priority_encoder is port
-  (interrupts : in  std_logic_vector(7 downto 0);
-   priority   : in  std_logic_vector(2 downto 0);
-   result     : out std_logic_vector(2 downto 0)
-  );
-end priority_encoder;
-
-architecture behave of priority_encoder is
-begin
-
-  process (interrupts)
-     variable selectIn  : integer;
-     variable LoopCount : integer;
-  begin
-
-    LoopCount   := 1;
-    selectIn := to_integer(to_unsigned(priority));
-      
-      while (LoopCount <= 7) and (interrupts(selectIn) /= '0') loop
-		
-        if (selectIn = 0) then
-          selectIn := 7;
-        else
-          selectIn := selectIn - 1;
-        end if;
-			
-        LoopCount := LoopCount + 1;
-  
-      end loop;
-		
-    result <= std_logic_vector(to_unsigned(selectIn,3));
-
-  end process;
-  
-end behave;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package primitive is
-  component DFFE port (
-    d: in std_logic;
-    q: out std_logic;
-    en: in std_logic;
-    clk: in std_logic
-    );
-  end component;
-
-  component DFFE_SR port (
-    d: in std_logic;
-    en: in std_logic;
-    clk: in std_logic;
-    rst: in std_logic;
-    prst: in std_logic;
-    q: out std_logic
-    );
-  end component;
-
-  component DLATCHH port (
-    d: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-  end component;
-
-  component AND2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component OR2 port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-  end component;
-
-  component INVERTER port (
-    i: in std_logic;
-    o: out std_logic
-    );
-  end component;
-
-  component TRIBUF port (
-    ip: in std_logic;
-    oe: in std_logic;
-    op: out std_logic
-    );
-  end component;
-
-  component BIDIR port (
-    ip: in std_logic;
-    oe: in std_logic;
-    op_fb: out std_logic;
-    op: inout std_logic
-    );
-  end component;
-
-end package;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFFE is port (
-    d: in std_logic;
-    q: out std_logic;
-    en: in std_logic;
-    clk: in std_logic
-    );
-end DFFE;
-
-architecture rtl of DFFE is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      if (en = '1') then
-        q <= d;
-      end if;
-  end process;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFFE_SR is port (
-    d: in std_logic;
-    en: in std_logic;
-    clk: in std_logic;
-    rst: in std_logic;
-    prst: in std_logic;
-    q: out std_logic
-    );
-end DFFE_SR;
-
-architecture rtl of DFFE_SR is
-
-begin
-
-  process (clk, rst, prst) begin
-    if (rst = '1') then
-      q <= '0';
-    elsif (prst = '1') then
-      q <= '1';
-    elsif (clk'event and clk = '1') then
-      if (en = '1') then
-        q <= d;
-      end if;
-    end if;
-  end process;
-
-end rtl;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DLATCHH is port (
-    d: in std_logic;
-    en: in std_logic;
-    q: out std_logic
-    );
-end DLATCHH;
-
-architecture rtl of DLATCHH is
-
-begin
-
-  process (en) begin
-    if (en = '1') then
-      q <= d;
-    end if;
-  end process;
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity AND2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end AND2;
-
-architecture rtl of AND2 is
-
-begin
-
-  y <= '1' when i1 = '1' and i2 = '1' else '0';
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity OR2 is port (
-    i1: in std_logic;
-    i2: in std_logic;
-    y: out std_logic
-    );
-end OR2;
-
-architecture rtl of OR2 is
-
-begin
-
-  y <= '1' when i1 = '1' or i2 = '1' else '0';
-
-end rtl;
-
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity INVERTER is port (
-    i: in std_logic;
-    o: out std_logic
-    );
-end INVERTER;
-
-architecture rtl of INVERTER is
-
-begin
-
-  o <= not i;
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity TRIBUF is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op: out std_logic
-  );
-end TRIBUF;
-
-architecture rtl of TRIBUF is
-
-begin
-
-  op <= ip when oe = '1' else 'Z';
-
-end rtl;
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity BIDIR is port (
-  ip: in std_logic;
-  oe: in std_logic;
-  op_fb: out std_logic;
-  op: inout std_logic
-  );
-end BIDIR;
-
-architecture rtl of BIDIR is
-
-begin
-
-  op <= ip when oe = '1' else 'Z';
-  op_fb <= op;
-
-end rtl;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity progPulse is port (
-  clk, reset: in std_logic;
-  loadLength,loadDelay: in std_logic;
-  data: in std_logic_vector(7 downto 0);
-  pulse: out std_logic
-  );
-end progPulse;
-
-architecture rtl of progPulse is
-
-signal downCnt, downCntData: unsigned(7 downto 0);
-signal downCntLd, downCntEn: std_logic;
-signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
-signal startPulse, endPulse: std_logic;
-
-subtype fsmType is std_logic_vector(1 downto 0);
-constant loadDelayCnt  : fsmType := "00";
-constant waitDelayEnd  : fsmType := "10";
-constant loadLengthCnt : fsmType := "11";
-constant waitLengthEnd : fsmType := "01";
-
-signal currState, nextState: fsmType;
-
-begin
-
-  delayreg: process (clk, reset) begin
-    if reset = '1' then
-      delayCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadDelay = '1' then
-        delayCntVal <= to_unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  lengthReg: process (clk, reset) begin
-    if reset = '1' then
-      pulseCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadDelay = '1' then
-        pulseCntVal <= to_unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
-    case currState is
-      when loadDelayCnt =>
-        nextState <= waitDelayEnd;
-
-      when waitDelayEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCnt = 0) then
-          nextState <= loadLengthCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when loadLengthCnt =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitLengthEnd;
-        end if;
-
-      when waitLengthEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCnt = 0) then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when others =>
-        null;
-
-   end case;
-  end process nextStProc;
-
-  currStProc: process (clk, reset) begin
-    if (reset = '1') then
-      currState <= loadDelayCnt;
-    elsif (clk'event and clk = '1') then
-      currState <= nextState;
-    end if;
-  end process currStProc;
-
-  outConProc: process (currState, delayCntVal, pulseCntVal) begin
-    case currState is
-      when loadDelayCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= delayCntVal;
-
-      when waitDelayEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downCntData <= delayCntVal;
-
-      when loadLengthCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= pulseCntVal;
-
-      when waitLengthEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downCntData <= pulseCntVal;
-
-      when others =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= pulseCntVal;
-
-    end case;
-  end process outConProc;
-
-  downCntr: process (clk,reset) begin
-    if (reset = '1') then
-      downCnt <= "00000000";
-    elsif (clk'event and clk = '1') then
-      if (downCntLd = '1') then
-        downCnt <= downCntData;
-      elsif (downCntEn = '1') then
-        downCnt <= downCnt - 1;
-      else
-        downCnt <= downCnt;
-      end if;
-    end if;
-  end process;
-
-  -- Assign pulse output
-  pulse <= currState(0);
-        
-
-end rtl;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity pulseErr is port
-  (a: in std_logic;
-   b: out std_logic
-  );
-end pulseErr;
-
-architecture behavior of pulseErr is
-
-signal c: std_logic;
-
-begin
-
-  pulse: process (a,c) begin
-    b <= c XOR a;
-
-    c <= a;
-  end process;
-
-end behavior;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity progPulse is port (
-  clk, reset: in std_logic;
-  loadLength,loadDelay: in std_logic;
-  data: in std_logic_vector(7 downto 0);
-  pulse: out std_logic
-  );
-end progPulse;
-
-architecture rtl of progPulse is
-
-signal downCnt, downCntData: unsigned(7 downto 0);
-signal downCntLd, downCntEn: std_logic;
-signal delayCntVal, pulseCntVal: unsigned(7 downto 0);
-signal startPulse, endPulse: std_logic;
-
-type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
-signal currState, nextState: progPulseFsmType;
-
-begin
-
-  delayreg: process (clk, reset) begin
-    if reset = '1' then
-      delayCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadDelay = '1' then
-        delayCntVal <= to_unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  lengthReg: process (clk, reset) begin
-    if reset = '1' then
-      pulseCntVal <= "11111111";
-    elsif clk'event and clk = '1' then
-      if loadDelay = '1' then
-        pulseCntVal <= to_unsigned(data);
-      end if;
-    end if;
-  end process;
-
-  nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
-    case currState is
-      when loadDelayCnt =>
-        nextState <= waitDelayEnd;
-
-      when waitDelayEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCnt = 0) then
-          nextState <= loadLengthCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when loadLengthCnt =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitLengthEnd;
-        end if;
-
-      when waitLengthEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCnt = 0) then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when others =>
-        null;
-
-   end case;
-  end process nextStProc;
-
-  currStProc: process (clk, reset) begin
-    if (reset = '1') then
-      currState <= loadDelayCnt;
-    elsif (clk'event and clk = '1') then
-      currState <= nextState;
-    end if;
-  end process currStProc;
-
-  outConProc: process (currState, delayCntVal, pulseCntVal) begin
-    case currState is
-      when loadDelayCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= delayCntVal;
-        pulse <= '0';
-
-      when waitDelayEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downCntData <= delayCntVal;
-        pulse <= '0';
-
-      when loadLengthCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= pulseCntVal;
-        pulse <= '1';
-
-      when waitLengthEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downCntData <= pulseCntVal;
-        pulse <= '1';
-
-      when others =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downCntData <= pulseCntVal;
-        pulse <= '0';
-
-    end case;
-  end process outConProc;
-
-  downCntr: process (clk,reset) begin
-    if (reset = '1') then
-      downCnt <= "00000000";
-    elsif (clk'event and clk = '1') then
-      if (downCntLd = '1') then
-        downCnt <= downCntData;
-      elsif (downCntEn = '1') then
-        downCnt <= downCnt - 1;
-      else
-        downCnt <= downCnt;
-      end if;
-    end if;
-  end process;
-        
-
-end rtl;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity progPulseFsm is port (
-  downCnt: in std_logic_vector(7 downto 0);
-  delayCntVal: in std_logic_vector(7 downto 0);
-  lengthCntVal: in std_logic_vector(7 downto 0);
-  loadLength: in std_logic;
-  loadDelay: in std_logic;
-  clk: in std_logic;
-  reset: in std_logic;
-
-  downCntEn: out std_logic;
-  downCntLd: out std_logic;
-  downCntData: out std_logic_vector(7 downto 0);
-
-  pulse: out std_logic
-  );
-end progPulseFsm;
-
-architecture fsm of progPulseFsm is
-
-type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
-type stateVec is array (3 downto 0) of std_logic;
-type stateBits is array (progPulseFsmType) of stateVec;
-
-signal loadVal: std_logic;
-
-constant stateTable: stateBits := (
-  loadDelayCnt =>  "0010",
-  waitDelayEnd =>  "0100",
-  loadLengthCnt => "0011",
-  waitLengthEnd => "1101" );
---                  ^^^^
---                  ||||__ loadVal   
---                  |||___ downCntLd
---                  ||____ downCntEn
---                  |_____ pulse
-
-signal currState, nextState: progPulseFsmType;
-
-begin
-
-  nextStProc: process (currState, downCnt, loadDelay, loadLength) begin
-    case currState is
-      when loadDelayCnt =>
-        nextState <= waitDelayEnd;
-
-      when waitDelayEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (to_unsigned(downCnt) = 0) then
-          nextState <= loadLengthCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when loadLengthCnt =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitLengthEnd;
-        end if;
-
-      when waitLengthEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (to_unsigned(downCnt) = 0) then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when others =>
-        null;
-
-   end case;
-
-  end process nextStProc;
-
-  currStProc: process (clk, reset) begin
-    if (reset = '1') then
-      currState <= loadDelayCnt;
-    elsif (clk'event and clk = '1') then
-      currState <= nextState;
-    end if;
-  end process currStProc;
-
-  pulse     <= stateTable(currState)(3);
-  downCntEn <= stateTable(currState)(2);
-  downCntLd <= stateTable(currState)(1);
-  loadVal   <= stateTable(currState)(0);
-  
-  downCntData <= delayCntVal when loadVal = '0' else lengthCntVal;
-
-end fsm;
--- Incorporates Errata 6.1
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity progPulseFsm is port (
-  downCnt: in std_logic_vector(7 downto 0);
-  delayCntVal: in std_logic_vector(7 downto 0);
-  lengthCntVal: in std_logic_vector(7 downto 0);
-  loadLength: in std_logic;
-  loadDelay: in std_logic;
-  clk: in std_logic;
-  reset: in std_logic;
-
-  downCntEn: out std_logic;
-  downCntLd: out std_logic;
-  downtCntData: out std_logic_vector(7 downto 0);
-
-  pulse: out std_logic
-  );
-end progPulseFsm;
-
-architecture fsm of progPulseFsm is
-
-type progPulseFsmType is (loadDelayCnt, waitDelayEnd, loadLengthCnt, waitLengthEnd);
-signal currState, nextState: progPulseFsmType;
-signal downCntL: unsigned (7 downto 0);
-
-begin
-
-  downCntL <= to_unsigned(downCnt); -- convert downCnt to unsigned
-
-  nextStProc: process (currState, downCntL, loadDelay, loadLength) begin
-    case currState is
-      when loadDelayCnt =>
-        nextState <= waitDelayEnd;
-
-      when waitDelayEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCntL = 0) then
-          nextState <= loadLengthCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when loadLengthCnt =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitLengthEnd;
-        end if;
-
-      when waitLengthEnd =>
-        if (loadDelay = '1' or loadLength = '1') then
-          nextState <= loadDelayCnt;
-        elsif (downCntL = 0) then
-          nextState <= loadDelayCnt;
-        else
-          nextState <= waitDelayEnd;
-        end if;
-
-      when others =>
-        null;
-
-   end case;
-
-  end process nextStProc;
-
-  currStProc: process (clk, reset) begin
-    if (reset = '1') then
-      currState <= loadDelayCnt;
-    elsif (clk'event and clk = '1') then
-      currState <= nextState;
-    end if;
-  end process currStProc;
-
-  outConProc: process (currState, delayCntVal, lengthCntVal) begin
-    case currState is
-      when loadDelayCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downtCntData <= delayCntVal;
-        pulse <= '0';
-
-      when waitDelayEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downtCntData <= delayCntVal;
-        pulse <= '0';
-
-      when loadLengthCnt =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downtCntData <= lengthCntVal;
-        pulse <= '1';
-
-      when waitLengthEnd =>
-        downCntEn <= '1';
-        downCntLd <= '0';
-        downtCntData <= lengthCntVal;
-        pulse <= '1';
-
-      when others =>
-        downCntEn <= '0';
-        downCntLd <= '1';
-        downtCntData <= delayCntVal;
-        pulse <= '0';
-
-    end case;
-  end process outConProc;
-
-end fsm;
--- Incorporates errata 5.4
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-use work.specialFunctions.all;
-
-entity powerOfFour is port(
-  clk      : in  std_logic; 
-  inputVal : in  std_logic_vector(3 downto 0);
-  power    : out std_logic_vector(15 downto 0)
-  );
-end powerOfFour;
-
-architecture behavioral of powerOfFour is
-
-begin
-
-   process begin
-     wait until Clk = '1';
-
-       power <= std_logic_vector(to_unsigned(Pow(to_integer(unsigned(inputVal)),4),16));
-   
-   end process;
-
-end behavioral;
--- Incorporate errata 5.4
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity powerOfFour is port(
-  clk      : in  std_logic; 
-  inputVal : in  std_logic_vector(3 downto 0);
-  power    : out std_logic_vector(15 downto 0)
-  );
-end powerOfFour;
-
-architecture behavioral of powerOfFour is
-
-   function Pow( N, Exp : integer )  return integer is
-      Variable Result   : integer := 1;
-
-   begin
-      for i in 1 to Exp loop
-         Result := Result * N;
-      end loop;
-      return( Result );
-   end Pow;
-
-begin
-
-   process begin
-     wait until Clk = '1';
-
-       power <= std_logic_vector(to_unsigned(Pow(to_integer(to_unsigned(inputVal)),4),16));
-   
-   end process;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_arith.all;
-use IEEE.std_logic_unsigned.all;
-
-entity powerOfFour is port(
-  clk      : in  std_logic; 
-  inputVal : in  std_logic_vector(3 downto 0);
-  power    : out std_logic_vector(15 downto 0)
-  );
-end powerOfFour;
-
-architecture behavioral of powerOfFour is
-
-   function Pow( N, Exp : integer )  return integer is
-      Variable Result   : integer := 1;
-
-   begin
-      for i in 1 to Exp loop
-         Result := Result * N;
-      end loop;
-      return( Result );
-   end Pow;
-
-begin
-
-   process begin
-     wait until Clk = '1';
-
-       power <= conv_std_logic_vector(Pow(conv_integer(inputVal),4),16);
-   
-   end process;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity regFile is port (
-  clk, rst: in std_logic;
-  data: in std_logic_vector(31 downto 0);
-  regSel: in std_logic_vector(1 downto 0);
-  wrEnable: in std_logic;
-  regOut: out std_logic_vector(31 downto 0)
-  );
-end regFile;
-
-architecture behavioral of regFile is
-
-subtype reg is std_logic_vector(31 downto 0);
-type regArray is array (integer range <>) of reg;
-
-signal registerFile: regArray(0 to 3);
-
-begin
-
-  regProc: process (clk, rst) 
-  variable i: integer;
-
-  begin
-    i := 0;
-
-    if rst = '1' then
-      while i <= registerFile'high loop
-        registerFile(i) <= (others => '0');
-        i := i + 1;
-      end loop;
-
-    elsif clk'event and clk = '1' then
-      if (wrEnable = '1') then
-        case regSel is
-          when "00" =>
-            registerFile(0) <= data;
-          when "01" =>
-            registerFile(1) <= data;
-          when "10" =>
-            registerFile(2) <= data;
-          when "11" =>
-            registerFile(3) <= data;
-          when others =>
-            null;
-        end case;
-      end if;
-    end if;
-  end process;
-
-  outputs: process(regSel, registerFile) begin
-    case regSel is
-      when "00" =>
-        regOut <= registerFile(0);
-      when "01" =>
-        regOut <= registerFile(1);
-      when "10" =>
-        regOut <= registerFile(2);
-      when "11" =>
-        regOut <= registerFile(3);
-      when others =>
-        null;
-    end case;
-  end process;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity DFF is port (
-    d1,d2: in std_logic;
-    q1,q2: out std_logic;
-    clk: in std_logic;
-    rst : in std_logic
-    );
-end DFF;
-
-architecture rtl of DFF is
-
-begin
-
-  resetLatch: process (clk, rst) begin
-    if rst = '1' then
-      q1 <= '0';
-    elsif clk'event and clk = '1' then
-      q1 <= d1;
-      q2 <= d2;
-    end if;
-  end process;
-
-end rtl;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity resFcnDemo is port (
-  a, b: in std_logic;
-  oeA,oeB: in std_logic;
-  result: out std_logic
-  );
-end resFcnDemo;
-
-architecture multiDriver of resFcnDemo is
-
-begin
-
-  result <= a when oeA = '1' else 'Z';
-  result <= b when oeB = '1' else 'Z';
-
-end multiDriver;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity scaleDFF is port (
-  data: in std_logic_vector(7 downto 0);
-  clock: in std_logic;
-  enable: in std_logic;
-  qout: out std_logic_vector(7 downto 0)
-  );
-end scaleDFF;
-
-architecture scalable of scaleDFF is
-
-begin
-
-  u1: sDFFE port map (d => data,
-                      clk =>clock,
-                      en => enable,
-                      q => qout
-                     );
-
-end scalable;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-
-entity sevenSegment is port (
-  bcdInputs: in std_logic_vector (3 downto 0);
-  a_n, b_n, c_n, d_n,
-  e_n, f_n, g_n: out std_logic
-  );
-end sevenSegment;
-
-architecture behavioral of sevenSegment is
-
-signal la_n, lb_n, lc_n, ld_n, le_n, lf_n, lg_n: std_logic;
-signal oe: std_logic;
-
-begin
-
-  bcd2sevSeg: process (bcdInputs) begin
-
-  -- Assign default to "off"
-    la_n <= '1';    lb_n <= '1';
-    lc_n <= '1';    ld_n <= '1';
-    le_n <= '1';    lf_n <= '1';
-    lg_n <= '1';
-
-    case bcdInputs is
-      when "0000" => la_n <= '0';        lb_n <= '0';
-                     lc_n <= '0';        ld_n <= '0';
-                     le_n <= '0';        lf_n <= '0';
-
-      when "0001" => lb_n <= '0';        lc_n <= '0';
-
-      when "0010" => la_n <= '0';        lb_n <= '0';
-                     ld_n <= '0';        le_n <= '0';
-                     lg_n <= '0';
-
-      when "0011" => la_n <= '0';        lb_n <= '0';
-                     lc_n <= '0';        ld_n <= '0';
-                     lg_n <= '0';
-
-      when "0100" => lb_n <= '0';        lc_n <= '0';
-                     lf_n <= '0';        lg_n <= '0';
-
-      when "0101" => la_n <= '0';        lc_n <= '0';
-                     ld_n <= '0';        lf_n <= '0';
-                     lg_n <= '0';
-
-      when "0110" => la_n <= '0';        lc_n <= '0';
-                     ld_n <= '0';        le_n <= '0';
-                     lf_n <= '0';        lg_n <= '0';
-
-      when "0111" => la_n <= '0';        lb_n <= '0';
-                     lc_n <= '0';
-
-      when "1000" => la_n <= '0';        lb_n <= '0';
-                     lc_n <= '0';        ld_n <= '0';
-                     le_n <= '0';        lf_n <= '0';
-                     lg_n <= '0';
-
-      when "1001" => la_n <= '0';        lb_n <= '0';
-                     lc_n <= '0';        ld_n <= '0';
-                     lf_n <= '0';        lg_n <= '0';
-
--- All other inputs possibilities are "don't care"
-
-      when others => la_n <= 'X';        lb_n <= 'X';
-                     lc_n <= 'X';        ld_n <= 'X';
-                     le_n <= 'X';        lf_n <= 'X';
-                     lg_n <= 'X';
-
-    end case;
-
-  end process bcd2sevSeg;
-
-  -- Disable outputs for all invalid input values
-
-  oe <= '1' when (bcdInputs < 10) else '0';
-
-  a_n <= la_n when oe = '1' else 'Z';
-  b_n <= lb_n when oe = '1' else 'Z';
-  c_n <= lc_n when oe = '1' else 'Z';
-  d_n <= ld_n when oe = '1' else 'Z';
-  e_n <= le_n when oe = '1' else 'Z';
-  f_n <= lf_n when oe = '1' else 'Z';
-  g_n <= lg_n when oe = '1' else 'Z';
-
-
-end behavioral;
-library ieee;
-use ieee.std_logic_1164.all;
-
-use std.textio.all;
-
-entity sevenSegmentTB is
-end sevenSegmentTB;
-
-architecture testbench of sevenSegmentTB is
-
-component sevenSegment port (
-  bcdInputs: in std_logic_vector (3 downto 0);
-  a_n, b_n, c_n, d_n,
-  e_n, f_n, g_n: out std_logic
-  );
-end component;
-
-type vector is record
-  bcdStimulus: std_logic_vector(3 downto 0);
-  sevSegOut: std_logic_vector(6 downto 0);
-end record;
-
-constant NumVectors: integer:= 17;
-constant PropDelay: time := 40 ns;
-constant SimLoopDelay: time := 10 ns;
-
-type vectorArray is array (0 to NumVectors - 1) of vector;
-constant vectorTable: vectorArray := (
-  (bcdStimulus => "0000", sevSegOut => "0000001"),
-  (bcdStimulus => "0001", sevSegOut => "1001111"),
-  (bcdStimulus => "0010", sevSegOut => "0010010"),
-  (bcdStimulus => "0011", sevSegOut => "0000110"),
-  (bcdStimulus => "0100", sevSegOut => "1001100"),
-  (bcdStimulus => "0101", sevSegOut => "0100100"),
-  (bcdStimulus => "0110", sevSegOut => "0100000"),
-  (bcdStimulus => "0111", sevSegOut => "0001111"),
-  (bcdStimulus => "1000", sevSegOut => "0000000"),
-  (bcdStimulus => "1001", sevSegOut => "0000100"),
-  (bcdStimulus => "1010", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "1011", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "1100", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "1101", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "1110", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "1111", sevSegOut => "ZZZZZZZ"),
-  (bcdStimulus => "0000", sevSegOut => "0110110") -- this vector fails
-  );
-
-for all : sevenSegment use entity work.sevenSegment(behavioral);
-
-signal StimInputs: std_logic_vector(3 downto 0);
-signal CaptureOutputs: std_logic_vector(6 downto 0);
-
-begin
-
-  u1: sevenSegment port map (bcdInputs => StimInputs,
-                             a_n => CaptureOutputs(6),
-                             b_n => CaptureOutputs(5),
-                             c_n => CaptureOutputs(4),
-                             d_n => CaptureOutputs(3),
-                             e_n => CaptureOutputs(2),
-                             f_n => CaptureOutputs(1),
-                             g_n => CaptureOutputs(0));
-
-  LoopStim: process
-    variable FoundError: boolean := false;
-    variable TempVector: vector;
-    variable ErrorMsgLine: line;
-  begin
-
-    for i in vectorTable'range loop
-      TempVector := vectorTable(i);
-
-      StimInputs <= TempVector.bcdStimulus;
-
-      wait for PropDelay;
-
-      if CaptureOutputs /= TempVector.sevSegOut then
-          write (ErrorMsgLine, string'("Vector failed at "));
-          write (ErrorMsgLine, now);
-          writeline (output, ErrorMsgLine);
-          FoundError := true;
-      end if;
-
-      wait for SimLoopDelay;
-
-    end loop;
-
-  assert FoundError
-    report "No errors. All vectors passed."
-    severity note;
-
-  wait;
-
-  end process;
-
-end testbench;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sevenSegment is port (
-  bcdInputs: in std_logic_vector (3 downto 0);
-  a_n, b_n, c_n, d_n,
-  e_n, f_n, g_n: out std_logic
-  );
-end sevenSegment;
-
-architecture behavioral of sevenSegment is
-
-begin
-
-  bcd2sevSeg: process (bcdInputs) begin
-
-  -- Assign default to "off"
-    a_n <= '1';    b_n <= '1';
-    c_n <= '1';    d_n <= '1';
-    e_n <= '1';    f_n <= '1';
-    g_n <= '1';
-
-    case bcdInputs is
-      when "0000" =>
-        a_n <= '0';        b_n <= '0';
-        c_n <= '0';        d_n <= '0';
-        e_n <= '0';        f_n <= '0';
-
-      when "0001" =>
-        b_n <= '0';        c_n <= '0';
-
-      when "0010" =>
-        a_n <= '0';        b_n <= '0';
-        d_n <= '0';        e_n <= '0';
-        g_n <= '0';
-
-      when "0011" =>
-        a_n <= '0';        b_n <= '0';
-        c_n <= '0';        d_n <= '0';
-        g_n <= '0';
-
-      when "0100" =>
-        b_n <= '0';        c_n <= '0';
-        f_n <= '0';        g_n <= '0';
-
-      when "0101" =>
-        a_n <= '0';        c_n <= '0';
-        d_n <= '0';        f_n <= '0';
-        g_n <= '0';
-
-      when "0110" =>
-        a_n <= '0';        c_n <= '0';
-        d_n <= '0';        e_n <= '0';
-        f_n <= '0';        g_n <= '0';
-
-      when "0111" =>
-        a_n <= '0';        b_n <= '0';
-        c_n <= '0';
-
-      when "1000" =>
-        a_n <= '0';        b_n <= '0';
-        c_n <= '0';        d_n <= '0';
-        e_n <= '0';        f_n <= '0';
-        g_n <= '0';
-
-      when "1001" =>
-        a_n <= '0';        b_n <= '0';
-        c_n <= '0';        d_n <= '0';
-        f_n <= '0';        g_n <= '0';
-
-      when others =>
-        null;
-
-    end case;
-
-  end process bcd2sevSeg;
-
-end behavioral;
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.std_logic_unsigned.all;
-
-entity ForceShare is port (
-  a,b,c,d,e,f: in std_logic_vector (7 downto 0);
-  result: out std_logic_vector(7 downto 0)
-  );
-end ForceShare;
-
-architecture behaviour of ForceShare is
-
-begin
-
-  sum: process (a,c,b,d,e,f)
-  variable tempSum: std_logic_vector(7 downto 0);
-  begin
-
-    tempSum := a + b; -- temporary node for sum
-
-    if (tempSum = "10011010") then
-      result <= c;
-    elsif (tempSum = "01011001") then
-          result <= d;
-    elsif (tempSum = "10111011") then
-      result <= e;
-    else
-      result <= f;
-    end if;
-  end process;
-
-end behaviour;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity shifter is port (
-  clk, rst: in std_logic;
-  shiftEn,shiftIn: std_logic;
-  q: out std_logic_vector (15 downto 0)
-  );
-end shifter;
-
-
-architecture behav of shifter is
-
-signal qLocal: std_logic_vector(15 downto 0);
-
-begin
-
-  shift: process (clk, rst) begin
-    if (rst = '1') then
-      qLocal <= (others => '0');
-    elsif (clk'event and clk = '1') then
-      if (shiftEn = '1') then
-        qLocal <= qLocal(14 downto 0) & shiftIn;
-      else
-        qLocal <= qLocal;
-      end if;
-    end if;
-
-    q <= qLocal;
-  end process;
-
-end behav;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity lastAssignment is port
-  (a, b: in std_logic;
-   selA, selb: in std_logic;
-   result: out std_logic
-  );
-end lastAssignment;
-
-architecture behavioral of lastAssignment is
-
-begin
-
-  demo: process (a,b,selA,selB) begin
-    if (selA = '1') then
-      result <= a;
-    else
-      result <= '0';
-    end if;
-
-    if (selB = '1') then
-      result <= b;
-    else
-      result <= '0';
-    end if;
-  end process demo;
-
-end behavioral;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity signalDemo is port (
-  a: in std_logic;
-  b: out std_logic
-  );
-end signalDemo;
-
-architecture basic of signalDemo is
-
-signal c: std_logic;
-
-begin
-
-  demo: process (a) begin
-
-    c <= a;
-
-    if c = '0' then
-      b <= a;
-    else
-      b <= '0';
-    end if;
-
-  end process;
-
-end basic;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity signalDemo is port (
-  a: in std_logic;
-  b: out std_logic
-  );
-end signalDemo;
-
-architecture basic of signalDemo is
-
-signal c: std_logic;
-
-begin
-
-  demo: process (a) begin
-
-    c <= a;
-
-    if c = '1' then
-      b <= a;
-    else
-      b <= '0';
-    end if;
-
-  end process;
-
-end basic;
-library IEEE;
-USE IEEE.std_logic_1164.all;
-
-package simPrimitives is
-
-  component OR2
-    generic (tPD: time := 1 ns);
-
-    port (I1, I2: in std_logic;
-          Y: out std_logic
-         );
-  end component;
-
-  component SimDFF
-  generic(tCQ: time := 1 ns;
-          tS : time := 1 ns;
-          tH : time := 1 ns
-         );
-  port (D, Clk: in std_logic;
-        Q: out std_logic
-       );
-  end component;
-
-
-end simPrimitives;
-
-
-library IEEE;
-USE IEEE.std_logic_1164.all;
-
-entity OR2 is
-  generic (tPD: time := 1 ns);
-
-  port (I1, I2: in std_logic;
-    Y: out std_logic
-    );
-end OR2;
-
-architecture simple of OR2 is
-
-begin
-
-  Y <= I1 OR I2 after tPD;
-
-end simple;
-
-
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SimDFF is
-  generic(tCQ: time := 1 ns;
-          tS : time := 1 ns;
-          tH : time := 1 ns
-         );
-  port (D, Clk: in std_logic;
-  Q: out std_logic
-  );
-end SimDff;
-
-architecture SimModel of SimDFF is
-
-begin
-
-  reg: process (Clk, D) begin
-
-    -- Assign output tCQ after rising clock edge
-    if (Clk'event and Clk = '1') then
-      Q <= D after tCQ;
-    end if;
-
-    -- Check setup time
-    if (Clk'event and Clk = '1') then
-      assert (D'last_event >= tS)
-        report "Setup time violation"
-        severity Warning;
-    end if;
-
-    -- Check hold time
-    if (D'event and Clk'stable and Clk = '1') then
-      assert (D'last_event - Clk'last_event > tH)
-        report "Hold Time Violation"
-        severity Warning;
-    end if;
-
-  end process;
-
-end simModel;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SRFF is port (
-    s,r: in std_logic;
-    clk: in std_logic;
-    q: out std_logic
-    );
-end SRFF;
-
-architecture rtl of SRFF is
-
-begin
-
-  process begin
-    wait until rising_edge(clk);
-      if s = '0' and r = '1' then
-	q <= '0';
-      elsif s = '1' and r = '0' then
-	q <= '1';
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity SRFF is port (
-    s,r: in std_logic;
-    clk: in std_logic;
-    q: out std_logic
-    );
-end SRFF;
-
-architecture rtl of SRFF is
-
-begin
-
-  process begin
-    wait until clk = '1';
-      if s = '0' and r = '1' then
-	q <= '0';
-      elsif s = '1' and r = '0' then
-	q <= '1';
-      end if;
-  end process;
-
-end rtl;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package scaleable is
-  component scaleUpCnt port (
-    clk: in std_logic;
-    reset: in std_logic;
-    cnt: in std_logic_vector
-    );
-  end component;
-end scaleable;
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-use work.primitive.all;
-
-entity scaleUpCnt is port (
-  clk: in std_logic;
-  reset: in std_logic;
-  cnt: out std_logic_vector
-  );
-end scaleUpCnt;
-
-architecture scaleable of scaleUpCnt is
-
-signal one: std_logic := '1';
-signal cntL: std_logic_vector(cnt'range);
-signal andTerm: std_logic_vector(cnt'range);
-
-begin
-
--- Special case is the least significant bit
-
-  lsb: tff port map (t => one,
-                     reset => reset,
-                     clk => clk,
-                     q => cntL(cntL'low)
-                    );
-
-  andTerm(0) <= cntL(cntL'low);
-
-
--- General case for all other bits
-
-  genAnd: for i in 1 to cntL'high generate
-    andTerm(i) <= andTerm(i - 1) and cntL(i);
-  end generate;
-
-  genTFF: for i in 1 to cntL'high generate
-    t1: tff port map (t => andTerm(i),
-                      clk => clk,
-                      reset => reset,
-                      q => cntl(i)
-                     );
-  end generate;
-
-  cnt <= CntL;
-
-end scaleable;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(2 downto 0);
-
-constant Idle: 		targetFsmType := "000";
-constant B_Busy: 		targetFsmType := "101";
-constant Backoff: 	targetFsmType := "010";
-constant S_Data: 		targetFsmType := "011";
-constant Turn_Ar: 	targetFsmType := "110";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    null;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(2 downto 0);
-
-constant Idle: 		targetFsmType := "000";
-constant B_Busy: 		targetFsmType := "001";
-constant Backoff: 	targetFsmType := "011";
-constant S_Data: 		targetFsmType := "010";
-constant Turn_Ar: 	targetFsmType := "110";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    null;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(2 downto 0);
-
-constant Idle: 		targetFsmType := "000";
-constant B_Busy: 	targetFsmType := "001";
-constant Backoff: 	targetFsmType := "010";
-constant S_Data: 	targetFsmType := "011";
-constant Turn_Ar: 	targetFsmType := "100";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    null;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(3 downto 0);
-
-constant Idle: 		targetFsmType := "0000";
-constant B_Busy: 	targetFsmType := "0001";
-constant Backoff: 	targetFsmType := "0011";
-constant S_Data: 	targetFsmType := "1100";
-constant Turn_Ar: 	targetFsmType := "1101";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    null;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(2 downto 0);
-
-constant Idle: 		targetFsmType := "000";
-constant B_Busy: 		targetFsmType := "101";
-constant Backoff: 	targetFsmType := "010";
-constant S_Data: 		targetFsmType := "011";
-constant Turn_Ar: 	targetFsmType := "110";
-constant Dont_Care: targetFsmType := "XXX";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    nextState <= Dont_Care;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-
-  -- Set default output assignments
-  OE_Trdy_n <= '0';
-  OE_Stop_n <= '0';
-  OE_Devsel_n <= '0';
-  OE_AD <= '0';
-  LPCI_Trdy_n <= '1';
-  LPCI_Stop_n <= '1';
-  LPCI_Devsel_n <= '1';
-
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;    -- PCI Frame#
-  PCI_Irdy_n: in std_logic;     -- PCI Irdy#
-  Hit: in std_logic;            -- Hit on address decode
-  D_Done: in std_logic;         -- Device decode complete
-  Term: in std_logic;           -- Terminate transaction
-  Ready: in std_logic;          -- Ready to transfer data
-  Cmd_Write: in std_logic;      -- Command is Write
-  Cmd_Read: in std_logic;       -- Command is Read
-  T_Abort: in std_logic;        -- Target error  - abort transaction
-  PCI_Clk: in std_logic;        -- PCI Clock
-  PCI_Reset_n: in std_logic;    -- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Stop_n: out std_logic;    -- PCI Stop#
-  PCI_Trdy_n: out std_logic;    -- PCI Trdy#
-  OE_AD: out std_logic;         -- PCI AD bus enable
-  OE_Trdy_n: out std_logic;     -- PCI Trdy# enable
-  OE_Stop_n: out std_logic;     -- PCI Stop# enable
-  OE_Devsel_n: out std_logic    -- PCI Devsel# enable
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-type targetFsmType is (Idle, B_Busy, Backoff, S_Data, Turn_Ar);
-
-signal currState, nextState: targetFsmType;
-
-begin
-
--- Process to generate next state logic
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when Idle  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_Busy;
-      else
-        nextState <= Idle;
-      end if;
-
-    when B_Busy =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= Idle;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= Backoff;
-      else
-        nextState <= B_Busy;
-      end if;
-
-    when S_Data =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= Backoff;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= Turn_Ar;
-      else
-        nextState <= S_Data;
-      end if;
-
-
-    when Backoff =>
-      if PCI_Frame_n = '1' then
-        nextState <= Turn_Ar;
-      else
-        nextState <= Backoff;
-      end if;
-
-    when Turn_Ar  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_Busy;
-      else
-        nextState <= Idle;
-      end if;
-
-    when others =>
-      null;
-
-    end case;
-
-  end process nxtStProc;
-
-
--- Process to register the current state
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
--- Process to generate outputs
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-          OE_AD <= '1';
-        else
-          OE_AD <= '0';
-        end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-          OE_AD <= '1';
-        else
-          OE_AD <= '0';
-        end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-        OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
--- Assign output ports
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
--- Incorporates Errata 10.1 and 10.2
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;    -- PCI Frame#
-  PCI_Irdy_n: in std_logic;     -- PCI Irdy#
-  Hit: in std_logic;            -- Hit on address decode
-  D_Done: in std_logic;         -- Device decode complete
-  Term: in std_logic;           -- Terminate transaction
-  Ready: in std_logic;          -- Ready to transfer data
-  Cmd_Write: in std_logic;      -- Command is Write
-  Cmd_Read: in std_logic;       -- Command is Read
-  T_Abort: in std_logic;        -- Target error  - abort transaction
-  PCI_Clk: in std_logic;        -- PCI Clock
-  PCI_Reset_n: in std_logic;    -- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;  -- PCI Devsel#
-  PCI_Trdy_n: out std_logic;    -- PCI Trdy#
-  PCI_Stop_n: out std_logic;    -- PCI Stop#
-  OE_AD: out std_logic;         -- PCI AD bus enable
-  OE_Trdy_n: out std_logic;     -- PCI Trdy# enable
-  OE_Stop_n: out std_logic;     -- PCI Stop# enable
-  OE_Devsel_n: out std_logic    -- PCI Devsel# enable
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(4 downto 0);
-
-constant Idle:    integer := 0;
-constant B_Busy:  integer := 1;
-constant Backoff: integer := 2;
-constant S_Data:  integer := 3;
-constant Turn_Ar: integer := 4;
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-                     LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-
-   nextState <= (others => '0');
-
-   if currState(Idle) = '1' then
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState(B_Busy) <= '1';
-      else
-        nextState(Idle) <= '1';
-      end if;
-   end if;
-
-   if currState(B_Busy) = '1' then
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState(Idle) <= '1';
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState(S_Data) <= '1';
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState(Backoff) <= '1';
-      else
-        nextState(B_Busy) <= '1';
-      end if;
-   end if;
-
-   if currState(S_Data) = '1' then
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
-         (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState(Backoff) <= '1';
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState(Turn_Ar) <= '1';
-      else
-        nextState(S_Data) <= '1';
-      end if;
-   end if;
-
-
-   if currState(Backoff) = '1' then
-      if PCI_Frame_n = '1' then
-        nextState(Turn_Ar) <= '1';
-      else
-        nextState(Backoff) <= '1';
-      end if;
-   end if;
-
-   if currState(Turn_Ar) = '1' then
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState(B_Busy) <= '1';
-      else
-        nextState(Idle) <= '1';
-      end if;
-   end if;
-
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-	currState <= (others => '0'); -- per Errata 10.2
-      currState(Idle) <= '1';
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-      OE_Trdy_n <= '0';	OE_Stop_n <= '0';	OE_Devsel_n <= '0';	-- defaults per errata 10.1
-      OE_AD <= '0';		LPCI_Trdy_n <= '1';	LPCI_Stop_n <= '1';
-	  LPCI_Devsel_n <= '1';
-
-    if (currState(S_Data) = '1') then
-      if (Cmd_Read = '1') then 
-        OE_AD <= '1';
-      else
-        OE_AD <= '0';
-      end if;
-
-      if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-      else
-        LPCI_Trdy_n <= '1';
-      end if;
-
-      if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-        LPCI_Stop_n <= '0';
-      else
-        LPCI_Stop_n <= '1';
-      end if;
-
-      if (T_Abort = '0') then
-        LPCI_Devsel_n <= '0';
-      else
-        LPCI_Devsel_n <= '1';
-      end if;
-
-      OE_Trdy_n <= '1';
-      OE_Stop_n <= '1';
-      OE_Devsel_n <= '1';
-    end if;
-
-
-    if (currState(Backoff) = '1') then
-      if (Cmd_Read = '1') then 
-        OE_AD <= '1';
-      else
-        OE_AD <= '0';
-      end if;
-
-      LPCI_Stop_n <= '0';
-
-      OE_Trdy_n <= '1';
-      OE_Stop_n <= '1';
-      OE_Devsel_n <= '1';
-
-      if (T_Abort = '0') then
-        LPCI_Devsel_n <= '0';
-      else
-        LPCI_Devsel_n <= '1';
-      end if;
-    end if;
-
-
-    if (currState(Turn_Ar) = '1') then
-      OE_Trdy_n <= '1';
-      OE_Stop_n <= '1';
-      OE_Devsel_n <= '1';
-    end if;
-
-    if (currState(Idle) = '1' or currState(B_Busy) = '1') then
-      OE_Trdy_n <= '0';
-      OE_Stop_n <= '0';
-      OE_Devsel_n <= '0';
-      OE_AD <= '0';
-      LPCI_Trdy_n <= '1';
-      LPCI_Stop_n <= '1';
-      LPCI_Devsel_n <= '1';
-    end if;
-
-   end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;	-- PCI Frame#
-  PCI_Irdy_n: in std_logic;		-- PCI Irdy#
-  Hit: in std_logic;			-- Hit on address decode
-  D_Done: in std_logic;			-- Device decode complete
-  Term: in std_logic;			-- Terminate transaction
-  Ready: in std_logic;			-- Ready to transfer data
-  Cmd_Write: in std_logic;		-- Command is Write
-  Cmd_Read: in std_logic;		-- Command is Read
-  T_Abort: in std_logic;		-- Target error  - abort transaction
-  PCI_Clk: in std_logic;		-- PCI Clock
-  PCI_Reset_n: in std_logic;	-- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;	-- PCI Devsel#
-  PCI_Trdy_n: out std_logic;	-- PCI Trdy#
-  PCI_Stop_n: out std_logic;	-- PCI Stop#
-  OE_AD: out std_logic;			-- PCI AD bus enable
-  OE_Trdy_n: out std_logic;		-- PCI Trdy# enable
-  OE_Stop_n: out std_logic;		-- PCI Stop# enable
-  OE_Devsel_n: out std_logic	-- PCI Devsel# enable
-
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-subtype targetFsmType is std_logic_vector(2 downto 0);
-
-constant Idle: 		targetFsmType := "000";
-constant B_Busy: 	targetFsmType := "001";
-constant Backoff: 	targetFsmType := "011";
-constant S_Data: 	targetFsmType := "110";
-constant Turn_Ar: 	targetFsmType := "100";
-
-signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-			         LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when IDLE  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-    when B_BUSY =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= IDLE;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= BACKOFF;
-      else
-        nextState <= B_BUSY;
-      end if;
-
-    when S_DATA =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= BACKOFF;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= TURN_AR;
-      else
-        nextState <= S_DATA;
-      end if;
-
-
-    when BACKOFF =>
-      if PCI_Frame_n = '1' then
-        nextState <= TURN_AR;
-      else
-        nextState <= BACKOFF;
-      end if;
-
-    when TURN_AR  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_BUSY;
-      else
-        nextState <= IDLE;
-      end if;
-
-      when others =>
-	    nextState <= IDLE;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-
-  -- Set default output assignments
-  OE_Trdy_n <= '0';
-  OE_Stop_n <= '0';
-  OE_Devsel_n <= '0';
-  OE_AD <= '0';
-  LPCI_Trdy_n <= '1';
-  LPCI_Stop_n <= '1';
-  LPCI_Devsel_n <= '1';
-
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-		  OE_AD <= '1';
-	    else
-		  OE_AD <= '0';
-		end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-	  when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-		OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity pci_target is port (
-  PCI_Frame_n: in std_logic;    -- PCI Frame#
-  PCI_Irdy_n: in std_logic;     -- PCI Irdy#
-  Hit: in std_logic;            -- Hit on address decode
-  D_Done: in std_logic;         -- Device decode complete
-  Term: in std_logic;           -- Terminate transaction
-  Ready: in std_logic;          -- Ready to transfer data
-  Cmd_Write: in std_logic;      -- Command is Write
-  Cmd_Read: in std_logic;       -- Command is Read
-  T_Abort: in std_logic;        -- Target error  - abort transaction
-  PCI_Clk: in std_logic;        -- PCI Clock
-  PCI_Reset_n: in std_logic;    -- PCI Reset#
-
-  PCI_Devsel_n: out std_logic;  -- PCI Devsel#
-  PCI_Trdy_n: out std_logic;    -- PCI Trdy#
-  PCI_Stop_n: out std_logic;    -- PCI Stop#
-  OE_AD: out std_logic;         -- PCI AD bus enable
-  OE_Trdy_n: out std_logic;     -- PCI Trdy# enable
-  OE_Stop_n: out std_logic;     -- PCI Stop# enable
-  OE_Devsel_n: out std_logic    -- PCI Devsel# enable
-  );
-end pci_target;
-
-architecture fsm of pci_target is
-
-  signal LPCI_Devsel_n, LPCI_Trdy_n, LPCI_Stop_n: std_logic;
-
-  subtype targetFsmType is std_logic_vector(2 downto 0);
-
-  constant Idle:    targetFsmType := "000";
-  constant B_Busy:  targetFsmType := "001";
-  constant Backoff: targetFsmType := "011";
-  constant S_Data:  targetFsmType := "110";
-  constant Turn_Ar: targetFsmType := "100";
-
-  signal currState, nextState: targetFsmType;
-
-begin
-
- nxtStProc: process (currState, PCI_Frame_n, Hit, D_Done, PCI_Irdy_n, LPCI_Trdy_n,
-                     LPCI_Devsel_n, LPCI_Stop_n, Term, Ready) begin
-   case currState is
-     when Idle  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_Busy;
-      else
-        nextState <= Idle;
-      end if;
-
-    when B_Busy =>
-      if (PCI_Frame_n ='1' and D_Done = '1') or
-	     (PCI_Frame_n = '1' and D_Done = '0' and LPCI_Devsel_n = '0') then
-        nextState <= Idle;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '0' or (Term = '1' and Ready = '1') ) then
-        nextState <= S_Data;
-      elsif (PCI_Frame_n = '0' or PCI_Irdy_n = '0') and Hit = '1' and
-		    (Term = '1' and Ready = '0') then
-        nextState <= Backoff;
-      else
-        nextState <= B_Busy;
-      end if;
-
-    when S_Data =>
-      if PCI_Frame_n = '0' and LPCI_Stop_n = '0' and
-         (LPCI_Trdy_n = '1' or PCI_Irdy_n = '0') then
-        nextState <= Backoff;
-      elsif PCI_Frame_n = '1' and (LPCI_Trdy_n = '0' or LPCI_Stop_n = '0') then
-        nextState <= Turn_Ar;
-      else
-        nextState <= S_Data;
-      end if;
-
-
-    when Backoff =>
-      if PCI_Frame_n = '1' then
-        nextState <= Turn_Ar;
-      else
-        nextState <= Backoff;
-      end if;
-
-    when Turn_Ar  =>
-      if (PCI_Frame_n = '0' and Hit = '0') then
-        nextState <= B_Busy;
-      else
-        nextState <= Idle;
-      end if;
-
-      when others =>
-	    null;
-    end case;
-  end process nxtStProc;
-
-
-  curStProc: process (PCI_Clk, PCI_Reset_n) begin
-    if (PCI_Reset_n = '0') then
-      currState <= Idle;
-    elsif (PCI_Clk'event and PCI_Clk = '1') then
-      currState <= nextState;
-    end if;
-  end process curStProc;
-
-
-  outConProc: process (currState, Ready, T_Abort, Cmd_Write,
-                       Cmd_Read, T_Abort, Term) begin
-    case currState is
-      when S_Data =>
-        if (Cmd_Read = '1') then 
-          OE_AD <= '1';
-        else
-          OE_AD <= '0';
-        end if;
-
-        if (Ready = '1' and T_Abort = '0' and (Cmd_Write = '1' or Cmd_Read = '1')) then
-          LPCI_Trdy_n <= '0';
-        else
-          LPCI_Trdy_n <= '1';
-        end if;
-
-        if (T_Abort = '1' or Term = '1') and (Cmd_Write = '1' or Cmd_Read = '1')  then
-          LPCI_Stop_n <= '0';
-        else
-          LPCI_Stop_n <= '1';
-        end if;
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when Backoff =>
-        if (Cmd_Read = '1') then 
-          OE_AD <= '1';
-        else
-          OE_AD <= '0';
-        end if;
-
-        LPCI_Stop_n <= '0';
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-        if (T_Abort = '0') then
-          LPCI_Devsel_n <= '0';
-        else
-          LPCI_Devsel_n <= '1';
-        end if;
-
-      when Turn_Ar =>
-
-        OE_Trdy_n <= '1';
-        OE_Stop_n <= '1';
-        OE_Devsel_n <= '1';
-
-      when others =>
-
-        OE_Trdy_n <= '0';
-        OE_Stop_n <= '0';
-        OE_Devsel_n <= '0';
-        OE_AD <= '0';
-        LPCI_Trdy_n <= '1';
-        LPCI_Stop_n <= '1';
-        LPCI_Devsel_n <= '1';
-
-    end case;
-
-  end process outConProc;
-
-  PCI_Devsel_n <= LPCI_Devsel_n;
-  PCI_Trdy_n <= LPCI_Trdy_n;
-  PCI_Stop_n <= LPCI_Stop_n;
-
-end fsm;
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity test is port (
-  a: in std_logic;
-  z: out std_logic;
-  en: in std_logic
-  );
-end test;
-
-architecture simple of test is
-
-begin
-
-  z <= a when en = '1' else 'z';
-
-end simple;
diff --git a/tests/ctags/test.vhd.tags b/tests/ctags/test.vhd.tags
deleted file mode 100644
index 7bd919f752..0000000000
--- a/tests/ctags/test.vhd.tags
+++ /dev/null
@@ -1,358 +0,0 @@
-# format=tagmanager
-ADlyÌ16384Ö0
-AND2Ì1Ö0
-AND2Ì64Ö0
-AtcStatusRegÌ16384Ö0
-BDlyÌ16384Ö0
-BIDIRÌ1Ö0
-BIDIRÌ64Ö0
-B_BusyÌ16384Ö0
-BackoffÌ16384Ö0
-BidirBufÌ1Ö0
-BidirBufÌ64Ö0
-BidirCntÌ1Ö0
-CaptureOutputsÌ16384Ö0
-ClkDlyÌ16384Ö0
-ClkPeriodÌ16384Ö0
-CntÌ16384Ö0
-Cnt4TermÌ1Ö0
-Cnt4TermÌ64Ö0
-CntLÌ16384Ö0
-CntValÌ16384Ö0
-ConstÌ16384Ö0
-CounterÌ1Ö0
-CtrlBitsÌ4096Ö0
-CtrlRegRangeÌ16384Ö0
-DEC2x4Ì16Ö0
-DFFÌ1Ö0
-DFFEÌ1Ö0
-DFFEÌ64Ö0
-DFFE_SRÌ1Ö0
-DFFE_SRÌ64Ö0
-DLATCHHÌ1Ö0
-DLATCHHÌ64Ö0
-DelayMuxÌ64Ö0
-Dont_CareÌ16384Ö0
-ErrorMsgÌ16384Ö0
-ErrorMsgLineÌ16384Ö0
-FEWGATESÌ1Ö0
-FlopOutÌ16384Ö0
-ForceShareÌ1Ö0
-FoundErrorÌ16384Ö0
-GatesPkgÌ256Ö0
-INVERTERÌ1Ö0
-INVERTERÌ64Ö0
-IdleÌ16384Ö0
-IntCtrlRegÌ16384Ö0
-IoIntStatRegÌ16384Ö0
-LPCI_Devsel_nÌ16384Ö0
-LPCI_Stop_nÌ16384Ö0
-LPCI_Trdy_nÌ16384Ö0
-Latc_stat_rd_nÌ16384Ö0
-Lint_ctrl_rd_nÌ16384Ö0
-Lio_int_stat_rd_nÌ16384Ö0
-Lmgmt_stat_rd_nÌ16384Ö0
-LoadCntÌ1Ö0
-LoadCntÌ64Ö0
-LoadValÌ16384Ö0
-LogicFcnÌ1Ö0
-LoopCountÌ16384Ö0
-LoopStimÌ64Ö0
-Lrst_ctrl_rd_nÌ16384Ö0
-Lsio_dec_nÌ16384Ö0
-MgmtStatusRegÌ16384Ö0
-NumVectorsÌ16384Ö0
-OR2Ì1Ö0
-OR2Ì64Ö0
-OrGateÌ16384Ö0
-OrGateDlyÌ16384Ö0
-PowÌ16Ö0
-PowerÌ1Ö0
-PowerÌ64Ö0
-PowerPkgÌ256Ö0
-PropDelayÌ16384Ö0
-QoutÌ16384Ö0
-ResultÌ16384Ö0
-RollValÌ16Ö0
-RstCtrlRegÌ16384Ö0
-SRFFÌ1Ö0
-S_DataÌ16384Ö0
-SimDFFÌ1Ö0
-SimDFFÌ64Ö0
-SimLoopDelayÌ16384Ö0
-SimModelÌ2048Ö0
-StimInputsÌ16384Ö0
-SuperIoRangeÌ16384Ö0
-THREEÌ16384Ö0
-TRIBUFÌ1Ö0
-TRIBUFÌ64Ö0
-TRIBUF8Ì1Ö0
-TempVectorÌ16384Ö0
-TestClkÌ16384Ö0
-Turn_ArÌ16384Ö0
-VectorLineÌ16384Ö0
-VectorValidÌ16384Ö0
-a_and_bÌ16384Ö0
-accumLÌ16384Ö0
-accumulateÌ64Ö0
-accumulatorÌ1Ö0
-adderÌ1Ö0
-andSignalÌ16384Ö0
-andTermÌ16384Ö0
-asyncLdCntÌ1Ö0
-asyncLoadÌ1Ö0
-atc_stat_rd_nÌ4096Ö0
-bad_charcodeÌ16384Ö0
-basicÌ2048Ö0
-bcd2sevSegÌ64Ö0
-behavÌ2048Ö0
-behaveÌ2048Ö0
-behaviorÌ2048Ö0
-behavioralÌ2048Ö0
-behaviourÌ2048Ö0
-bidirBufÌ64Ö0
-bidirbufferÌ1Ö0
-bitposÌ16384Ö0
-bodyÌ256Ö0
-cÌ16384Ö0
-c_and_dÌ16384Ö0
-carryÌ16384Ö0
-char2char_tÌ4096Ö0
-charcodeÌ16384Ö0
-charposÌ16384Ö0
-clkGenÌ1Ö0
-clkTableÌ16384Ö0
-clkTableTypeÌ4096Ö0
-cntÌ16384Ö0
-cntLÌ16384Ö0
-compareÌ1Ö0
-compareÌ64Ö0
-compareDCÌ1Ö0
-concatÌ2048Ö0
-concurrentÌ2048Ö0
-convertArithÌ1Ö0
-count8Ì1Ö0
-countLÌ16384Ö0
-counterÌ1Ö0
-counterÌ64Ö0
-curStProcÌ64Ö0
-currStProcÌ64Ö0
-currStateÌ16384Ö0
-dÌ16384Ö0
-dataflowÌ2048Ö0
-decProcsÌ256Ö0
-decoderÌ1Ö0
-decoderÌ64Ö0
-decrementÌ64Ö0
-delayCntÌ16384Ö0
-delayCntValÌ16384Ö0
-delayRegÌ64Ö0
-delayregÌ64Ö0
-demoÌ64Ö0
-dffÌ16Ö0
-dffTriÌ1Ö0
-digitÌ16384Ö0
-digit2int_tÌ4096Ö0
-doneÌ16384Ö0
-downCntÌ16384Ö0
-downCntDataÌ16384Ö0
-downCntEnÌ16384Ö0
-downCntLÌ16384Ö0
-downCntLdÌ16384Ö0
-downCntrÌ64Ö0
-downCounterÌ1Ö0
-enableÌ64Ö0
-encodeÌ64Ö0
-encoderÌ1Ö0
-endPulseÌ16384Ö0
-equalProcÌ64Ö0
-f_logic_to_characterÌ16384Ö0
-f_logic_to_character_tÌ4096Ö0
-fcnÌ64Ö0
-flipFlopÌ1Ö0
-fsmÌ2048Ö0
-fsmTypeÌ4096Ö0
-funkyÌ2048Ö0
-genXorÌ16384Ö0
-goodlengthÌ16384Ö0
-hex_bits_per_digitÌ16384Ö0
-hex_logic_vectorÌ16384Ö0
-hex_logic_vector_tÌ4096Ö0
-hexdigit2intÌ16384Ö0
-hexint2logicÌ16384Ö0
-hexint2logic_tÌ4096Ö0
-hierarchicalÌ2048Ö0
-iÌ16384Ö0
-incrementÌ64Ö0
-indexÌ16384Ö0
-inputValIntÌ16384Ö0
-instanceÌ2048Ö0
-int2hexdigitÌ16384Ö0
-int2hexdigit_tÌ4096Ö0
-int2octdigitÌ16384Ö0
-int2octdigit_tÌ4096Ö0
-int_ctrl_rd_nÌ4096Ö0
-integer_valueÌ16384Ö0
-io1164Ì256Ö0
-io_int_stat_rd_nÌ4096Ö0
-isa_decÌ1Ö0
-isxÌ16384Ö0
-la_nÌ16384Ö0
-lastAssignmentÌ1Ö0
-lb_nÌ16384Ö0
-lc_nÌ16384Ö0
-ld_nÌ16384Ö0
-le_nÌ16384Ö0
-lengthRegÌ64Ö0
-lf_nÌ16384Ö0
-lg_nÌ16384Ö0
-loadCntÌ1Ö0
-loadCntÌ64Ö0
-loadCntTBÌ1Ö0
-loadDelayCntÌ16384Ö0
-loadLengthCntÌ16384Ö0
-loadValÌ16384Ö0
-localRstÌ16384Ö0
-localSumÌ16384Ö0
-localYÌ16384Ö0
-logic_valueÌ16384Ö0
-lookupTableÌ64Ö0
-loopDemoÌ2048Ö0
-loopXorÌ16384Ö0
-lowcaseÌ16384Ö0
-mÌ16384Ö0
-maxhex_charcodeÌ16384Ö0
-maxoct_charcodeÌ16384Ö0
-mgmt_stat_rd_nÌ4096Ö0
-multiDriverÌ2048Ö0
-multiplierÌ1Ö0
-muxÌ1Ö0
-nextStProcÌ64Ö0
-nextStateÌ16384Ö0
-notAÌ16384Ö0
-notBÌ16384Ö0
-not_c_and_dÌ16384Ö0
-numClksÌ4096Ö0
-numPatternsÌ4096Ö0
-nxtStProcÌ64Ö0
-oct_bits_per_digitÌ16384Ö0
-oct_logic_vectorÌ16384Ö0
-oct_logic_vector_tÌ4096Ö0
-octdigit2intÌ16384Ö0
-octint2logicÌ16384Ö0
-octint2logic_tÌ4096Ö0
-oddParityGenÌ1Ö0
-oddParityLoopÌ1Ö0
-oeÌ16384Ö0
-old_lÌ16384Ö0
-oneÌ16384Ö0
-outConProcÌ64Ö0
-outputsÌ64Ö0
-pAdderAttrÌ1Ö0
-paramDFFÌ1Ö0
-parameterizeÌ2048Ö0
-pci_targetÌ1Ö0
-posÌ16384Ö0
-powerLÌ16384Ö0
-powerOfFourÌ1Ö0
-primitiveÌ256Ö0
-priority_encoderÌ1Ö0
-progPulseÌ1Ö0
-progPulseFsmÌ1Ö0
-progPulseFsmTypeÌ4096Ö0
-pulseÌ64Ö0
-pulseCntÌ16384Ö0
-pulseCntValÌ16384Ö0
-pulseDelayÌ64Ö0
-pulseErrÌ1Ö0
-pulseLengthÌ64Ö0
-pulseOutputÌ64Ö0
-qÌ16384Ö0
-qLocalÌ16384Ö0
-qualifyÌ64Ö0
-readÌ16Ö0
-readVecÌ64Ö0
-read_hexÌ16Ö0
-read_octÌ16Ö0
-regÌ64Ö0
-regÌ4096Ö0
-regÌ16384Ö0
-regArrayÌ4096Ö0
-regFileÌ1Ö0
-regProcÌ64Ö0
-registerFileÌ16384Ö0
-resFcnDemoÌ1Ö0
-resetLatchÌ64Ö0
-resultÌ16384Ö0
-rst_ctrl_rd_nÌ4096Ö0
-rtlÌ2048Ö0
-scalableÌ2048Ö0
-scaleDFFÌ1Ö0
-scaleUpCntÌ1Ö0
-scaleUpCntÌ64Ö0
-scaleableÌ256Ö0
-scaleableÌ2048Ö0
-selectInÌ16384Ö0
-sequentialÌ2048Ö0
-sevenSegmentÌ1Ö0
-sevenSegmentÌ64Ö0
-sevenSegmentTBÌ1Ö0
-shiftÌ64Ö0
-shifterÌ1Ö0
-signalDemoÌ1Ö0
-simHierarchyÌ1Ö0
-simModelÌ2048Ö0
-simPrimitivesÌ256Ö0
-simpleÌ2048Ö0
-sio_dec_nÌ4096Ö0
-stage0Ì16384Ö0
-stage1Ì16384Ö0
-stage2Ì16384Ö0
-stage3Ì16384Ö0
-stage4Ì16384Ö0
-startPulseÌ16384Ö0
-stateBitsÌ4096Ö0
-stateTableÌ16384Ö0
-stateVecÌ4096Ö0
-struct_dffeÌ1Ö0
-struct_dffe_srÌ1Ö0
-struct_dlatchÌ1Ö0
-structuralÌ2048Ö0
-successÌ16384Ö0
-sumÌ64Ö0
-synthesisÌ2048Ö0
-tCQÌ16384Ö0
-tHÌ16384Ö0
-tPD_AÌ16384Ö0
-tPD_BÌ16384Ö0
-tPD_SelÌ16384Ö0
-tSÌ16384Ö0
-targetFsmTypeÌ4096Ö0
-tempSumÌ16384Ö0
-termCntÌ16384Ö0
-testÌ1Ö0
-testVectorÌ16384Ö0
-testbenchÌ2048Ö0
-triÌ16384Ö0
-tribufArrayTypeÌ4096Ö0
-tribufTypeÌ4096Ö0
-tribufferÌ1Ö0
-typeConvertÌ1Ö0
-unnamedÌ64Ö0
-upperÌ4096Ö0
-vDataÌ16384Ö0
-vLoadÌ16384Ö0
-vQÌ16384Ö0
-vRstÌ16384Ö0
-vectorÌ4096Ö0
-vectorArrayÌ4096Ö0
-vectorTableÌ16384Ö0
-vectorTypeÌ4096Ö0
-verifyÌ64Ö0
-waitDelayEndÌ16384Ö0
-waitLengthEndÌ16384Ö0
-wontWorkÌ2048Ö0
-writeÌ16Ö0
-write_hexÌ16Ö0
-write_octÌ16Ö0
-x_charcodeÌ16384Ö0
diff --git a/tests/ctags/vhdl-component.vhd b/tests/ctags/vhdl-component.vhd
new file mode 100644
index 0000000000..09c40c38bf
--- /dev/null
+++ b/tests/ctags/vhdl-component.vhd
@@ -0,0 +1,54 @@
+-- Taken from a comment https://github.com/universal-ctags/ctags/issues/2678
+-- submitted by @pidgeon777
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ENTITY_TOP is
+  generic (
+    GEN : integer := 0
+  );
+  port (
+    INP : in std_logic
+  );
+end entity;
+
+architecture arch of ENTITY_TOP is
+  signal sig : std_logic := '0';
+
+  component ENTITY_1
+    generic (
+      GEN : integer := 0
+    );
+    port (
+      INP : in std_logic
+    );
+  end component;
+
+  component ENTITY_2
+    generic (
+      GEN : integer := 0
+    );
+    port (
+      INP : in std_logic
+    );
+  end component;
+
+begin
+
+  ENTITY_1_i : ENTITY_1
+  generic map(
+    GEN => 0
+  )
+  port map(
+    INP => '0'
+  );
+
+  ENTITY_2_i : ENTITY_2
+  generic map(
+    GEN => 0
+  )
+  port map(
+    INP => '0'
+  );
+
+end architecture;
diff --git a/tests/ctags/vhdl-component.vhd.tags b/tests/ctags/vhdl-component.vhd.tags
new file mode 100644
index 0000000000..4b2a0dc6b2
--- /dev/null
+++ b/tests/ctags/vhdl-component.vhd.tags
@@ -0,0 +1,6 @@
+# format=tagmanager
+ENTITY_1Ì64Ö0
+ENTITY_2Ì64Ö0
+ENTITY_TOPÌ1Ö0
+archÌ2048Ö0
+sigÌ16384Ö0
diff --git a/tests/ctags/vhdl-local.vhd b/tests/ctags/vhdl-local.vhd
new file mode 100644
index 0000000000..02d73e4af1
--- /dev/null
+++ b/tests/ctags/vhdl-local.vhd
@@ -0,0 +1,203 @@
+--
+-- Taken from rtl/commonlib/types_util.vhd of https://github.com/sergeykhbr/riscv_vhdl
+--
+-----------------------------------------------------------------------------
+--! @file
+--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
+--! @author    Sergey Khabarov - sergeykhbr@gmail.com
+--! @brief	    Package for common testbenches implementation.
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+package types_util is
+
+function strlen(s: in string) return integer;
+function StringToUVector(inStr: string) return std_ulogic_vector;
+function StringToSVector(inStr: string) return std_logic_vector;
+function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
+function SignalFromString(inStr: string; ind : integer ) return std_logic;
+function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
+
+function tost(v:std_logic_vector) return string;
+function tost(v:std_logic) return string;
+function tost(i : integer) return string;
+procedure print(s : string);
+
+end;
+
+package body types_util is
+
+  function strlen(s: in string) return integer is
+    variable n: integer:=0; variable sj: integer:=s'left;
+  begin
+    loop
+      if    sj>s'right then exit;
+      elsif s(sj)=NUL  then exit; --sequential if protects sj > length
+      else                  sj:=sj+1; n:=n+1;
+      end if;
+    end loop;
+    return n;
+  end strlen;
+
+  function SignalFromString(inStr: string; ind : integer ) return std_logic is
+    variable temp: std_logic := 'X';
+  begin
+    if(inStr(inStr'high-ind)='1')    then temp := '1';
+    elsif(inStr(inStr'high-ind)='0') then temp := '0';
+    end if;
+    return temp;
+  end function SignalFromString;
+
+
+  function StringToUVector(inStr: string) return std_ulogic_vector is
+    variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
+  begin
+    for i in inStr'range loop --
+      if(inStr(inStr'high-i+1)='1')    then temp(i) := '1';
+      elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
+      end if;
+    end loop;
+    return temp(inStr'high downto 1);
+  end function StringToUVector;
+  -- conversion function
+  
+  function StringToSVector(inStr: string) return std_logic_vector is
+    variable temp: std_logic_vector(inStr'range) := (others => 'X');
+  begin
+    for i in inStr'range loop --
+      if(inStr(inStr'high-i+1)='1')    then temp(i) := '1';
+      elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
+      end if;
+    end loop;
+    return temp(inStr'high downto 1);
+  end function StringToSVector;
+
+  function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
+    constant ss: string(1 to inStr'length) := inStr;
+    variable c : integer;
+    variable temp: std_logic_vector(7 downto 0) := (others => 'X');
+  begin
+    c := character'pos(ss(idx+1));
+    for i in 0 to 7 loop --
+      temp(i) := to_unsigned(c,8)(i);
+    end loop;
+    return temp;
+  end function SymbolToSVector;
+  
+
+  function UnsignedToSigned(inUnsigned: std_ulogic_vector) 
+    return std_logic_vector is
+    variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
+    variable i: integer:=0;
+  begin
+    while i < inUnsigned'length loop
+      if(inUnsigned(i)='1')    then temp(i) := '1';
+      elsif(inUnsigned(i)='0') then temp(i) := '0';
+      end if;
+      i := i+1;
+    end loop;
+    return temp;
+  end function UnsignedToSigned;
+
+
+  subtype nibble is std_logic_vector(3 downto 0);
+
+  function todec(i:integer) return character is
+  begin
+    case i is
+    when 0 => return('0');
+    when 1 => return('1');
+    when 2 => return('2');
+    when 3 => return('3');
+    when 4 => return('4');
+    when 5 => return('5');
+    when 6 => return('6');
+    when 7 => return('7');
+    when 8 => return('8');
+    when 9 => return('9');
+    when others => return('0');
+    end case;
+  end;
+
+
+  function tohex(n:nibble) return character is
+  begin
+    case n is
+    when "0000" => return('0');
+    when "0001" => return('1');
+    when "0010" => return('2');
+    when "0011" => return('3');
+    when "0100" => return('4');
+    when "0101" => return('5');
+    when "0110" => return('6');
+    when "0111" => return('7');
+    when "1000" => return('8');
+    when "1001" => return('9');
+    when "1010" => return('a');
+    when "1011" => return('b');
+    when "1100" => return('c');
+    when "1101" => return('d');
+    when "1110" => return('e');
+    when "1111" => return('f');
+    when others => return('X');
+    end case;
+  end;
+
+
+  function tost(v:std_logic_vector) return string is
+    constant vlen : natural := v'length; --'
+    constant slen : natural := (vlen+3)/4;
+    variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
+    variable s : string(1 to slen);
+    variable nz : boolean := false;
+    variable index : integer := -1;
+  begin
+    vv(slen*4-vlen to slen*4-1) := v;
+    for i in 0 to slen-1 loop
+      if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
+        index := i;
+      else
+        nz := false;
+        s(i+1) := tohex(vv(i*4 to i*4+3));
+      end if;
+    end loop;
+    if ((index +2) = slen) then return(s(slen to slen));
+    else return(string'("0x") & s(index+2 to slen)); end if; --'
+  end;
+
+
+  function tost(v:std_logic) return string is
+  begin
+    if to_x01(v) = '1' then return("1"); else return("0"); end if;
+  end;
+
+
+  function tost(i : integer) return string is
+    variable L : line;
+    variable s, x : string(1 to 128);
+    variable n, tmp : integer := 0;
+  begin
+    tmp := i;
+    if i < 0 then tmp := -i; end if;
+    loop
+      s(128-n) := todec(tmp mod 10);
+      tmp := tmp / 10;
+      n := n+1;
+      if tmp = 0 then exit; end if;
+    end loop;
+    x(1 to n) := s(129-n to 128);
+    if i < 0 then return "-" & x(1 to n); end if;
+    return(x(1 to n));
+  end;
+
+  procedure print(s : string) is
+    variable L : line;
+  begin
+    L := new string'(s); writeline(output, L);
+  end;
+
+end;
diff --git a/tests/ctags/vhdl-local.vhd.tags b/tests/ctags/vhdl-local.vhd.tags
new file mode 100644
index 0000000000..4a5608e5a0
--- /dev/null
+++ b/tests/ctags/vhdl-local.vhd.tags
@@ -0,0 +1,27 @@
+# format=tagmanager
+LÌ16384Ö0
+SignalFromStringÌ16Ö0
+StringToSVectorÌ16Ö0
+StringToUVectorÌ16Ö0
+SymbolToSVectorÌ16Ö0
+UnsignedToSignedÌ16Ö0
+bodyÌ256Ö0
+cÌ16384Ö0
+iÌ16384Ö0
+indexÌ16384Ö0
+nÌ16384Ö0
+nibbleÌ4096Ö0
+nzÌ16384Ö0
+printÌ16Ö0
+sÌ16384Ö0
+sjÌ16384Ö0
+slenÌ16384Ö0
+ssÌ16384Ö0
+strlenÌ16Ö0
+tempÌ16384Ö0
+todecÌ16Ö0
+tohexÌ16Ö0
+tostÌ16Ö0
+types_utilÌ256Ö0
+vlenÌ16384Ö0
+vvÌ16384Ö0
diff --git a/tests/ctags/vhdl-port.vhd b/tests/ctags/vhdl-port.vhd
new file mode 100644
index 0000000000..22e83f30ff
--- /dev/null
+++ b/tests/ctags/vhdl-port.vhd
@@ -0,0 +1,5 @@
+-- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
+entity logical_ops_1 is
+  port (a, b, c, d: in bit;
+        m: out bit);
+end logical_ops_1;
diff --git a/tests/ctags/vhdl-port.vhd.tags b/tests/ctags/vhdl-port.vhd.tags
new file mode 100644
index 0000000000..94b6696ffa
--- /dev/null
+++ b/tests/ctags/vhdl-port.vhd.tags
@@ -0,0 +1,2 @@
+# format=tagmanager
+logical_ops_1Ì1Ö0
diff --git a/tests/ctags/vhdl-process.vhd b/tests/ctags/vhdl-process.vhd
new file mode 100644
index 0000000000..90f0d68dea
--- /dev/null
+++ b/tests/ctags/vhdl-process.vhd
@@ -0,0 +1,51 @@
+--
+-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
+--
+-----------------------------------------------------------------------------
+--! @file
+--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
+--! @author    Sergey Khabarov - sergeykhbr@gmail.com
+--! @brief     Stack trace buffer on hardware level.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+library commonlib;
+use commonlib.types_common.all;
+
+entity StackTraceBuffer is 
+  generic (
+    abits : integer := 5;
+    dbits : integer := 64
+  );
+  port (
+    i_clk   : in std_logic;
+    i_raddr : in std_logic_vector(abits-1 downto 0);
+    o_rdata : out std_logic_vector(dbits-1 downto 0);
+    i_we    : in std_logic;
+    i_waddr : in std_logic_vector(abits-1 downto 0);
+    i_wdata : in std_logic_vector(dbits-1 downto 0)
+  );
+end; 
+ 
+architecture arch_StackTraceBuffer of StackTraceBuffer is
+
+  type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
+  signal stackbuf    : ram_type;
+  signal raddr       : std_logic_vector(abits-1 downto 0);
+
+begin
+
+  -- registers:
+  regs : process(i_clk) begin 
+    if rising_edge(i_clk) then 
+      if i_we = '1' then
+        stackbuf(conv_integer(i_waddr)) <= i_wdata; 
+      end if;
+      raddr <= i_raddr;
+    end if;
+  end process;
+  
+  o_rdata <= stackbuf(conv_integer(raddr));
+
+end;
diff --git a/tests/ctags/vhdl-process.vhd.tags b/tests/ctags/vhdl-process.vhd.tags
new file mode 100644
index 0000000000..6972ae1103
--- /dev/null
+++ b/tests/ctags/vhdl-process.vhd.tags
@@ -0,0 +1,7 @@
+# format=tagmanager
+StackTraceBufferÌ1Ö0
+arch_StackTraceBufferÌ2048Ö0
+raddrÌ16384Ö0
+ram_typeÌ4096Ö0
+regsÌ64Ö0
+stackbufÌ16384Ö0
diff --git a/tests/ctags/vhdl-type.vhd b/tests/ctags/vhdl-type.vhd
new file mode 100644
index 0000000000..4e17158318
--- /dev/null
+++ b/tests/ctags/vhdl-type.vhd
@@ -0,0 +1,325 @@
+--
+-- Taken from rtl/misclib/types_misc.vhd of https://github.com/sergeykhbr/riscv_vhdl
+--
+--!
+--! Copyright 2018 Sergey Khabarov, sergeykhbr@gmail.com
+--!
+--! Licensed under the Apache License, Version 2.0 (the "License");
+--! you may not use this file except in compliance with the License.
+--! You may obtain a copy of the License at
+--!
+--!     http://www.apache.org/licenses/LICENSE-2.0
+--! Unless required by applicable law or agreed to in writing, software
+--! distributed under the License is distributed on an "AS IS" BASIS,
+--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+--! See the License for the specific language governing permissions and
+--! limitations under the License.
+--!
+
+--! Standard library.
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library commonlib;
+use commonlib.types_common.all;
+--! Technology definition library.
+library techmap;
+use techmap.gencomp.all;
+--! CPU, System Bus and common peripheries library.
+library ambalib;
+use ambalib.types_amba4.all;
+use ambalib.types_bus0.all;
+
+--! @brief   Declaration of components visible on SoC top level.
+package types_misc is
+
+--! @defgroup irq_id_group AXI4 interrupt generic IDs.
+--! @ingroup axi4_config_generic_group
+--! @details Unique indentificator of the interrupt pin also used
+--!          as an index in the interrupts bus.
+--! @{
+
+--! Zero interrupt index must be unused.
+constant CFG_IRQ_UNUSED         : integer := 0;
+--! UART_A interrupt pin.
+constant CFG_IRQ_UART1          : integer := 1;
+--! Ethernet MAC interrupt pin.
+constant CFG_IRQ_ETHMAC         : integer := 2;
+--! GP Timers interrupt pin
+constant CFG_IRQ_GPTIMERS       : integer := 3;
+--! GNSS Engine IRQ pin that generates 1 msec pulses.
+constant CFG_IRQ_GNSSENGINE     : integer := 4;
+--! Total number of used interrupts in a system
+constant CFG_IRQ_TOTAL          : integer := 5;
+--! @}
+
+--! @brief SOC global reset former.
+--! @details This module produces output reset signal in a case if
+--!          button 'Reset' was pushed or PLL isn't a 'lock' state.
+--! param[in]  inSysReset Button generated signal
+--! param[in]  inSysClk Clock from the PLL. Bus clock.
+--! param[out] outReset Output reset signal with active 'High' (1 = reset).
+component reset_global
+port (
+  inSysReset  : in std_ulogic;
+  inSysClk    : in std_ulogic;
+  outReset    : out std_ulogic );
+end component;
+
+
+--! Boot ROM with AXI4 interface declaration.
+component axi4_rom is
+generic (
+    memtech  : integer := inferred;
+    async_reset : boolean := false;
+    xaddr    : integer := 0;
+    xmask    : integer := 16#fffff#;
+    sim_hexfile : string
+  );
+port (
+    clk  : in std_logic;
+    nrst : in std_logic;
+    cfg  : out axi4_slave_config_type;
+    i    : in  axi4_slave_in_type;
+    o    : out axi4_slave_out_type
+  );
+end component; 
+
+--! Internal RAM with AXI4 interface declaration.
+component axi4_sram is
+  generic (
+    memtech  : integer := inferred;
+    async_reset : boolean := false;
+    xaddr    : integer := 0;
+    xmask    : integer := 16#fffff#;
+    abits    : integer := 17;
+    init_file : string := "" -- only for 'inferred'
+  );
+  port (
+    clk  : in std_logic;
+    nrst : in std_logic;
+    cfg  : out axi4_slave_config_type;
+    i    : in  axi4_slave_in_type;
+    o    : out axi4_slave_out_type
+  );
+end component; 
+
+--! AXI4 to SPI brdige for external Flash IC Micron M25AA1024
+type spi_in_type is record
+    SDI : std_logic;
+end record;
+
+type spi_out_type is record
+    SDO : std_logic;
+    SCK : std_logic;
+    nCS : std_logic;
+    nWP : std_logic;
+    nHOLD : std_logic;
+    RESET : std_logic;
+end record;
+
+constant spi_out_none : spi_out_type := (
+  '0', '0', '1', '1', '1', '0'
+);
+
+component axi4_flashspi is
+  generic (
+    async_reset : boolean := false;
+    xaddr   : integer := 0;
+    xmask   : integer := 16#fffff#;
+    wait_while_write : boolean := true  -- hold AXI bus response until end of write cycle
+  );
+  port (
+    clk    : in  std_logic;
+    nrst   : in  std_logic;
+    cfg    : out axi4_slave_config_type;
+    i_spi  : in  spi_in_type;
+    o_spi  : out spi_out_type;
+    i_axi  : in  axi4_slave_in_type;
+    o_axi  : out axi4_slave_out_type  );
+end component; 
+
+--! @brief AXI4 GPIO controller
+component axi4_gpio is
+  generic (
+    async_reset : boolean := false;
+    xaddr    : integer := 0;
+    xmask    : integer := 16#fffff#;
+    xirq     : integer := 0;
+    width    : integer := 12
+  );
+  port (
+    clk  : in std_logic;
+    nrst : in std_logic;
+    cfg  : out axi4_slave_config_type;
+    i    : in  axi4_slave_in_type;
+    o    : out axi4_slave_out_type;
+    i_gpio : in std_logic_vector(width-1 downto 0);
+    o_gpio : out std_logic_vector(width-1 downto 0);
+    o_gpio_dir : out std_logic_vector(width-1 downto 0)
+  );
+end component; 
+
+type uart_in_type is record
+  rd   	: std_ulogic;
+  cts   : std_ulogic;
+end record;
+
+type uart_out_type is record
+  td   	: std_ulogic;
+  rts   : std_ulogic;
+end record;
+
+--! UART with the AXI4 interface declaration.
+component axi4_uart is
+  generic (
+    async_reset : boolean := false;
+    xaddr   : integer := 0;
+    xmask   : integer := 16#fffff#;
+    xirq    : integer := 0;
+    fifosz  : integer := 16
+  );
+  port (
+    clk    : in  std_logic;
+    nrst   : in  std_logic;
+    cfg    : out axi4_slave_config_type;
+    i_uart : in  uart_in_type;
+    o_uart : out uart_out_type;
+    i_axi  : in  axi4_slave_in_type;
+    o_axi  : out axi4_slave_out_type;
+    o_irq  : out std_logic);
+end component;
+
+--! Test Access Point via UART (debug access)
+component uart_tap is
+  port (
+    nrst     : in std_logic;
+    clk      : in std_logic;
+    i_uart   : in  uart_in_type;
+    o_uart   : out uart_out_type;
+    i_msti   : in axi4_master_in_type;
+    o_msto   : out axi4_master_out_type;
+    o_mstcfg : out axi4_master_config_type
+  );
+end component; 
+
+-- JTAG TAP
+component tap_jtag is
+  generic (
+    ainst  : integer range 0 to 255 := 2;
+    dinst  : integer range 0 to 255 := 3);
+  port (
+    nrst  : in std_logic;
+    clk  : in std_logic;
+    i_tck   : in std_logic;   -- in: Test Clock
+    i_ntrst   : in std_logic;   -- in: 
+    i_tms   : in std_logic;   -- in: Test Mode State
+    i_tdi   : in std_logic;   -- in: Test Data Input
+    o_tdo   : out std_logic;   -- out: Test Data Output
+    o_jtag_vref : out std_logic;
+    i_msti   : in axi4_master_in_type;
+    o_msto   : out axi4_master_out_type;
+    o_mstcfg : out axi4_master_config_type
+    );
+end component;
+
+
+--! @brief   Interrupt controller with the AXI4 interface declaration.
+--! @details To rise interrupt on certain CPU HostIO interface is used.
+component axi4_irqctrl is
+  generic (
+    async_reset : boolean := false;
+    xaddr    : integer := 0;
+    xmask    : integer := 16#fffff#
+  );
+  port 
+ (
+    clk    : in std_logic;
+    nrst   : in std_logic;
+    i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
+    o_cfg  : out axi4_slave_config_type;
+    i_axi  : in axi4_slave_in_type;
+    o_axi  : out axi4_slave_out_type;
+    o_irq_meip : out std_logic
+  );
+  end component;
+
+  --! @brief   General Purpose Timers with the AXI interface.
+  --! @details This module provides high precision counter and
+  --!          generic number of GP timers.
+  component axi4_gptimers is
+  generic (
+    async_reset : boolean := false;
+    xaddr   : integer := 0;
+    xmask   : integer := 16#fffff#;
+    xirq    : integer := 0;
+    tmr_total  : integer := 2
+  );
+  port (
+    clk    : in  std_logic;
+    nrst   : in  std_logic;
+    cfg    : out axi4_slave_config_type;
+    i_axi  : in  axi4_slave_in_type;
+    o_axi  : out axi4_slave_out_type;
+    o_pwm : out std_logic_vector(tmr_total-1 downto 0);
+    o_irq  : out std_logic
+  );
+  end component; 
+
+--! @brief   Plug-n-Play support module with AXI4 interface declaration.
+--! @details Each device in a system hase to implements sideband signal
+--!          structure 'nasti_slave_config_type' that allows FW to
+--!          detect Hardware configuration in a run-time.
+--! @todo Implements PnP signals for all Masters devices.
+component axi4_pnp is
+  generic (
+    async_reset : boolean := false;
+    xaddr   : integer := 0;
+    xmask   : integer := 16#fffff#;
+    tech    : integer := 0;
+    hw_id   : std_logic_vector(31 downto 0) := X"20170101"
+  );
+  port (
+    sys_clk : in  std_logic;
+    adc_clk : in  std_logic;
+    nrst   : in  std_logic;
+    mstcfg : in  bus0_xmst_cfg_vector;
+    slvcfg : in  bus0_xslv_cfg_vector;
+    cfg    : out  axi4_slave_config_type;
+    i      : in  axi4_slave_in_type;
+    o      : out axi4_slave_out_type;
+    -- OTP Timing control
+    i_otp_busy : in std_logic;
+    o_otp_cfg_rsetup : out std_logic_vector(3 downto 0);
+    o_otp_cfg_wadrsetup : out std_logic_vector(3 downto 0);
+    o_otp_cfg_wactive : out std_logic_vector(31 downto 0);
+    o_otp_cfg_whold : out std_logic_vector(3 downto 0)
+  );
+end component; 
+
+component axi4_otp is
+  generic (
+    async_reset : boolean := false;
+    xaddr   : integer := 0;
+    xmask   : integer := 16#ffffe#
+  );
+  port (
+    clk    : in  std_logic;
+    nrst   : in  std_logic;
+    cfg    : out axi4_slave_config_type;
+    i_axi  : in  axi4_slave_in_type;
+    o_axi  : out axi4_slave_out_type;
+    o_otp_we     : out  std_ulogic;
+    o_otp_re     : out  std_ulogic;
+    o_otp_addr   : out std_logic_vector(11 downto 0);
+    o_otp_wdata  : out std_logic_vector(15 downto 0);
+    i_otp_rdata  : in std_logic_vector(15 downto 0);
+    i_cfg_rsetup : in std_logic_vector(3 downto 0);
+    i_cfg_wadrsetup : in std_logic_vector(3 downto 0);
+    i_cfg_wactive : in std_logic_vector(31 downto 0);
+    i_cfg_whold : in std_logic_vector(3 downto 0);
+    o_busy : out std_logic
+  );
+end component; 
+
+end; -- package declaration
diff --git a/tests/ctags/vhdl-type.vhd.tags b/tests/ctags/vhdl-type.vhd.tags
new file mode 100644
index 0000000000..91ec3e3719
--- /dev/null
+++ b/tests/ctags/vhdl-type.vhd.tags
@@ -0,0 +1,25 @@
+# format=tagmanager
+CFG_IRQ_ETHMACÌ16384Ö0
+CFG_IRQ_GNSSENGINEÌ16384Ö0
+CFG_IRQ_GPTIMERSÌ16384Ö0
+CFG_IRQ_TOTALÌ16384Ö0
+CFG_IRQ_UART1Ì16384Ö0
+CFG_IRQ_UNUSEDÌ16384Ö0
+axi4_flashspiÌ64Ö0
+axi4_gpioÌ64Ö0
+axi4_gptimersÌ64Ö0
+axi4_irqctrlÌ64Ö0
+axi4_otpÌ64Ö0
+axi4_pnpÌ64Ö0
+axi4_romÌ64Ö0
+axi4_sramÌ64Ö0
+axi4_uartÌ64Ö0
+reset_globalÌ64Ö0
+spi_in_typeÌ4096Ö0
+spi_out_noneÌ16384Ö0
+spi_out_typeÌ4096Ö0
+tap_jtagÌ64Ö0
+types_miscÌ256Ö0
+uart_in_typeÌ4096Ö0
+uart_out_typeÌ4096Ö0
+uart_tapÌ64Ö0
diff --git a/tests/meson.build b/tests/meson.build
index 7125f330d0..79b439e063 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -323,7 +323,6 @@ ctags_tests = files([
 	'ctags/test.erl.tags',
 	'ctags/test.go.tags',
 	'ctags/test.py.tags',
-	'ctags/test.vhd.tags',
 	'ctags/test_input.rs.tags',
 	'ctags/test_input2.rs.tags',
 	'ctags/titles.t2t.tags',
@@ -333,6 +332,11 @@ ctags_tests = files([
 	'ctags/union.f.tags',
 	'ctags/value.f.tags',
 	'ctags/var-and-return-type.cpp.tags',
+	'ctags/vhdl-component.vhd.tags',
+	'ctags/vhdl-local.vhd.tags',
+	'ctags/vhdl-port.vhd.tags',
+	'ctags/vhdl-process.vhd.tags',
+	'ctags/vhdl-type.vhd.tags',
 	'ctags/whitespaces.php.tags'
 ])
 

From 8483fc78c1cdb2d58882f59a22a06f7eb61545fb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ji=C5=99=C3=AD=20Techet?= <techet@gmail.com>
Date: Mon, 11 Apr 2022 20:32:36 +0200
Subject: [PATCH 2/2] Use the upstream VHDL parser

The new parser supports scope reporting so update tm_parser_has_full_scope().
---
 ctags/Makefile.am                   |    2 +-
 ctags/parsers/geany_vhdl.c          |  289 -------
 ctags/parsers/vhdl.c                | 1083 +++++++++++++++++++++++++++
 meson.build                         |    2 +-
 src/tagmanager/tm_parser.c          |   36 +-
 tests/ctags/bug2374109.vhd.tags     |    2 +-
 tests/ctags/vhdl-component.vhd.tags |   11 +-
 tests/ctags/vhdl-local.vhd          |    4 +
 tests/ctags/vhdl-local.vhd.tags     |   59 +-
 tests/ctags/vhdl-port.vhd.tags      |    5 +
 tests/ctags/vhdl-process.vhd.tags   |   16 +-
 tests/ctags/vhdl-type.vhd.tags      |  142 +++-
 12 files changed, 1286 insertions(+), 365 deletions(-)
 delete mode 100644 ctags/parsers/geany_vhdl.c
 create mode 100644 ctags/parsers/vhdl.c

diff --git a/ctags/Makefile.am b/ctags/Makefile.am
index fb1d1d5964..82e708d24f 100644
--- a/ctags/Makefile.am
+++ b/ctags/Makefile.am
@@ -93,7 +93,7 @@ parsers = \
 	parsers/geany_tex.c \
 	parsers/txt2tags.c \
 	parsers/verilog.c \
-	parsers/geany_vhdl.c
+	parsers/vhdl.c
 
 # skip cmd.c and mini-geany.c which define main()
 # also skip lregex-pcre2.c which we don't use
diff --git a/ctags/parsers/geany_vhdl.c b/ctags/parsers/geany_vhdl.c
deleted file mode 100644
index f53329da7a..0000000000
--- a/ctags/parsers/geany_vhdl.c
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
-*   $Id: vhdl.c,v 1.0 2005/11/05
-*
-*   Copyright (c) 2005, Klaus Dannecker
-*
-*   This source code is released for free distribution under the terms of the
-*   GNU General Public License.
-*
-*   This module contains functions for generating tags for the Vhdl HDL
-*   (Hardware Description Language).
-*
-*/
-
-/*
- *   INCLUDE FILES
- */
-#include "general.h"    /* must always come first */
-
-#include <string.h>
-#include <setjmp.h>
-
-#include "debug.h"
-#include "keyword.h"
-#include "parse.h"
-#include "read.h"
-#include "routines.h"
-#include "vstring.h"
-
-/*
- *   DATA DECLARATIONS
- */
-typedef enum eException { ExceptionNone, ExceptionEOF } exception_t;
-
-typedef enum {
-	K_UNDEFINED = -1,
-	K_CONSTANT,
-	K_TYPE,
-	K_VARIABLE,
-	K_ATTRIBUTE,
-	K_SIGNAL,
-	K_FUNCTION,
-	K_PROCEDURE,
-	K_COMPONENT,
-	K_PACKAGE,
-	K_PROCESS,
-	K_ENTITY,
-	K_ARCHITECTURE,
-	K_PORT,
-	K_BLOCK,
-	K_ALIAS
-} vhdlKind;
-
-/*
- *   DATA DEFINITIONS
- */
-static int Ungetc;
-static int Lang_vhdl;
-static jmp_buf Exception;
-static vString* Name=NULL;
-static vString* Lastname=NULL;
-static vString* Keyword=NULL;
-static vString* TagName=NULL;
-
-static kindDefinition VhdlKinds [] = {
-	{ true, 'c', "variable",     "constants" },
-	{ true, 't', "typedef",      "types" },
-	{ true, 'v', "variable",     "variables" },
-	{ true, 'a', "attribute",    "attributes" },
-	{ true, 's', "variable",     "signals" },
-	{ true, 'f', "function",     "functions" },
-	{ true, 'p', "function",     "procedure" },
-	{ true, 'k', "member",       "components" },
-	{ true, 'l', "namespace",    "packages" },
-	{ true, 'm', "member",       "process" },
-	{ true, 'n', "class",        "entity" },
-	{ true, 'o', "struct",       "architecture" },
-	{ true, 'u', "port",         "ports" },
-	{ true, 'b', "member",       "blocks" },
-	{ true, 'A', "typedef",      "alias" }
-};
-
-static keywordTable VhdlKeywordTable [] = {
-	{ "constant",     K_CONSTANT },
-	{ "variable",     K_VARIABLE },
-	{ "type",         K_TYPE },
-	{ "subtype",      K_TYPE },
-	{ "signal",       K_SIGNAL },
-	{ "function",     K_FUNCTION },
-	{ "procedure",    K_PROCEDURE },
-	{ "component",    K_COMPONENT },
-	{ "package",      K_PACKAGE },
-	{ "process",      K_PROCESS },
-	{ "entity",       K_ENTITY },
-	{ "architecture", K_ARCHITECTURE },
-	{ "inout",        K_PORT },
-	{ "in",           K_PORT },
-	{ "out",          K_PORT },
-	{ "block",        K_BLOCK },
-	{ "alias",        K_ALIAS }
-};
-
-
-/*
- *   FUNCTION DEFINITIONS
- */
-
-static void initialize (const langType language)
-{
-	Lang_vhdl = language;
-}
-
-static void vUngetc (int c)
-{
-	Assert (Ungetc == '\0');
-	Ungetc = c;
-}
-
-static int vGetc (void)
-{
-	int c;
-	if (Ungetc == '\0')
-		c = getcFromInputFile ();
-	else
-	{
-		c = Ungetc;
-		Ungetc = '\0';
-	}
-	if (c == '-')
-	{
-		int c2 = getcFromInputFile ();
-		if (c2 == EOF)
-			longjmp (Exception, (int) ExceptionEOF);
-		else if (c2 == '-')   /* strip comment until end-of-line */
-		{
-			do
-				c = getcFromInputFile ();
-			while (c != '\n'  &&  c != EOF);
-		}
-		else
-			Ungetc = c2;
-	}
-	if (c == EOF)
-		longjmp (Exception, (int) ExceptionEOF);
-	return c;
-}
-
-static bool isIdentifierCharacter (const int c)
-{
-	return (bool)(isalnum (c)  ||  c == '_'  ||  c == '`');
-}
-
-static int skipWhite (int c)
-{
-	while (c==' ')
-		c = vGetc ();
-	return c;
-}
-
-static bool readIdentifier (vString *const name, int c)
-{
-	vStringClear (name);
-	if (isIdentifierCharacter (c))
-	{
-		while (isIdentifierCharacter (c))
-		{
-			vStringPut (name, c);
-			c = vGetc ();
-		}
-		vUngetc (c);
-	}
-	return (bool)(name->length > 0);
-}
-
-static void tagNameList (const vhdlKind kind, int c)
-{
-	Assert (isIdentifierCharacter (c));
-	if (isIdentifierCharacter (c))
-	{
-		readIdentifier (TagName, c);
-		makeSimpleTag (TagName, kind);
-	}
-}
-
-static void findTag (vString *const name)
-{
-	int c = '\0';
-	vhdlKind kind;
-	vStringCopyToLower (Keyword, name);
-	kind = (vhdlKind)lookupKeyword (vStringValue (Keyword), Lang_vhdl);
-	if (kind == K_UNDEFINED)
-	{
-		c = skipWhite (vGetc ());
-		vStringCopyS(Lastname,vStringValue(name));
-		if (c == ':')
-		{
-			c = skipWhite (vGetc ());
-			if (isIdentifierCharacter (c))
-			{
-				readIdentifier (name, c);
-				vStringCopyToLower (Keyword, name);
-				lookupKeyword (vStringValue (Keyword), Lang_vhdl);
-				kind = (vhdlKind)lookupKeyword (vStringValue (Keyword), Lang_vhdl);
-				if (kind == K_PROCESS || kind == K_BLOCK || kind == K_PORT)
-				{
-					makeSimpleTag (Lastname, kind);
-				}
-			}
-		} else {
-			vUngetc (c);
-		}
-	}
-	else
-	{
-		if (kind == K_SIGNAL) {
-			while (c!=':') {
-				c = skipWhite (vGetc ());
-				if (c==',')
-					c = vGetc ();
-				if (isIdentifierCharacter (c))
-					tagNameList (kind, c);
-				else
-					break;
-				c = vGetc ();
-			}
-		}
-		else if (kind == K_PROCESS || kind == K_BLOCK) {
-			vStringCopyS(TagName,"unnamed");
-			makeSimpleTag (TagName, kind);
-		} else {
-			c = skipWhite (vGetc ());
-			if (c=='\"')
-				c = vGetc ();
-			if (isIdentifierCharacter (c))
-				tagNameList (kind, c);
-		}
-	}
-}
-
-static void findVhdlTags (void)
-{
-	volatile bool newStatement = true;
-	volatile int c = '\0';
-	exception_t exception = (exception_t) setjmp (Exception);
-	Name = vStringNew ();
-	Lastname = vStringNew ();
-	Keyword = vStringNew ();
-	TagName = vStringNew ();
-
-	if (exception == ExceptionNone) while (c != EOF)
-	{
-		c = vGetc ();
-		switch (c)
-		{
-			case ';':
-			case '\n':
-				newStatement = true;
-				break;
-
-			case ' ':
-			case '\t':
-				break;
-
-			default:
-				if (newStatement && readIdentifier (Name, c)) {
-					findTag (Name);
-				}
-				newStatement = false;
-				break;
-		}
-	}
-	vStringDelete (Name);
-	vStringDelete (Lastname);
-	vStringDelete (Keyword);
-	vStringDelete (TagName);
-}
-
-extern parserDefinition* VhdlParser (void)
-{
-	static const char *const extensions [] = { "vhdl", "vhd", NULL };
-	parserDefinition* def = parserNew ("Vhdl");
-	def->kindTable  = VhdlKinds;
-	def->kindCount  = ARRAY_SIZE (VhdlKinds);
-	def->extensions = extensions;
-	def->parser     = findVhdlTags;
-	def->initialize = initialize;
-	def->keywordTable = VhdlKeywordTable;
-	def->keywordCount = ARRAY_SIZE (VhdlKeywordTable);
-	return def;
-}
diff --git a/ctags/parsers/vhdl.c b/ctags/parsers/vhdl.c
new file mode 100644
index 0000000000..15f3d5b864
--- /dev/null
+++ b/ctags/parsers/vhdl.c
@@ -0,0 +1,1083 @@
+/*
+*   Copyright (c) 2008, Nicolas Vincent
+*
+*   This source code is released for free distribution under the terms of the
+*   GNU General Public License version 2 or (at your option) any later version.
+*
+*   This module contains functions for generating tags for VHDL files.
+*
+*   References:
+*     https://rti.etf.bg.ac.rs/rti/ri5rvl/tutorial/TUTORIAL/IEEE/HTML/1076_TOC.HTM
+*     https://tams.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html
+*     http://www.vhdl.renerta.com/mobile/index.html
+*     https://www.hdlworks.com/hdl_corner/vhdl_ref/
+*     https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
+*     http://atlas.physics.arizona.edu/~kjohns/downloads/vhdl/VHDL-xilinx-help.pdf
+*     http://www.csit-sun.pub.ro/resources/xilinx/synvhdl.pdf
+*     https://edg.uchicago.edu/~tang/VHDLref.pdf
+*/
+
+/*
+ *   INCLUDE FILES
+ */
+#include "general.h"	/* must always come first */
+
+#include <ctype.h>	/* to define isalpha () */
+#include <string.h>
+
+#include "debug.h"
+#include "entry.h"
+#include "keyword.h"
+#include "parse.h"
+#include "read.h"
+#include "routines.h"
+#include "vstring.h"
+#include "trace.h"
+
+/*
+ *   MACROS
+ */
+#define isType(token,t)     (bool) ((token)->type == (t))
+#define isKeyword(token,k)  (bool) ((token)->keyword == (k))
+#define isIdentChar1(c) (isalpha (c) || (c) == '_')
+#define isIdentChar(c) (isalpha (c) || isdigit (c) || (c) == '_')
+
+/*
+ *   DATA DECLARATIONS
+ */
+
+/*
+ * Used to specify type of keyword.
+ */
+enum eKeywordId {
+	KEYWORD_ABS,
+	KEYWORD_ACCESS,
+	KEYWORD_AFTER,
+	KEYWORD_ALIAS,
+	KEYWORD_ALL,
+	KEYWORD_AND,
+	KEYWORD_ARCHITECTURE,
+	KEYWORD_ARRAY,
+	KEYWORD_ASSERT,
+	KEYWORD_ATTRIBUTE,
+	KEYWORD_BEGIN,
+	KEYWORD_BLOCK,
+	KEYWORD_BODY,
+	KEYWORD_BUFFER,
+	KEYWORD_BUS,
+	KEYWORD_CASE,
+	KEYWORD_COMPONENT,
+	KEYWORD_CONFIGURATION,
+	KEYWORD_CONSTANT,
+	KEYWORD_DISCONNECT,
+	KEYWORD_DOWNTO,
+	KEYWORD_ELSE,
+	KEYWORD_ELSIF,
+	KEYWORD_END,
+	KEYWORD_ENTITY,
+	KEYWORD_EXIT,
+	KEYWORD_FILE,
+	KEYWORD_FOR,
+	KEYWORD_FUNCTION,
+	KEYWORD_GENERATE,
+	KEYWORD_GENERIC,
+	KEYWORD_GROUP,
+	KEYWORD_GUARDED,
+	KEYWORD_IF,
+	KEYWORD_IMPURE,
+	KEYWORD_IN,
+	KEYWORD_INERTIAL,
+	KEYWORD_INOUT,
+	KEYWORD_IS,
+	KEYWORD_LABEL,
+	KEYWORD_LIBRARY,
+	KEYWORD_LINKAGE,
+	KEYWORD_LITERAL,
+	KEYWORD_LOOP,
+	KEYWORD_MAP,
+	KEYWORD_MOD,
+	KEYWORD_NAND,
+	KEYWORD_NEW,
+	KEYWORD_NEXT,
+	KEYWORD_NOR,
+	KEYWORD_NOT,
+	KEYWORD_NULL,
+	KEYWORD_OF,
+	KEYWORD_ON,
+	KEYWORD_OPEN,
+	KEYWORD_OR,
+	KEYWORD_OTHERS,
+	KEYWORD_OUT,
+	KEYWORD_PACKAGE,
+	KEYWORD_PORT,
+	KEYWORD_POSTPONED,
+	KEYWORD_PROCEDURE,
+	KEYWORD_PROCESS,
+	KEYWORD_PURE,
+	KEYWORD_RANGE,
+	KEYWORD_RECORD,
+	KEYWORD_REGISTER,
+	KEYWORD_REJECT,
+	KEYWORD_RETURN,
+	KEYWORD_ROL,
+	KEYWORD_ROR,
+	KEYWORD_SELECT,
+	KEYWORD_SEVERITY,
+	KEYWORD_SIGNAL,
+	KEYWORD_SHARED,
+	KEYWORD_SLA,
+	KEYWORD_SLI,
+	KEYWORD_SRA,
+	KEYWORD_SRL,
+	KEYWORD_SUBTYPE,
+	KEYWORD_THEN,
+	KEYWORD_TO,
+	KEYWORD_TRANSPORT,
+	KEYWORD_TYPE,
+	KEYWORD_UNAFFECTED,
+	KEYWORD_UNITS,
+	KEYWORD_UNTIL,
+	KEYWORD_USE,
+	KEYWORD_VARIABLE,
+	KEYWORD_WAIT,
+	KEYWORD_WHEN,
+	KEYWORD_WHILE,
+	KEYWORD_WITH,
+	KEYWORD_XNOR,
+	KEYWORD_XOR
+};
+typedef int keywordId; /* to allow KEYWORD_NONE */
+
+typedef enum eTokenType {
+	TOKEN_NONE,		/* none */
+	TOKEN_EOF,		/* end-of-file */
+	TOKEN_OPEN_PAREN,	/* ( */
+	TOKEN_CLOSE_PAREN,	/* ) */
+	TOKEN_COMMA,		/* the comma character */
+	TOKEN_IDENTIFIER,
+	TOKEN_KEYWORD,
+	TOKEN_PERIOD,		/* . */
+	TOKEN_OPERATOR,
+	TOKEN_SEMICOLON,	/* the semicolon character */
+	TOKEN_COLON,		/* : */
+	TOKEN_STRING
+} tokenType;
+
+typedef struct sTokenInfo {
+	tokenType type;
+	keywordId keyword;
+	vString *string;		/* the name of the token */
+	unsigned long lineNumber;	/* line number of tag */
+	MIOPos filePosition;		/* file position of line containing name */
+} tokenInfo;
+
+/*
+ *   DATA DEFINITIONS
+ */
+static int Lang_vhdl;
+
+typedef enum {
+	VHDL_ENTITY_DESIGNED,
+} vhdlEntityRole;
+
+static roleDefinition VhdlEntityRoles [] = {
+	{ true, "desigend",
+	  "designed by an architecture" },
+};
+
+/* Used to index into the VhdlKinds table. */
+typedef enum {
+	VHDLTAG_UNDEFINED = -1,
+	VHDLTAG_CONSTANT,
+	VHDLTAG_TYPE,
+	VHDLTAG_SUBTYPE,
+	VHDLTAG_RECORD,
+	VHDLTAG_ENTITY,
+	VHDLTAG_COMPONENT,
+	VHDLTAG_PROTOTYPE,
+	VHDLTAG_FUNCTION,
+	VHDLTAG_PROCEDURE,
+	VHDLTAG_PACKAGE,
+	VHDLTAG_LOCAL,
+	VHDLTAG_ARCHITECTURE,
+	VHDLTAG_PORT,
+	VHDLTAG_GENERIC,
+	VHDLTAG_SIGNAL,
+	VHDLTAG_PROCESS,
+	VHDLTAG_VARIABLE,
+	VHDLTAG_ALIAS,
+} vhdlKind;
+
+static kindDefinition VhdlKinds[] = {
+	{true, 'c', "constant", "constant declarations"},
+	{true, 't', "type", "type definitions"},
+	{true, 'T', "subtype", "subtype definitions"},
+	{true, 'r', "record", "record names"},
+	{true, 'e', "entity", "entity declarations",
+	 .referenceOnly = false, ATTACH_ROLES(VhdlEntityRoles)},
+	{false, 'C', "component", "component declarations"},
+	{false, 'd', "prototype", "prototypes"},
+	{true, 'f', "function", "function prototypes and declarations"},
+	{true, 'p', "procedure", "procedure prototypes and declarations"},
+	{true, 'P', "package", "package definitions"},
+	{false, 'l', "local", "local definitions"},
+	{true, 'a', "architecture", "architectures"},
+	{true, 'q', "port", "port declarations"},
+	{true, 'g', "generic", "generic declarations"},
+	{true , 's', "signal", "signal declarations"},
+	{true, 'Q',  "process", "processes"},
+	{true, 'v',  "variable", "variables"},
+	{true, 'A',  "alias", "aliases"},
+};
+
+static const keywordTable VhdlKeywordTable[] = {
+	{"abs", KEYWORD_ABS},
+	{"access", KEYWORD_ACCESS},
+	{"after", KEYWORD_AFTER},
+	{"alias", KEYWORD_ALIAS},
+	{"all", KEYWORD_ALL},
+	{"and", KEYWORD_AND},
+	{"architecture", KEYWORD_ARCHITECTURE},
+	{"array", KEYWORD_ARRAY},
+	{"assert", KEYWORD_ASSERT},
+	{"attribute", KEYWORD_ATTRIBUTE},
+	{"begin", KEYWORD_BEGIN},
+	{"block", KEYWORD_BLOCK},
+	{"body", KEYWORD_BODY},
+	{"buffer", KEYWORD_BUFFER},
+	{"bus", KEYWORD_BUS},
+	{"case", KEYWORD_CASE},
+	{"component", KEYWORD_COMPONENT},
+	{"configuration", KEYWORD_CONFIGURATION},
+	{"constant", KEYWORD_CONSTANT},
+	{"disconnect", KEYWORD_DISCONNECT},
+	{"downto", KEYWORD_DOWNTO},
+	{"else", KEYWORD_ELSE},
+	{"elsif", KEYWORD_ELSIF},
+	{"end", KEYWORD_END},
+	{"entity", KEYWORD_ENTITY},
+	{"exit", KEYWORD_EXIT},
+	{"file", KEYWORD_FILE},
+	{"for", KEYWORD_FOR},
+	{"function", KEYWORD_FUNCTION},
+	{"generate", KEYWORD_GENERATE},
+	{"generic", KEYWORD_GENERIC},
+	{"group", KEYWORD_GROUP},
+	{"guarded", KEYWORD_GUARDED},
+	{"if", KEYWORD_IF},
+	{"impure", KEYWORD_IMPURE},
+	{"in", KEYWORD_IN},
+	{"inertial", KEYWORD_INERTIAL},
+	{"inout", KEYWORD_INOUT},
+	{"is", KEYWORD_IS},
+	{"label", KEYWORD_LABEL},
+	{"library", KEYWORD_LIBRARY},
+	{"linkage", KEYWORD_LINKAGE},
+	{"literal", KEYWORD_LITERAL},
+	{"loop", KEYWORD_LOOP},
+	{"map", KEYWORD_MAP},
+	{"mod", KEYWORD_MOD},
+	{"nand", KEYWORD_NAND},
+	{"new", KEYWORD_NEW},
+	{"next", KEYWORD_NEXT},
+	{"nor", KEYWORD_NOR},
+	{"not", KEYWORD_NOT},
+	{"null", KEYWORD_NULL},
+	{"of", KEYWORD_OF},
+	{"on", KEYWORD_ON},
+	{"open", KEYWORD_OPEN},
+	{"or", KEYWORD_OR},
+	{"others", KEYWORD_OTHERS},
+	{"out", KEYWORD_OUT},
+	{"package", KEYWORD_PACKAGE},
+	{"port", KEYWORD_PORT},
+	{"postponed", KEYWORD_POSTPONED},
+	{"procedure", KEYWORD_PROCEDURE},
+	{"process", KEYWORD_PROCESS},
+	{"pure", KEYWORD_PURE},
+	{"range", KEYWORD_RANGE},
+	{"record", KEYWORD_RECORD},
+	{"register", KEYWORD_REGISTER},
+	{"reject", KEYWORD_REJECT},
+	{"return", KEYWORD_RETURN},
+	{"rol", KEYWORD_ROL},
+	{"ror", KEYWORD_ROR},
+	{"select", KEYWORD_SELECT},
+	{"severity", KEYWORD_SEVERITY},
+	{"signal", KEYWORD_SIGNAL},
+	{"shared", KEYWORD_SHARED},
+	{"sla", KEYWORD_SLA},
+	{"sli", KEYWORD_SLI},
+	{"sra", KEYWORD_SRA},
+	{"srl", KEYWORD_SRL},
+	{"subtype", KEYWORD_SUBTYPE},
+	{"then", KEYWORD_THEN},
+	{"to", KEYWORD_TO},
+	{"transport", KEYWORD_TRANSPORT},
+	{"type", KEYWORD_TYPE},
+	{"unaffected", KEYWORD_UNAFFECTED},
+	{"units", KEYWORD_UNITS},
+	{"until", KEYWORD_UNTIL},
+	{"use", KEYWORD_USE},
+	{"variable", KEYWORD_VARIABLE},
+	{"wait", KEYWORD_WAIT},
+	{"when", KEYWORD_WHEN},
+	{"while", KEYWORD_WHILE},
+	{"with", KEYWORD_WITH},
+	{"xnor", KEYWORD_XNOR},
+	{"xor", KEYWORD_XOR}
+};
+
+typedef enum {
+	F_ARCHITECTURE,
+} vhdlField;
+
+static fieldDefinition VhdlFields [] = {
+	{ .name = "architecture",
+	  .description = "architecture designing the entity",
+	  .enabled = true },
+};
+
+/*
+ *   FUNCTION DECLARATIONS
+ */
+static void parseKeywords (tokenInfo * const token, tokenInfo * const label, int parent);
+
+/*
+ *   FUNCTION DEFINITIONS
+ */
+static bool isIdentifierMatch (const tokenInfo * const token,
+	const char *name)
+{
+	return (bool) (isType (token, TOKEN_IDENTIFIER) &&
+		strncasecmp (vStringValue (token->string), name,
+					 vStringLength (token->string)) == 0);
+}
+
+static bool isSemicolonOrKeywordOrIdent (const tokenInfo * const token,
+	const keywordId keyword, const char *name)
+{
+	return (bool) (isType (token, TOKEN_SEMICOLON)
+				   || isKeyword (token, keyword)
+				   || isIdentifierMatch (token, name));
+}
+
+static tokenInfo *newToken (void)
+{
+	tokenInfo *const token = xMalloc (1, tokenInfo);
+	token->type = TOKEN_NONE;
+	token->keyword = KEYWORD_NONE;
+	token->string = vStringNew ();
+	token->lineNumber = getInputLineNumber ();
+	token->filePosition = getInputFilePosition ();
+	return token;
+}
+
+static tokenInfo *copyToken (tokenInfo * const src)
+{
+	tokenInfo *dst = newToken ();
+	vStringCopy (dst->string, src->string);
+	return dst;
+}
+
+static void deleteToken (tokenInfo * const token)
+{
+	if (token != NULL)
+	{
+		vStringDelete (token->string);
+		eFree (token);
+	}
+}
+
+/*
+ *   Parsing functions
+ */
+
+static void parseString (vString * const string, const int delimiter)
+{
+	bool end = false;
+	while (!end)
+	{
+		int c = getcFromInputFile ();
+		if (c == EOF)
+			end = true;
+		else if (c == '\\')
+		{
+			c = getcFromInputFile ();	/* This maybe a ' or ". */
+			vStringPut (string, c);
+		}
+		else if (c == delimiter)
+			end = true;
+		else
+			vStringPut (string, c);
+	}
+}
+
+/*  Read a VHDL identifier beginning with "firstChar" and place it into "name".
+*/
+static void parseIdentifier (vString * const string, const int firstChar)
+{
+	int c = firstChar;
+	Assert (isIdentChar1 (c));
+	do
+	{
+		vStringPut (string, c);
+		c = getcFromInputFile ();
+	} while (isIdentChar (c));
+	if (!isspace (c))
+		ungetcToInputFile (c);	/* unget non-identifier character */
+}
+
+static void readToken (tokenInfo * const token)
+{
+	int c;
+
+	token->type = TOKEN_NONE;
+	token->keyword = KEYWORD_NONE;
+	vStringClear (token->string);
+
+  getNextChar:
+	do
+	{
+		c = getcFromInputFile ();
+		token->lineNumber = getInputLineNumber ();
+		token->filePosition = getInputFilePosition ();
+	}
+	while (c == '\t' || c == ' ' || c == '\n');
+
+	switch (c)
+	{
+	case EOF:
+		token->type = TOKEN_EOF;
+		break;
+	case '(':
+		token->type = TOKEN_OPEN_PAREN;
+		break;
+	case ')':
+		token->type = TOKEN_CLOSE_PAREN;
+		break;
+	case ';':
+		token->type = TOKEN_SEMICOLON;
+		break;
+	case ':':
+		token->type = TOKEN_COLON;
+		break;
+	case '.':
+		token->type = TOKEN_PERIOD;
+		break;
+	case ',':
+		token->type = TOKEN_COMMA;
+		break;
+	case '\'':	/* only single char are inside simple quotes */
+		break;	/* or it is for attributes so we don't care */
+	case '"':
+		token->type = TOKEN_STRING;
+		parseString (token->string, c);
+		token->lineNumber = getInputLineNumber ();
+		token->filePosition = getInputFilePosition ();
+		break;
+	case '-':
+		c = getcFromInputFile ();
+		if (c == '-')	/* start of a comment */
+		{
+			skipToCharacterInInputFile ('\n');
+			goto getNextChar;
+		}
+		else
+		{
+			if (!isspace (c))
+				ungetcToInputFile (c);
+			token->type = TOKEN_OPERATOR;
+		}
+		break;
+	default:
+		if (!isIdentChar1 (c))
+			token->type = TOKEN_NONE;
+		else
+		{
+			parseIdentifier (token->string, c);
+			token->lineNumber = getInputLineNumber ();
+			token->filePosition = getInputFilePosition ();
+			token->keyword = lookupCaseKeyword (vStringValue (token->string), Lang_vhdl);
+			if (isKeyword (token, KEYWORD_NONE))
+				token->type = TOKEN_IDENTIFIER;
+			else
+				token->type = TOKEN_KEYWORD;
+		}
+		break;
+	}
+}
+
+static bool skipToKeyword (const keywordId keyword)
+{
+	tokenInfo *const token = newToken ();
+	do
+	{
+		readToken (token);
+	}
+	while (!isType (token, TOKEN_EOF) && !isKeyword (token, keyword));
+
+	bool r = isKeyword (token, keyword);
+	deleteToken (token);
+	return r;
+}
+
+static void skipToMatched (tokenInfo * const token)
+{
+	int nest_level = 0;
+	tokenType open_token;
+	tokenType close_token;
+
+	switch (token->type)
+	{
+	case TOKEN_OPEN_PAREN:
+		open_token = TOKEN_OPEN_PAREN;
+		close_token = TOKEN_CLOSE_PAREN;
+		break;
+	default:
+		return;
+	}
+
+	/*
+	 * This routine will skip to a matching closing token.
+	 * It will also handle nested tokens like the (, ) below.
+	 *   (  name varchar(30), text binary(10)  )
+	 */
+	if (isType (token, open_token))
+	{
+		nest_level++;
+		while (!(isType (token, close_token) && (nest_level == 0)) && !isType (token, TOKEN_EOF))
+		{
+			readToken (token);
+			if (isType (token, open_token))
+			{
+				nest_level++;
+			}
+			if (isType (token, close_token))
+			{
+				if (nest_level > 0)
+				{
+					nest_level--;
+				}
+			}
+		}
+		readToken (token);
+	}
+}
+
+static int makeVhdlTagWithScope (tokenInfo * const token, const vhdlKind kind, int parent)
+{
+	const char *const name = vStringValue (token->string);
+	tagEntryInfo e;
+	initTagEntry (&e, name, kind);
+	e.lineNumber = token->lineNumber;
+	e.filePosition = token->filePosition;
+	e.extensionFields.scopeIndex = parent;
+	return makeTagEntry (&e);
+}
+
+static int makeVhdlTag (tokenInfo * const token, const vhdlKind kind)
+{
+	return makeVhdlTagWithScope (token, kind, CORK_NIL);
+}
+
+static void initialize (const langType language)
+{
+	Lang_vhdl = language;
+}
+
+static void parseTillEnd (tokenInfo * const token, int parent, const int end_keyword)
+{
+	bool ended = false;
+	tagEntryInfo *e = getEntryInCorkQueue (parent);
+	/* If e is NULL, the input may be broken as VHDL code
+	 * or unsupported syntax in this parser. */
+
+	do
+	{
+		readToken (token);
+		if (isKeyword (token, KEYWORD_END))
+		{
+			readToken (token);
+			if (e)
+				ended = isSemicolonOrKeywordOrIdent (token,
+													 end_keyword, e->name);
+			if (!isType (token, TOKEN_SEMICOLON))
+				skipToCharacterInInputFile (';');
+			if (ended)
+				e->extensionFields.endLine = getInputLineNumber ();
+		}
+		else
+		{
+			if (isType (token, TOKEN_EOF))
+			{
+				ended = true;
+			}
+			else
+			{
+				parseKeywords (token, NULL, parent);
+			}
+		}
+	} while (!ended);
+}
+
+static void parseTillBegin (tokenInfo * const token, int parent)
+{
+	bool begun = false;
+	do
+	{
+		readToken (token);
+		if (isKeyword (token, KEYWORD_BEGIN)
+			|| isType (token, TOKEN_EOF))
+			begun = true;
+		else
+			parseKeywords (token, NULL, parent);
+	} while (!begun);
+}
+
+static void parsePackage (tokenInfo * const token)
+{
+	tokenInfo *const name = newToken ();
+	tokenInfo *token_for_tagging = NULL;
+	Assert (isKeyword (token, KEYWORD_PACKAGE));
+	readToken (token);
+	if (isKeyword (token, KEYWORD_BODY))
+	{
+		readToken (name);
+		token_for_tagging = name;
+	}
+	else if (isType (token, TOKEN_IDENTIFIER))
+		token_for_tagging = token;
+
+	if (token_for_tagging)
+	{
+		int index = makeVhdlTag (token_for_tagging, VHDLTAG_PACKAGE);
+		parseTillEnd (token, index, KEYWORD_PACKAGE);
+	}
+
+	deleteToken (name);
+}
+
+
+static void parseDeclElement (tokenInfo * const token,
+							  vhdlKind kind, int parent,
+							  bool ended_with_semicolon)
+{
+	TRACE_ENTER ();
+	while (! (isType (token, TOKEN_EOF)
+			  || isType (token, TOKEN_CLOSE_PAREN)
+			  || (ended_with_semicolon && isType (token, TOKEN_SEMICOLON))))
+	{
+		if (isType (token, TOKEN_IDENTIFIER))
+		{
+			makeVhdlTagWithScope (token, kind, parent);
+			readToken (token);
+		}
+		else if (isType (token, TOKEN_COMMA))
+			readToken (token);
+		else if (isType (token, TOKEN_COLON))
+		{
+			do
+			{
+				readToken (token);
+				skipToMatched (token);
+				if (isType (token, TOKEN_CLOSE_PAREN)
+					|| isType (token, TOKEN_SEMICOLON))
+					break;
+			}
+			while (!isType (token, TOKEN_EOF));
+		}
+		else
+		{
+			/* Unexpected */
+			readToken (token);
+		}
+	}
+	TRACE_LEAVE ();
+}
+
+static void parseModuleDecl (tokenInfo * const token, int parent)
+{
+	TRACE_ENTER ();
+	while (! (isKeyword (token, KEYWORD_END)
+			  || isType (token, TOKEN_EOF)))
+	{
+		vhdlKind kind = VHDLTAG_UNDEFINED;
+		if (isKeyword (token, KEYWORD_PORT))
+			kind = VHDLTAG_PORT;
+		else if (isKeyword (token, KEYWORD_GENERIC))
+			kind = VHDLTAG_GENERIC;
+
+		if (kind != VHDLTAG_UNDEFINED)
+		{
+			readToken (token);
+			if (isType (token, TOKEN_OPEN_PAREN))
+			{
+				readToken (token);
+				parseDeclElement (token, kind, parent, false);
+			}
+		}
+		else
+			readToken (token);
+	}
+	TRACE_LEAVE ();
+}
+
+static void parseModule (tokenInfo * const token, int parent)
+{
+	tokenInfo *const name = newToken ();
+	const vhdlKind kind = isKeyword (token, KEYWORD_ENTITY) ?
+		VHDLTAG_ENTITY : VHDLTAG_COMPONENT;
+	Assert (isKeyword (token, KEYWORD_ENTITY) ||
+		isKeyword (token, KEYWORD_COMPONENT));
+	readToken (name);
+	readToken (token);
+	if (kind == VHDLTAG_COMPONENT || isKeyword (token, KEYWORD_IS))
+	{
+		int index = makeVhdlTagWithScope (name, kind, parent);
+		if (isKeyword (token, KEYWORD_IS))
+			readToken (token);
+		parseModuleDecl (token, index);
+
+		bool ended = isKeyword (token, KEYWORD_END);
+		if (!ended)
+			ended = skipToKeyword (KEYWORD_END);
+		skipToCharacterInInputFile (';');
+
+		if (ended)
+		{
+			tagEntryInfo *e = getEntryInCorkQueue (index);
+			if (e)
+				e->extensionFields.endLine = getInputLineNumber ();
+		}
+
+		if (kind == VHDLTAG_ENTITY)
+			registerEntry (index);
+	}
+	deleteToken (name);
+}
+
+static void parseRecord (tokenInfo * const token, int parent)
+{
+	tokenInfo *const name = newToken ();
+	Assert (isKeyword (token, KEYWORD_RECORD));
+	readToken (name);
+	do
+	{
+		readToken (token);	/* should be a colon */
+		skipToCharacterInInputFile (';');
+		makeVhdlTagWithScope (name, VHDLTAG_RECORD, parent);
+		readToken (name);
+	}
+	while (!isKeyword (name, KEYWORD_END) && !isType (name, TOKEN_EOF));
+	skipToCharacterInInputFile (';');
+
+	if (isKeyword (name, KEYWORD_END))
+	{
+		tagEntryInfo *e = getEntryInCorkQueue (parent);
+		if (e)
+			e->extensionFields.endLine = getInputLineNumber ();
+	}
+
+	deleteToken (name);
+}
+
+static void parseTypes (tokenInfo * const token, int parent)
+{
+	tokenInfo *const name = newToken ();
+	const vhdlKind kind = isKeyword (token, KEYWORD_TYPE) ?
+		VHDLTAG_TYPE : VHDLTAG_SUBTYPE;
+	Assert (isKeyword (token, KEYWORD_TYPE) ||
+		isKeyword (token, KEYWORD_SUBTYPE));
+	readToken (name);
+	readToken (token);
+	if (isKeyword (token, KEYWORD_IS))
+	{
+		readToken (token);	/* type */
+		if (isKeyword (token, KEYWORD_RECORD))
+		{
+			int index = makeVhdlTagWithScope (name, kind, parent);
+			/*TODO: make tags of the record's names */
+			parseRecord (token, index);
+		}
+		else
+		{
+			makeVhdlTagWithScope (name, kind, parent);
+		}
+	}
+	deleteToken (name);
+}
+
+static void parseConstant (int parent)
+{
+	vhdlKind parent_kind = VHDLTAG_UNDEFINED;
+	tagEntryInfo *e = getEntryInCorkQueue (parent);
+	if (e)
+		parent_kind = e->kindIndex;
+
+	vhdlKind kind;
+	switch (parent_kind)
+	{
+	case VHDLTAG_FUNCTION:
+	case VHDLTAG_PROCEDURE:
+		kind = VHDLTAG_LOCAL;
+		break;
+	default:
+		kind = VHDLTAG_CONSTANT;
+		break;
+	}
+
+	tokenInfo *const name = newToken ();
+	readToken (name);
+	makeVhdlTagWithScope (name, kind, parent);
+	skipToCharacterInInputFile (';');
+	deleteToken (name);
+}
+
+static void parseSubProgram (tokenInfo * const token, int parent)
+{
+	tokenInfo *const name = newToken ();
+	const vhdlKind kind = isKeyword (token, KEYWORD_FUNCTION) ?
+		VHDLTAG_FUNCTION : VHDLTAG_PROCEDURE;
+	const int end_keyword = token->keyword;
+	Assert (isKeyword (token, KEYWORD_FUNCTION) ||
+		isKeyword (token, KEYWORD_PROCEDURE));
+	readToken (name);	/* the name of the function or procedure */
+	readToken (token);
+	if (isType (token, TOKEN_OPEN_PAREN))
+	{
+		skipToMatched (token);
+	}
+
+	if (kind == VHDLTAG_FUNCTION)
+	{
+		if (isKeyword (token, KEYWORD_RETURN))
+		{
+			/* Read datatype */
+			readToken (token);
+			while (! isKeyword (token, KEYWORD_IS) &&
+					! isType (token, TOKEN_SEMICOLON) &&
+					! isType (token, TOKEN_EOF))
+			{
+				readToken (token);
+			}
+		}
+	}
+
+	if (isType (token, TOKEN_SEMICOLON))
+	{
+		makeVhdlTagWithScope (name, VHDLTAG_PROTOTYPE, parent);
+	}
+	else if (isKeyword (token, KEYWORD_IS))
+	{
+		int index = makeVhdlTagWithScope (name, kind, parent);
+		parseTillEnd (token, index, end_keyword);
+	}
+	deleteToken (name);
+}
+
+/*  architecture behavioral of ent is*/
+static void parseArchitecture (tokenInfo * const token)
+{
+	tokenInfo *const name = newToken ();
+
+	readToken (name);
+	if (!isType (name, TOKEN_IDENTIFIER))
+	{
+		skipToKeyword (KEYWORD_END);
+		skipToCharacterInInputFile (';');
+		deleteToken (name);
+		return;
+	}
+
+	int index = makeVhdlTag (name, VHDLTAG_ARCHITECTURE);
+	readToken (token);
+	if (isKeyword (token, KEYWORD_OF))
+	{
+		readToken (token);
+		if (isType (token, TOKEN_IDENTIFIER))
+		{
+			/* Filling scope field of this architecture.
+			   If the definition for the entity can be found in the symbol table,
+			   use its cork as the scope. If not, use the reference tag for the
+			   entity as fallback. */
+			int role_index = makeSimpleRefTag (token->string,
+											   VHDLTAG_ENTITY, VHDL_ENTITY_DESIGNED);
+			int entity_index = anyKindEntryInScope (CORK_NIL,
+													vStringValue (token->string),
+													VHDLTAG_ENTITY);
+			tagEntryInfo *e = getEntryInCorkQueue (index);
+			if (e)
+			{
+				e->extensionFields.scopeIndex = (
+					entity_index == CORK_NIL
+					? role_index
+					: entity_index);
+
+				/* TODO: append thes architecture name to
+				 * architecture: field of *e*. */
+			}
+
+			attachParserFieldToCorkEntry (role_index,
+										  VhdlFields[F_ARCHITECTURE].ftype,
+										  vStringValue (name->string));
+
+			readToken (token);
+			if (isKeyword (token, KEYWORD_IS))
+			{
+				parseTillBegin (token, index);
+				parseTillEnd (token, index, KEYWORD_ARCHITECTURE);
+			}
+		}
+	}
+	deleteToken (name);
+}
+
+static void parseSignal (tokenInfo * const token, int parent)
+{
+	readToken (token);
+	parseDeclElement (token, VHDLTAG_SIGNAL, parent, true);
+}
+
+static void parseLabel (tokenInfo * const name, int parent)
+{
+	tokenInfo *const token = newToken ();
+
+	readToken (token);
+	if (isType (token, TOKEN_COLON))
+	{
+		readToken (token);
+		if (isType (token, TOKEN_KEYWORD))
+			parseKeywords (token, name, parent);
+	}
+	deleteToken (token);
+}
+
+static void parseProcess (tokenInfo * const token, tokenInfo * const label, int parent)
+{
+	tokenInfo *process = label? label: copyToken (token);
+
+	if (label == NULL)
+	{
+		process->type = TOKEN_IDENTIFIER;
+		vStringClear (process->string);
+		anonGenerate (process->string, "anonProcess", VHDLTAG_PROCESS);
+	}
+
+	int index = makeVhdlTagWithScope (process, VHDLTAG_PROCESS, parent);
+
+	if (label == NULL)
+	{
+		tagEntryInfo *e = getEntryInCorkQueue (index);
+		if (e)
+			markTagExtraBit (e, XTAG_ANONYMOUS);
+		deleteToken (process);
+	}
+
+	skipToMatched (token);
+	parseTillBegin (token, index);
+	parseTillEnd (token, index, KEYWORD_PROCESS);
+}
+
+static void parseVariable (tokenInfo * const token, int parent)
+{
+	readToken (token);
+	parseDeclElement (token, VHDLTAG_VARIABLE, parent, true);
+}
+
+static void parseAlias (tokenInfo * const token, int parent)
+{
+	readToken (token);
+	parseDeclElement (token, VHDLTAG_ALIAS, parent, true);
+}
+
+/* TODO */
+/* records */
+static void parseKeywords (tokenInfo * const token, tokenInfo * const label, int index)
+{
+	switch (token->keyword)
+	{
+	case KEYWORD_END:
+		skipToCharacterInInputFile (';');
+		break;
+	case KEYWORD_CONSTANT:
+		parseConstant (index);
+		break;
+	case KEYWORD_TYPE:
+		parseTypes (token, index);
+		break;
+	case KEYWORD_SUBTYPE:
+		parseTypes (token, index);
+		break;
+	case KEYWORD_ENTITY:
+		parseModule (token, index);
+		break;
+	case KEYWORD_COMPONENT:
+		parseModule (token, index);
+		break;
+	case KEYWORD_FUNCTION:
+		parseSubProgram (token, index);
+		break;
+	case KEYWORD_PROCEDURE:
+		parseSubProgram (token, index);
+		break;
+	case KEYWORD_PACKAGE:
+		parsePackage (token);
+		break;
+	case KEYWORD_ARCHITECTURE:
+		parseArchitecture (token);
+		break;
+	case KEYWORD_SIGNAL:
+		parseSignal (token, index);
+		break;
+	case KEYWORD_PROCESS:
+		parseProcess (token, label, index);
+		break;
+	case KEYWORD_VARIABLE:
+		parseVariable (token, index);
+		break;
+	case KEYWORD_ALIAS:
+		parseAlias (token, index);
+		break;
+	default:
+		if (isType (token, TOKEN_IDENTIFIER))
+			parseLabel (token, index);
+		break;
+	}
+}
+
+static tokenType parseVhdlFile (tokenInfo * const token)
+{
+	do
+	{
+		readToken (token);
+		parseKeywords (token, NULL, CORK_NIL);
+	} while (!isKeyword (token, KEYWORD_END) && !isType (token, TOKEN_EOF));
+	return token->type;
+}
+
+static void findVhdlTags (void)
+{
+	tokenInfo *const token = newToken ();
+
+	while (parseVhdlFile (token) != TOKEN_EOF);
+
+	deleteToken (token);
+}
+
+extern parserDefinition *VhdlParser (void)
+{
+	static const char *const extensions[] = { "vhdl", "vhd", NULL };
+	parserDefinition *def = parserNew ("VHDL");
+	def->kindTable = VhdlKinds;
+	def->kindCount = ARRAY_SIZE (VhdlKinds);
+	def->extensions = extensions;
+	def->parser = findVhdlTags;
+	def->initialize = initialize;
+	def->keywordTable = VhdlKeywordTable;
+	def->keywordCount = ARRAY_SIZE (VhdlKeywordTable);
+	def->fieldTable = VhdlFields;
+	def->fieldCount = ARRAY_SIZE (VhdlFields);
+	def->useCork = CORK_QUEUE|CORK_SYMTAB;
+	return def;
+}
diff --git a/meson.build b/meson.build
index bbbaa7b33c..829a212db0 100644
--- a/meson.build
+++ b/meson.build
@@ -640,7 +640,6 @@ ctags = static_library('ctags',
 	'ctags/parsers/geany_matlab.c',
 	'ctags/parsers/geany_tcl.c',
 	'ctags/parsers/geany_tex.c',
-	'ctags/parsers/geany_vhdl.c',
 	'ctags/parsers/go.c',
 	'ctags/parsers/haskell.c',
 	'ctags/parsers/haxe.c',
@@ -670,6 +669,7 @@ ctags = static_library('ctags',
 	'ctags/parsers/sql.c',
 	'ctags/parsers/txt2tags.c',
 	'ctags/parsers/verilog.c',
+	'ctags/parsers/vhdl.c',
 	c_args: geany_cflags + [ '-DG_LOG_DOMAIN="CTags"',
 	                         '-DEXTERNAL_PARSER_LIST_FILE="src/tagmanager/tm_parsers.h"' ],
 	dependencies: deps + [dep_fnmatch, dep_regex],
diff --git a/src/tagmanager/tm_parser.c b/src/tagmanager/tm_parser.c
index a305674e2d..4eb3bfb11c 100644
--- a/src/tagmanager/tm_parser.c
+++ b/src/tagmanager/tm_parser.c
@@ -432,21 +432,24 @@ static TMParserMapGroup group_DIFF[] = {
 };
 
 static TMParserMapEntry map_VHDL[] = {
-	{'c', tm_tag_variable_t},
-	{'t', tm_tag_typedef_t},
-	{'v', tm_tag_variable_t},
-	{'a', tm_tag_undef_t},
-	{'s', tm_tag_variable_t},
-	{'f', tm_tag_function_t},
-	{'p', tm_tag_function_t},
-	{'k', tm_tag_member_t},
-	{'l', tm_tag_namespace_t},
-	{'m', tm_tag_member_t},
-	{'n', tm_tag_class_t},
-	{'o', tm_tag_struct_t},
-	{'u', tm_tag_undef_t},
-	{'b', tm_tag_member_t},
-	{'A', tm_tag_typedef_t},
+	{'c', tm_tag_variable_t},   // constant
+	{'t', tm_tag_typedef_t},    // type
+	{'T', tm_tag_typedef_t},    // subtype
+	{'r', tm_tag_undef_t},      // record
+	{'e', tm_tag_class_t},      // entity
+	{'C', tm_tag_member_t},     // component
+	{'d', tm_tag_undef_t},      // prototype
+	{'f', tm_tag_function_t},   // function
+	{'p', tm_tag_function_t},   // procedure
+	{'P', tm_tag_namespace_t},  // package
+	{'l', tm_tag_variable_t},   // local
+	{'a', tm_tag_struct_t},     // architecture
+	{'q', tm_tag_variable_t},   // port
+	{'g', tm_tag_undef_t},      // generic
+	{'s', tm_tag_variable_t},   // signal
+	{'Q', tm_tag_member_t},     // process
+	{'v', tm_tag_variable_t},   // variable
+	{'A', tm_tag_typedef_t},    // alias
 };
 static TMParserMapGroup group_VHDL[] = {
 	{_("Package"), TM_ICON_NAMESPACE, tm_tag_namespace_t},
@@ -454,7 +457,7 @@ static TMParserMapGroup group_VHDL[] = {
 	{_("Architectures"), TM_ICON_STRUCT, tm_tag_struct_t},
 	{_("Types"), TM_ICON_OTHER, tm_tag_typedef_t},
 	{_("Functions / Procedures"), TM_ICON_METHOD, tm_tag_function_t},
-	{_("Variables / Signals"), TM_ICON_VAR, tm_tag_variable_t},
+	{_("Variables / Signals / Ports"), TM_ICON_VAR, tm_tag_variable_t},
 	{_("Processes / Blocks / Components"), TM_ICON_MEMBER, tm_tag_member_t},
 };
 
@@ -1494,6 +1497,7 @@ gboolean tm_parser_has_full_scope(TMParserType lang)
 		case TM_PARSER_SQL:
 		case TM_PARSER_TXT2TAGS:
 		case TM_PARSER_VALA:
+		case TM_PARSER_VHDL:
 		case TM_PARSER_VERILOG:
 		case TM_PARSER_ZEPHIR:
 			return TRUE;
diff --git a/tests/ctags/bug2374109.vhd.tags b/tests/ctags/bug2374109.vhd.tags
index 66cd145297..27ac01496e 100644
--- a/tests/ctags/bug2374109.vhd.tags
+++ b/tests/ctags/bug2374109.vhd.tags
@@ -1,3 +1,3 @@
 # format=tagmanager
 Pow2Ì16Ö0
-ResultÌ16384Ö0
+ResultÌ16384ÎPow2Ö0
diff --git a/tests/ctags/vhdl-component.vhd.tags b/tests/ctags/vhdl-component.vhd.tags
index 4b2a0dc6b2..9dd61f2d05 100644
--- a/tests/ctags/vhdl-component.vhd.tags
+++ b/tests/ctags/vhdl-component.vhd.tags
@@ -1,6 +1,9 @@
 # format=tagmanager
-ENTITY_1Ì64Ö0
-ENTITY_2Ì64Ö0
+ENTITY_1Ì64ÎENTITY_TOP.archÖ0
+ENTITY_2Ì64ÎENTITY_TOP.archÖ0
 ENTITY_TOPÌ1Ö0
-archÌ2048Ö0
-sigÌ16384Ö0
+INPÌ16384ÎENTITY_TOPÖ0
+INPÌ16384ÎENTITY_TOP.arch.ENTITY_1Ö0
+INPÌ16384ÎENTITY_TOP.arch.ENTITY_2Ö0
+archÌ2048ÎENTITY_TOPÖ0
+sigÌ16384ÎENTITY_TOP.archÖ0
diff --git a/tests/ctags/vhdl-local.vhd b/tests/ctags/vhdl-local.vhd
index 02d73e4af1..07fc5d7236 100644
--- a/tests/ctags/vhdl-local.vhd
+++ b/tests/ctags/vhdl-local.vhd
@@ -155,6 +155,10 @@ package body types_util is
     variable s : string(1 to slen);
     variable nz : boolean := false;
     variable index : integer := -1;
+    variable vector : bit_vector(0 TO 7);
+    alias reverse_vector : bit_vector
+       ( vector'length DOWNTO 1 )
+         IS vector ;
   begin
     vv(slen*4-vlen to slen*4-1) := v;
     for i in 0 to slen-1 loop
diff --git a/tests/ctags/vhdl-local.vhd.tags b/tests/ctags/vhdl-local.vhd.tags
index 4a5608e5a0..d8892ae038 100644
--- a/tests/ctags/vhdl-local.vhd.tags
+++ b/tests/ctags/vhdl-local.vhd.tags
@@ -1,27 +1,36 @@
 # format=tagmanager
-LÌ16384Ö0
-SignalFromStringÌ16Ö0
-StringToSVectorÌ16Ö0
-StringToUVectorÌ16Ö0
-SymbolToSVectorÌ16Ö0
-UnsignedToSignedÌ16Ö0
-bodyÌ256Ö0
-cÌ16384Ö0
-iÌ16384Ö0
-indexÌ16384Ö0
-nÌ16384Ö0
-nibbleÌ4096Ö0
-nzÌ16384Ö0
-printÌ16Ö0
-sÌ16384Ö0
-sjÌ16384Ö0
-slenÌ16384Ö0
-ssÌ16384Ö0
-strlenÌ16Ö0
-tempÌ16384Ö0
-todecÌ16Ö0
-tohexÌ16Ö0
-tostÌ16Ö0
+LÌ16384Îtypes_util.printÖ0
+LÌ16384Îtypes_util.tostÖ0
+SignalFromStringÌ16Îtypes_utilÖ0
+StringToSVectorÌ16Îtypes_utilÖ0
+StringToUVectorÌ16Îtypes_utilÖ0
+SymbolToSVectorÌ16Îtypes_utilÖ0
+UnsignedToSignedÌ16Îtypes_utilÖ0
+cÌ16384Îtypes_util.SymbolToSVectorÖ0
+iÌ16384Îtypes_util.UnsignedToSignedÖ0
+indexÌ16384Îtypes_util.tostÖ0
+nÌ16384Îtypes_util.strlenÖ0
+nÌ16384Îtypes_util.tostÖ0
+nibbleÌ4096Îtypes_utilÖ0
+nzÌ16384Îtypes_util.tostÖ0
+printÌ16Îtypes_utilÖ0
+reverse_vectorÌ4096Îtypes_util.tostÖ0
+sÌ16384Îtypes_util.tostÖ0
+sjÌ16384Îtypes_util.strlenÖ0
+slenÌ16384Îtypes_util.tostÖ0
+ssÌ16384Îtypes_util.SymbolToSVectorÖ0
+strlenÌ16Îtypes_utilÖ0
+tempÌ16384Îtypes_util.SignalFromStringÖ0
+tempÌ16384Îtypes_util.StringToSVectorÖ0
+tempÌ16384Îtypes_util.StringToUVectorÖ0
+tempÌ16384Îtypes_util.SymbolToSVectorÖ0
+tempÌ16384Îtypes_util.UnsignedToSignedÖ0
+tmpÌ16384Îtypes_util.tostÖ0
+todecÌ16Îtypes_utilÖ0
+tohexÌ16Îtypes_utilÖ0
+tostÌ16Îtypes_utilÖ0
 types_utilÌ256Ö0
-vlenÌ16384Ö0
-vvÌ16384Ö0
+vectorÌ16384Îtypes_util.tostÖ0
+vlenÌ16384Îtypes_util.tostÖ0
+vvÌ16384Îtypes_util.tostÖ0
+xÌ16384Îtypes_util.tostÖ0
diff --git a/tests/ctags/vhdl-port.vhd.tags b/tests/ctags/vhdl-port.vhd.tags
index 94b6696ffa..3513e03bba 100644
--- a/tests/ctags/vhdl-port.vhd.tags
+++ b/tests/ctags/vhdl-port.vhd.tags
@@ -1,2 +1,7 @@
 # format=tagmanager
+aÌ16384Îlogical_ops_1Ö0
+bÌ16384Îlogical_ops_1Ö0
+cÌ16384Îlogical_ops_1Ö0
+dÌ16384Îlogical_ops_1Ö0
 logical_ops_1Ì1Ö0
+mÌ16384Îlogical_ops_1Ö0
diff --git a/tests/ctags/vhdl-process.vhd.tags b/tests/ctags/vhdl-process.vhd.tags
index 6972ae1103..3fac379da0 100644
--- a/tests/ctags/vhdl-process.vhd.tags
+++ b/tests/ctags/vhdl-process.vhd.tags
@@ -1,7 +1,13 @@
 # format=tagmanager
 StackTraceBufferÌ1Ö0
-arch_StackTraceBufferÌ2048Ö0
-raddrÌ16384Ö0
-ram_typeÌ4096Ö0
-regsÌ64Ö0
-stackbufÌ16384Ö0
+arch_StackTraceBufferÌ2048ÎStackTraceBufferÖ0
+i_clkÌ16384ÎStackTraceBufferÖ0
+i_raddrÌ16384ÎStackTraceBufferÖ0
+i_waddrÌ16384ÎStackTraceBufferÖ0
+i_wdataÌ16384ÎStackTraceBufferÖ0
+i_weÌ16384ÎStackTraceBufferÖ0
+o_rdataÌ16384ÎStackTraceBufferÖ0
+raddrÌ16384ÎStackTraceBuffer.arch_StackTraceBufferÖ0
+ram_typeÌ4096ÎStackTraceBuffer.arch_StackTraceBufferÖ0
+regsÌ64ÎStackTraceBuffer.arch_StackTraceBufferÖ0
+stackbufÌ16384ÎStackTraceBuffer.arch_StackTraceBufferÖ0
diff --git a/tests/ctags/vhdl-type.vhd.tags b/tests/ctags/vhdl-type.vhd.tags
index 91ec3e3719..05a8d898bc 100644
--- a/tests/ctags/vhdl-type.vhd.tags
+++ b/tests/ctags/vhdl-type.vhd.tags
@@ -1,25 +1,121 @@
 # format=tagmanager
-CFG_IRQ_ETHMACÌ16384Ö0
-CFG_IRQ_GNSSENGINEÌ16384Ö0
-CFG_IRQ_GPTIMERSÌ16384Ö0
-CFG_IRQ_TOTALÌ16384Ö0
-CFG_IRQ_UART1Ì16384Ö0
-CFG_IRQ_UNUSEDÌ16384Ö0
-axi4_flashspiÌ64Ö0
-axi4_gpioÌ64Ö0
-axi4_gptimersÌ64Ö0
-axi4_irqctrlÌ64Ö0
-axi4_otpÌ64Ö0
-axi4_pnpÌ64Ö0
-axi4_romÌ64Ö0
-axi4_sramÌ64Ö0
-axi4_uartÌ64Ö0
-reset_globalÌ64Ö0
-spi_in_typeÌ4096Ö0
-spi_out_noneÌ16384Ö0
-spi_out_typeÌ4096Ö0
-tap_jtagÌ64Ö0
+CFG_IRQ_ETHMACÌ16384Îtypes_miscÖ0
+CFG_IRQ_GNSSENGINEÌ16384Îtypes_miscÖ0
+CFG_IRQ_GPTIMERSÌ16384Îtypes_miscÖ0
+CFG_IRQ_TOTALÌ16384Îtypes_miscÖ0
+CFG_IRQ_UART1Ì16384Îtypes_miscÖ0
+CFG_IRQ_UNUSEDÌ16384Îtypes_miscÖ0
+adc_clkÌ16384Îtypes_misc.axi4_pnpÖ0
+axi4_flashspiÌ64Îtypes_miscÖ0
+axi4_gpioÌ64Îtypes_miscÖ0
+axi4_gptimersÌ64Îtypes_miscÖ0
+axi4_irqctrlÌ64Îtypes_miscÖ0
+axi4_otpÌ64Îtypes_miscÖ0
+axi4_pnpÌ64Îtypes_miscÖ0
+axi4_romÌ64Îtypes_miscÖ0
+axi4_sramÌ64Îtypes_miscÖ0
+axi4_uartÌ64Îtypes_miscÖ0
+cfgÌ16384Îtypes_misc.axi4_flashspiÖ0
+cfgÌ16384Îtypes_misc.axi4_gpioÖ0
+cfgÌ16384Îtypes_misc.axi4_gptimersÖ0
+cfgÌ16384Îtypes_misc.axi4_otpÖ0
+cfgÌ16384Îtypes_misc.axi4_pnpÖ0
+cfgÌ16384Îtypes_misc.axi4_romÖ0
+cfgÌ16384Îtypes_misc.axi4_sramÖ0
+cfgÌ16384Îtypes_misc.axi4_uartÖ0
+clkÌ16384Îtypes_misc.axi4_flashspiÖ0
+clkÌ16384Îtypes_misc.axi4_gpioÖ0
+clkÌ16384Îtypes_misc.axi4_gptimersÖ0
+clkÌ16384Îtypes_misc.axi4_irqctrlÖ0
+clkÌ16384Îtypes_misc.axi4_otpÖ0
+clkÌ16384Îtypes_misc.axi4_romÖ0
+clkÌ16384Îtypes_misc.axi4_sramÖ0
+clkÌ16384Îtypes_misc.axi4_uartÖ0
+clkÌ16384Îtypes_misc.tap_jtagÖ0
+clkÌ16384Îtypes_misc.uart_tapÖ0
+iÌ16384Îtypes_misc.axi4_gpioÖ0
+iÌ16384Îtypes_misc.axi4_pnpÖ0
+iÌ16384Îtypes_misc.axi4_romÖ0
+iÌ16384Îtypes_misc.axi4_sramÖ0
+i_axiÌ16384Îtypes_misc.axi4_flashspiÖ0
+i_axiÌ16384Îtypes_misc.axi4_gptimersÖ0
+i_axiÌ16384Îtypes_misc.axi4_irqctrlÖ0
+i_axiÌ16384Îtypes_misc.axi4_otpÖ0
+i_axiÌ16384Îtypes_misc.axi4_uartÖ0
+i_cfg_rsetupÌ16384Îtypes_misc.axi4_otpÖ0
+i_cfg_wactiveÌ16384Îtypes_misc.axi4_otpÖ0
+i_cfg_wadrsetupÌ16384Îtypes_misc.axi4_otpÖ0
+i_cfg_wholdÌ16384Îtypes_misc.axi4_otpÖ0
+i_gpioÌ16384Îtypes_misc.axi4_gpioÖ0
+i_irqsÌ16384Îtypes_misc.axi4_irqctrlÖ0
+i_mstiÌ16384Îtypes_misc.tap_jtagÖ0
+i_mstiÌ16384Îtypes_misc.uart_tapÖ0
+i_ntrstÌ16384Îtypes_misc.tap_jtagÖ0
+i_otp_busyÌ16384Îtypes_misc.axi4_pnpÖ0
+i_otp_rdataÌ16384Îtypes_misc.axi4_otpÖ0
+i_spiÌ16384Îtypes_misc.axi4_flashspiÖ0
+i_tckÌ16384Îtypes_misc.tap_jtagÖ0
+i_tdiÌ16384Îtypes_misc.tap_jtagÖ0
+i_tmsÌ16384Îtypes_misc.tap_jtagÖ0
+i_uartÌ16384Îtypes_misc.axi4_uartÖ0
+i_uartÌ16384Îtypes_misc.uart_tapÖ0
+inSysClkÌ16384Îtypes_misc.reset_globalÖ0
+inSysResetÌ16384Îtypes_misc.reset_globalÖ0
+mstcfgÌ16384Îtypes_misc.axi4_pnpÖ0
+nrstÌ16384Îtypes_misc.axi4_flashspiÖ0
+nrstÌ16384Îtypes_misc.axi4_gpioÖ0
+nrstÌ16384Îtypes_misc.axi4_gptimersÖ0
+nrstÌ16384Îtypes_misc.axi4_irqctrlÖ0
+nrstÌ16384Îtypes_misc.axi4_otpÖ0
+nrstÌ16384Îtypes_misc.axi4_pnpÖ0
+nrstÌ16384Îtypes_misc.axi4_romÖ0
+nrstÌ16384Îtypes_misc.axi4_sramÖ0
+nrstÌ16384Îtypes_misc.axi4_uartÖ0
+nrstÌ16384Îtypes_misc.tap_jtagÖ0
+nrstÌ16384Îtypes_misc.uart_tapÖ0
+oÌ16384Îtypes_misc.axi4_gpioÖ0
+oÌ16384Îtypes_misc.axi4_pnpÖ0
+oÌ16384Îtypes_misc.axi4_romÖ0
+oÌ16384Îtypes_misc.axi4_sramÖ0
+o_axiÌ16384Îtypes_misc.axi4_flashspiÖ0
+o_axiÌ16384Îtypes_misc.axi4_gptimersÖ0
+o_axiÌ16384Îtypes_misc.axi4_irqctrlÖ0
+o_axiÌ16384Îtypes_misc.axi4_otpÖ0
+o_axiÌ16384Îtypes_misc.axi4_uartÖ0
+o_busyÌ16384Îtypes_misc.axi4_otpÖ0
+o_cfgÌ16384Îtypes_misc.axi4_irqctrlÖ0
+o_gpioÌ16384Îtypes_misc.axi4_gpioÖ0
+o_gpio_dirÌ16384Îtypes_misc.axi4_gpioÖ0
+o_irqÌ16384Îtypes_misc.axi4_gptimersÖ0
+o_irqÌ16384Îtypes_misc.axi4_uartÖ0
+o_irq_meipÌ16384Îtypes_misc.axi4_irqctrlÖ0
+o_jtag_vrefÌ16384Îtypes_misc.tap_jtagÖ0
+o_mstcfgÌ16384Îtypes_misc.tap_jtagÖ0
+o_mstcfgÌ16384Îtypes_misc.uart_tapÖ0
+o_mstoÌ16384Îtypes_misc.tap_jtagÖ0
+o_mstoÌ16384Îtypes_misc.uart_tapÖ0
+o_otp_addrÌ16384Îtypes_misc.axi4_otpÖ0
+o_otp_cfg_rsetupÌ16384Îtypes_misc.axi4_pnpÖ0
+o_otp_cfg_wactiveÌ16384Îtypes_misc.axi4_pnpÖ0
+o_otp_cfg_wadrsetupÌ16384Îtypes_misc.axi4_pnpÖ0
+o_otp_cfg_wholdÌ16384Îtypes_misc.axi4_pnpÖ0
+o_otp_reÌ16384Îtypes_misc.axi4_otpÖ0
+o_otp_wdataÌ16384Îtypes_misc.axi4_otpÖ0
+o_otp_weÌ16384Îtypes_misc.axi4_otpÖ0
+o_pwmÌ16384Îtypes_misc.axi4_gptimersÖ0
+o_spiÌ16384Îtypes_misc.axi4_flashspiÖ0
+o_tdoÌ16384Îtypes_misc.tap_jtagÖ0
+o_uartÌ16384Îtypes_misc.axi4_uartÖ0
+o_uartÌ16384Îtypes_misc.uart_tapÖ0
+outResetÌ16384Îtypes_misc.reset_globalÖ0
+reset_globalÌ64Îtypes_miscÖ0
+slvcfgÌ16384Îtypes_misc.axi4_pnpÖ0
+spi_in_typeÌ4096Îtypes_miscÖ0
+spi_out_noneÌ16384Îtypes_miscÖ0
+spi_out_typeÌ4096Îtypes_miscÖ0
+sys_clkÌ16384Îtypes_misc.axi4_pnpÖ0
+tap_jtagÌ64Îtypes_miscÖ0
 types_miscÌ256Ö0
-uart_in_typeÌ4096Ö0
-uart_out_typeÌ4096Ö0
-uart_tapÌ64Ö0
+uart_in_typeÌ4096Îtypes_miscÖ0
+uart_out_typeÌ4096Îtypes_miscÖ0
+uart_tapÌ64Îtypes_miscÖ0