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This PR removes gcc-8\r\nwhich means gem5 would support GCC >= version 10.\r\n\r\nThe reason for removing gcc-8:\r\n\r\n1. We already dropped support for gcc-9. I don't see any good reason to\r\nsupport anything <9 as a result.\r\n2. GCC is relatively old, and we're probably supporting a bit too many\r\ncompiler versions anyway. In Ubuntu 22.04, gcc-11 is downloaded by\r\ndefault with `apt`. It doesn't seem many system are still using gcc.\r\n3. There is a weird compiler bug in gcc-8 which is causes failure when\r\ncompiling gem5 since the inclusion of #1123. The error received is as\r\nfollows:\r\n\r\n```sh\r\nIn file included from src/arch/riscv/tlb.hh:42,\r\n from src/arch/riscv/mmu.hh:45,\r\n from build/ALL/arch/riscv/generated/exec-g.cc.inc:14,\r\n from build/ALL/arch/riscv/generated/generic_cpu_exec.cc:5:\r\nsrc/arch/riscv/utility.hh: In instantiation of ‘FloatType gem5::RiscvISA::ftype(IntType) [with FloatType = float8_t; IntType = unsigned char]’:\r\nbuild/ALL/arch/riscv/generated/exec-ns.cc.inc:38839:42: required from ‘gem5::Fault gem5::RiscvISAInst::Vfwcvt_xu_f_vMicro::execute(gem5::ExecContext*, gem5::trace::InstRecord*) const [with ElemType = float8_t; gem5::Fault = std::shared_ptr]’\r\nbuild/ALL/arch/riscv/generated/exec-ns.cc.inc:38856:16: required from here\r\nsrc/arch/riscv/utility.hh:327:15: error: parameter ‘a’ set but not used [-Werror=unused-but-set-parameter]\r\n ftype(IntType a) -> FloatType\r\n ~~~~~~~~^\r\nsrc/arch/riscv/utility.hh: In instantiation of ‘IntType gem5::RiscvISA::f_to_wui(FloatType, uint_fast8_t) [with FloatType = float8_t; IntType = short unsigned int; uint_fast8_t = unsigned char]’:\r\nbuild/ALL/arch/riscv/generated/exec-ns.cc.inc:38838:49: required from ‘gem5::Fault gem5::RiscvISAInst::Vfwcvt_xu_f_vMicro::execute(gem5::ExecContext*, gem5::trace::InstRecord*) const [with ElemType = float8_t; gem5::Fault = std::shared_ptr]’\r\nbuild/ALL/arch/riscv/generated/exec-ns.cc.inc:38856:16: required from here\r\nsrc/arch/riscv/utility.hh:570:20: error: parameter ‘a’ set but not used [-Werror=unused-but-set-parameter]\r\n f_to_wui(FloatType a, uint_fast8_t mode)\r\n```\r\n\r\nNote: This is currently causing our SST Daily tests to fail, and our\r\ncompiler tests to fail.","shortMessageHtmlLink":"misc: Remove gcc 8 support, gem5 support GCC >= v10 (#1145)"}},{"before":"688f8fb03b2bf62234611b0e5f36a02d8f268497","after":"33cebe9376132d2f80f39440ac01a31d0bb7a355","ref":"refs/heads/develop","pushedAt":"2024-05-21T17:55:03.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"dev: add reset wrap mode to mouse.cc (#1149)\n\nThis change fixes #1148 \r\n\r\nI have only added an acknowledged return, as we dont ahve remote and\r\nwrap mode so it can only be in stream mode.\r\n\r\nChange-Id: I1882042d873ff0e9465c9491238554c8fbb9aa76","shortMessageHtmlLink":"dev: add reset wrap mode to mouse.cc (#1149)"}},{"before":"5e20438c1cbe9bbba77c85520ca14fc246a49a94","after":"688f8fb03b2bf62234611b0e5f36a02d8f268497","ref":"refs/heads/develop","pushedAt":"2024-05-21T16:59:25.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"arch-riscv: add exception code to DPRINTFS msg (#1153)\n\nChange-Id: Ib5d1dc991f18256ec634c604c776629ea31317a9","shortMessageHtmlLink":"arch-riscv: add exception code to DPRINTFS msg (#1153)"}},{"before":"0824d7f2cd9a413998c373284955fb6fcbd5f15a","after":"5e20438c1cbe9bbba77c85520ca14fc246a49a94","ref":"refs/heads/develop","pushedAt":"2024-05-21T16:58:15.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"arch-riscv: Fix GDB connection failed after #1099 (#1152)\n\nGDB connection failed after the PR[1] changed the index of CSR_FCSR to\r\nMISCREG_FCSR itself. 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If XLEN > SEW, the index value is not truncated to SEW bits.\r\n\r\nThe fix zero-extends the index value in the scalar register and the\r\nimmediate.","shortMessageHtmlLink":"arch-riscv: Fix vrgather instruction (#1134)"}},{"before":"321bd0716392c0e11c4cfb9aac9a4d774d8d36f3","after":"97a87a7c849b46b1303b7bc7ad5271e4e3ba4fd0","ref":"refs/heads/develop","pushedAt":"2024-05-16T17:09:28.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"util: Fixed gem5img.py script (#990)\n\nMade the script more robust to different names.\r\n\r\nCo-authored-by: Hossam ElAtali ","shortMessageHtmlLink":"util: Fixed gem5img.py script (#990)"}},{"before":"d48191d6088c0b20638e5ff98606eccc39fb4904","after":"321bd0716392c0e11c4cfb9aac9a4d774d8d36f3","ref":"refs/heads/develop","pushedAt":"2024-05-16T17:02:53.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"cpu: Don't change to suspend if the thread status is halted (#1039)\n\nIn our gem5 model, there are four types represent thread context:\r\nActive, Suspend, Halting and Halted\r\n\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/thread_context.hh#L99-L117\r\n\r\nWhen initializing the gem5 instance, all of the thread contexts are set\r\nHalted. The status of thread context will not be active until the\r\nWorkload initializes start up, except the StubWorkload. So if the user\r\nuses the StubWorkload, and the CPU is connected with the model_reset\r\nport. The thread context of the CPU will be activated possibly.\r\n\r\nThe following is the steps of activating thread context of the CPU\r\nwithout Workload[1] initialization or lower model_reset port[2].\r\n\r\n1. Raise the model_reset port (Change the state from Halted to Suspend)\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/base.cc#L671-L673\r\n\r\n2. Post the interrupt to CPU (Change the state from Suspend to Active)\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/base.cc#L231-L239\r\n\r\nImplementation of wakeup\r\n\r\nSimpleCPU:\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/simple/base.cc#L251-L259\r\n\r\nMinorCPU:\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/minor/cpu.cc#L143-L151\r\n\r\nO3CPU:\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/o3/cpu.cc#L1337-L1346\r\n\r\nThis CL fixed the issue when raising the model reset port to CPU(let CPU\r\nsleep) if the CPU is not activated by workload. If the CPU status is\r\nhalted, it's should not change to Suspend to avoid wake up\r\n\r\nReference\r\n\r\nThe model_reset is introduced in the CL:\r\nhttps://gem5-review.googlesource.com/c/public/gem5/+/67574/4\r\n\r\n[1] Activate by workload (ARM example):\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/arch/arm/fs_workload.cc#L101-L114\r\n\r\n[2] Lower the model_reset:\r\n\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/base.cc#L191-L192\r\nhttps://github.com/gem5/gem5/blob/5641c5e4642f7d44651f783bdb018d3cf8ba01b5/src/cpu/base.cc#L674-L685\r\n\r\nChange-Id: I5bfc0b7491d14369fff77b98b71c0ac763fb7c42","shortMessageHtmlLink":"cpu: Don't change to suspend if the thread status is halted (#1039)"}},{"before":"65976e4c6de69c2545e547dc87580a4761d39b95","after":"d48191d6088c0b20638e5ff98606eccc39fb4904","ref":"refs/heads/develop","pushedAt":"2024-05-16T15:37:01.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"arch-riscv: Add RVV FP16 support (Zvfh & Zvfhmin) (#1123)\n\nAdd support for the following two extensions:\r\n\r\n[Zvfh](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#185-zvfh-vector-extension-for-half-precision-floating-point):\r\nVector Extension for Half-Precision Floating-Point\r\n\r\n[Zvfhmin](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#184-zvfhmin-vector-extension-for-minimal-half-precision-floating-point):\r\nVector Extension for Minimal Half-Precision Floating-Point\r\n\r\nFor instructions (`vfncvt[.rtz].x[u].f.w`) and (`vfwcvt.f.x[u].v`) which\r\nwill become defined when `SEW = 8`, a new template\r\n`VectorFloatWideningAndNarrowingCvtDecodeBlock` is added and 8-bit\r\nfloating point type (`float8_t`) is defined.\r\n\r\nThe data type `float8_t` is introduced in the newer `3e` version of the\r\nSoftFloat Package, however, the current version in use is `3d` which\r\ndoes not include this definition. Despite this, `float8_t` is utilized\r\nsolely for constructing the `vfncvt[.rtz].x[u].f.w` and\r\n`vfwcvt.f.x[u].v` instructions when `SEW = 8`. There are no operations\r\nthat directly manipulate data of the `float8_t` type.","shortMessageHtmlLink":"arch-riscv: Add RVV FP16 support (Zvfh & Zvfhmin) (#1123)"}},{"before":"b279e40cb788087bab9926fa92484f57ab1e8978","after":"65976e4c6de69c2545e547dc87580a4761d39b95","ref":"refs/heads/develop","pushedAt":"2024-05-14T18:06:13.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"util: Add GNU non executable line to x86 m5 (#1116)\n\n- Adding this line as not specifiying GNU non executable stack was\r\nthrowing warnings when building m5\r\nfor ubuntu 24.04\r\n\r\nChange-Id: I620c508be4090804698391cff671ba5091b053d7","shortMessageHtmlLink":"util: Add GNU non executable line to x86 m5 (#1116)"}},{"before":"6b427a84f71a48b4d7c5d6012d99e3f3d1c73dfe","after":"b279e40cb788087bab9926fa92484f57ab1e8978","ref":"refs/heads/develop","pushedAt":"2024-05-13T21:51:39.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"BobbyRBruce","name":"Bobby R. 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Therefore, the simulation time is 0 as the user discovered.\r\nThis patch should fix this bug.\r\n\r\nChange-Id: I800dfbd28d7b2c842864a1ab7d84b8f8e17b9b3c","shortMessageHtmlLink":"stdlib: change default exit event for SIMPOINT_BEGIN (#1085)"}},{"before":null,"after":"38fbd7fe1da1c1b06f048bb2114ff70fd199915d","ref":"refs/heads/revert-1065-kvm-hybrid-pmu","pushedAt":"2024-05-13T17:27:46.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"Harshil2107","name":"Harshil Patel","path":"/Harshil2107","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/91860903?s=80&v=4"},"commit":{"message":"Revert \"cpu-kvm: Support perf counters on hybrid host architectures\"","shortMessageHtmlLink":"Revert \"cpu-kvm: Support perf counters on hybrid host architectures\""}},{"before":"53245fa0e8fc0625fdf851a87ed7e4a9c18e47a5","after":"10b24dc9a477d9c3b82c1a4c86c7462d65d3a64d","ref":"refs/heads/develop","pushedAt":"2024-05-13T15:56:23.000Z","pushType":"pr_merge","commitsCount":4,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"arch-arm: Implement FEAT_MPAM in CPU (#1082)\n\nThis PR implements FEAT_MPAM on the CPU side. We define a MPAM system\r\nregisters and a mechanism\r\nfor tagging memory requests with the MPAM information bundle as\r\nspecified in existing documentation [1].\r\n\r\nWhat this PR is *not* covering is the MPAM implementation in a MSC\r\n(Memory System Component).\r\nWhich means at the moment it's only possible to have static partitioning\r\nschemes (via the PartitioningPolicies\r\nalready part of gem5) and there is currently no way to dynamically\r\nprogram partitions at runtime.\r\n\r\n[1]: https://developer.arm.com/documentation/ddi0487/latest/","shortMessageHtmlLink":"arch-arm: Implement FEAT_MPAM in CPU (#1082)"}},{"before":"e3c2a322a1f940c03bb15d32a0c7fc6fb49d22b4","after":"53245fa0e8fc0625fdf851a87ed7e4a9c18e47a5","ref":"refs/heads/develop","pushedAt":"2024-05-10T17:21:48.000Z","pushType":"pr_merge","commitsCount":3,"pusher":{"login":"ivanaamit","name":"Ivana Mitrovic","path":"/ivanaamit","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/144054478?s=80&v=4"},"commit":{"message":"arch-riscv: Fix CSR instruction behavior 2nd attempts (#1099)\n\nQuote from change[1]\r\n\r\n> The RISC-V spec clarifies the CSR instruction operation, some of them\r\nshall not read or write CSR by the hints of RD/RS1/uimm, but the\r\noriginal version use the 'data != oldData' condition to determine\r\nwhether write or not, and always read CSR first.\r\nSee CSR instruction in spec:\r\nSection 9.1 Page 56 of\r\nhttps://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf\r\n\r\n|||Register operand|||\r\n|--- |--- |--- |--- |--- |\r\n|Instruction|rd is x0|rs1 is x0|Reads CSR|Writes CSR|\r\n|CSRRW|Yes|-|No|Yes|\r\n|CSRRW|No|-|Yes|Yes|\r\n|CSRRS/CSRRC|-|Yes|Yes|No|\r\n|CSRRS/CSRRC|-|No|Yes|Yes|\r\n|||Immediate operand|||\r\n|Instruction|rd is x0|uimm = 0|Reads CSR|Writes\r\nCSR|\r\n|CSRRWI|Yes|-|No|Yes|\r\n|CSRRWI|No|-|Yes|Yes|\r\n|CSRRSI/CSRRCI|-|Yes|Yes|No|\r\n|CSRRSI/CSRRCI|-|No|Yes|Yes|\r\n\r\nThe issue cause the ubuntu hanging because we shared the same status CSR\r\nwith `mstatus`, `sstatus` and `ustatus` and interrupt enabling CSR with\r\nmip, sip and uip. We may need to read origin CSR without effect of\r\nunmask bits to avoid override the bits of other CSR. Now the ubuntu can\r\nwork after the patch merged.\r\n\r\n[1] https://gem5-review.googlesource.com/c/public/gem5/+/67717","shortMessageHtmlLink":"arch-riscv: Fix CSR instruction behavior 2nd attempts (#1099)"}}],"hasNextPage":true,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEU_hwvAA","startCursor":null,"endCursor":null}},"title":"Activity · gem5/gem5"}