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Pull requests list

arch-arm: Automatically enable stat probe listeners arch-arm The ARM ISA
#2371 opened Jun 12, 2025 by giactra Loading… v25.0
1
misc: Pre commit clang format example (Option 3?) misc Anything outside of the current labeling categories
#2370 opened Jun 12, 2025 by BobbyRBruce • Draft
stdlib: Append resource version to cached resource filename stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2368 opened Jun 11, 2025 by BobbyRBruce Loading…
3
sim: Add NumericSignalSourcePort. sim General gem5 Simulation Components
#2353 opened Jun 6, 2025 by dl8sd11 • Draft
1
1
arch-x86: automatically exit X86 simulations on kernel panic arch-x86 The X86 ISA
#2351 opened Jun 6, 2025 by erin-le • Draft
Add Initial Support for VSX Instructions (mtvsrd, mfvsrd) in Power ISA arch-power The POWER ISA
#2339 opened Jun 4, 2025 by divyangt-07 Loading…
1
14
misc: v25.0.0.0 release notes doc Documentation misc Anything outside of the current labeling categories
#2336 opened Jun 3, 2025 by erin-le Loading…
7
Release v25.0.0.0 misc Anything outside of the current labeling categories
#2322 opened May 28, 2025 by BobbyRBruce Loading…
Introduce git-clang-format to gem5 with wrapper script (Option 2 of 2) misc Anything outside of the current labeling categories
#2314 opened May 27, 2025 by rjc-arch Loading…
Introduce git-clang-format to gem5 (Simple, Option 1 of 2) misc Anything outside of the current labeling categories
#2313 opened May 27, 2025 by rjc-arch Loading…
10
cpu-o3: stall fetch from commit when trap event is pending cpu-o3 gem5's Out-Of-Order CPU
#2312 opened May 27, 2025 by saul44203 Loading…
1
6
mem-ruby: return early response for software prefetches mem-ruby Ruby caches, structures, and protocols
#2311 opened May 27, 2025 by saul44203 • Draft
cpu: Add user and kernel-mode stats cpu General gem5 CPU code (e.g., `BaseCPU`) stats The gem5 statistics code and related infrastructure
#2308 opened May 26, 2025 by cmolder Loading…
7
Stdlib: Add prebuilt validated RISCV Boards - Rocket and Unleashed stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2304 opened May 25, 2025 by karnapathak Loading…
1
cpu:Add gshare branch predictor model cpu General gem5 CPU code (e.g., `BaseCPU`)
#2303 opened May 25, 2025 by karnapathak Loading…
1
5
tests: Add processor switching tests tests gem5's Testing Infrastructure
#2301 opened May 24, 2025 by erin-le Loading…
1
dev: reworks PCI to add a PCI host bridge dev General gem5 development code. Found in "src/dev"
#2298 opened May 23, 2025 by clemdiep Loading…
1
mem,cpu: Make load-to-use constant when L1D hit cpu-o3 gem5's Out-Of-Order CPU mem General Memory Systems (e.g., XBar, Packet)
#2292 opened May 21, 2025 by pierav Loading…
6
python: improve error message in SimObject __setattr__ python gem5's Python SimObject wrapping and infrastructure
#2269 opened May 14, 2025 by harry900831 Loading…
8
util: add dashboard for viewing gem5 simulation progress util Utilities for gem5. Typically found in "util"
#2250 opened May 5, 2025 by erin-le • Draft
29
Dockerfile updates apr 2025 util-docker Docker util files. That found in "utils/docker"
#2244 opened May 4, 2025 by BobbyRBruce • Draft
4
misc: Add useful workspace settings for GitHub and PR extensions misc Anything outside of the current labeling categories
#2228 opened Apr 29, 2025 by BobbyRBruce Loading…
1
mem: cache bank implementation mem General Memory Systems (e.g., XBar, Packet)
#2198 opened Apr 18, 2025 by amin-mamandi Loading…
4
misc: PoC Bazel integration misc Anything outside of the current labeling categories
#2172 opened Apr 10, 2025 by hchsiao • Draft
2
stdlib: Add a simulator API to set the exit event handler stdlib The gem5 standard library. Code typically found under "src/pythongem5"
#2156 opened Apr 7, 2025 by pranith Loading…
7
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