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ggml-cpu: add RISC-V Vector support for RWKV WKV6 operation #17716
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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Please note that |
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I'm thinking that we should deprecate these ops since they are very model-specific: Lines 2389 to 2417 in 37adc9c
Probably not worth investing much effort in optimizing. Rather, look to implement them as combination of other fundamental ops. |
Wanted to check in on this PR. Should I:
Happy to follow whatever direction works best for the project. Thanks! |
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The best way is to try to implement these operations with other |
This PR adds RISC-V Vector (RVV) extension support for the RWKV WKV6 operation, enabling vectorized computation on RISC-V platforms.