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branch: ghc-lwc2
Commits on Sep 28, 2013
  1. @kayceesrk
Commits on Sep 27, 2013
  1. @kayceesrk

    Removes tabs

    kayceesrk authored
  2. @kayceesrk

    Merging master

    kayceesrk authored
  3. @kayceesrk

    Update library refs

    kayceesrk authored
  4. @kayceesrk
  5. @kayceesrk
  6. @kayceesrk
  7. @kayceesrk

    Pulling changes from head

    kayceesrk authored
  8. @monoidal
  9. @monoidal
  10. @thoughtpolice

    Make typeRep_RDR use typeRep# instead of typeRep

    thoughtpolice authored
    Authored-by: Edward Kmett <>
    Authored-by: Austin Seipp <>
    Signed-off-by: Austin Seipp <>
  11. @thoughtpolice

    Implement an unlifted Proxy type, Proxy#

    thoughtpolice authored
    A value of type 'Proxy# a' can only be created through the new,
    primitive witness 'proxy# :: Proxy# a' - a Proxy# has no runtime
    representation and is thus free.
    This lets us clean up the internals of TypeRep, as well as Adam's future
    work concerning records (by using a zero-width primitive type.)
    Authored-by: Edward Kmett <>
    Authored-by: Austin Seipp <>
    Signed-off-by: Austin Seipp <>
Commits on Sep 26, 2013
  1. @hvr

    Update `primitive` and `vector` packages

    hvr authored
     - `primitive` is updated to upstream's HEAD which is essentially
       `primitive-`, plus a core-lint-error workaround for #8355 and
       some minor cleanups.
     - `vector` is updated to upstreams `vector-` release
    Note: The upstream repo location has changed to GitHub,
          hence the update in the `packages` file
    Signed-off-by: Herbert Valerio Riedel <>
Commits on Sep 24, 2013
  1. @Tarrasch @ggreif

    Fix user guide documentation about unboxed values

    Tarrasch authored ggreif committed
    Signed-off-by: Arash Rouhani <>
  2. @ggreif

    Typo in comment

    ggreif authored
  3. @yav

    Add a type-function for subtraction.

    yav authored
    This is used in the definition of `ToNat1` in the `base` library
    (module GHC.TypeLits).
Commits on Sep 23, 2013
  1. @monoidal
  2. @parcs

    Fix build when PROF_SPIN is unset

    parcs authored
    whitehole_spin is only defined when PROF_SPIN is set.
  3. @parcs

    Fix the definition of cas() on x86 (#8219)

    parcs authored
    *p is both read and written to by the cmpxchg instruction, and therefore
    should be given the '+' constraint modifier.
    (In GCC's extended ASM language, '+' means that the operand is both read
    and written to whereas '=' means that it is only written to.)
    Otherwise, the compiler is allowed to rewrite something like
    SpinLock lock;
    initSpinLock(&lock);       /* sets lock = 1 */
    SpinLock lock;
    because according to the asm statement, the previous value of 'lock' is
    not important.
  4. @monoidal

    Remove fglasgow-exts from ghci --help

    monoidal authored
    It has been deprecated for long and already removed from ghc --help
  5. @simonmar

    Fix linker_unload now that we are running constructors in the linker …

    simonmar authored
    See also #5435.
    Now we have to remember the the StablePtrs that get created by the
    module initializer so that we can free them again in unloadObj().
  6. @simonmar

    Discard unreachable code in the register allocator (#7574)

    simonmar authored
    The problem with unreachable code is that it might refer to undefined
    registers.  This happens accidentally: a block can be orphaned by an
    optimisation, for example when the result of a comparsion becomes
    The register allocator panics when it finds an undefined register,
    because they shouldn't occur in generated code.  So we need to also
    discard unreachable code to prevent this panic being triggered by
    The register alloator already does a strongly-connected component
    analysis, so it ought to be easy to make it discard unreachable code
    as part of that traversal.  It turns out that we need a different
    variant of the scc algorithm to do that (see Digraph), however the new
    variant also generates slightly better code by putting the blocks
    within a loop in a better order for register allocation.
  7. @monoidal


    monoidal authored
  8. Catch potential garbage after -msse.

    Geoffrey Mainland authored
  9. Merge branch 'wip/simd'

    Geoffrey Mainland authored
    This merge revises and extends the current SIMD support in GHC. Notable
     * Support for AVX, AVX2, and AVX-512. Support for AVX-512 is untested.
     * SIMD primops are currently LLVM-only and documented in
     * By default only 128-bit wide SIMD vectors are passed in registers, and then
       only on the X86_64 architecture. There is a "hidden" flag,
       -fllvm-pass-vectors-in-regs, that causes GHC to generate LLVM code that
       assumes all vectors are passed in registers by LLVM. This can be used with a
       suitably patched version of LLVM, and if we get LLVM 3.4 patched, we can
       consider turning it on by default for LLVM 3.4+. This would mean that we
       couldn't mix LLVM <3.4-compiled object files with LLVM >=3.4-compiled object
       files, but I don't see that as much of a problem.
     * utils/genprimcode has been hacked up to allow us to write vector operations
       once and have them instantiated at multiple vector types. I'm not thrilled
       with this solution, but after discussing with Simon PJ, what I've implemented
       seems to be the minimal reasonable solution to the problem of exploding
       primop boilerplate. The changes are documented in
     * Error handling is sub-optimal. My patch checks to make sure that vector
       primops can be compiled efficiently based on the current set of dynamic
       flags. For example, if -mavx is not specified and the user tries to use a
       primop that adds together two 256-bit wide vectors of double-precision
       elements, the user will see an error message like:
         ghc-stage2: sorry! (unimplemented feature or known bug)
           (GHC version 7.7.20130916 for x86_64-unknown-linux):
    	 256-bit wide floating point SIMD vector instructions require at least -mavx.
  10. Check that SIMD vector instructions are compatible with current set o…

    Geoffrey Mainland authored
    …f dynamic flags.
    SIMD vector instructions currently require the LLVM back-end. The set of
    available instructions also depends on the set of architecture flags specified
    on the command line.
  11. Enable -msse to be specified by itself.

    Geoffrey Mainland authored
    This sets the SSE "version" to 1.0.
  12. By default, only pass 128-bit SIMD vectors in registers on X86-64.

    Geoffrey Mainland authored
    LLVM's GHC calling convention only allows 128-bit SIMD vectors to be passed in
    machine registers on X86-64. This may change in LLVM 3.4; the hidden flag
    -fllvm-pass-vectors-in-regs causes all SIMD vector widths to be passed in
    registers on both X86-64 and on X86-32.
  13. Add 512-bit-wide SIMD primitives.

    Geoffrey Mainland authored
  14. Pass 512-bit-wide vectors in registers.

    Geoffrey Mainland authored
  15. Add support for 512-bit-wide vectors.

    Geoffrey Mainland authored
  16. Add Cmm support for 512-bit-wide values.

    Geoffrey Mainland authored
  17. Add support for -mavx512* flags.

    Geoffrey Mainland authored
  18. Add 256-bit-wide SIMD primitives.

    Geoffrey Mainland authored
  19. Pass 256-bit-wide vectors in registers.

    Geoffrey Mainland authored
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