diff --git a/testsuite/issues/issue160/fpu.vhdl b/testsuite/issues/issue160/fpu.vhdl new file mode 100644 index 0000000..b94509f --- /dev/null +++ b/testsuite/issues/issue160/fpu.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity fpu is + port ( + clk : in std_ulogic; + addr : in std_ulogic_vector(1 downto 0); + inverse_est : out std_ulogic_vector(17 downto 0) + ); +end entity fpu; + +architecture behaviour of fpu is + type lookup_table is array(0 to 3) of std_ulogic_vector(17 downto 0); + + signal inverse_table : lookup_table := ( + 18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460" + ); +begin + lut_access: process(clk) + begin + if rising_edge(clk) then + inverse_est <= inverse_table(to_integer(unsigned(addr))); + end if; + end process; + +end architecture behaviour; diff --git a/testsuite/issues/issue160/fpu2.vhdl b/testsuite/issues/issue160/fpu2.vhdl new file mode 100644 index 0000000..0b56725 --- /dev/null +++ b/testsuite/issues/issue160/fpu2.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity fpu is + port ( + clk : in std_ulogic; + addr : in std_ulogic_vector(1 downto 0); + inverse_est : out std_ulogic_vector(17 downto 0) + ); +end entity fpu; + +architecture behaviour of fpu is + type lookup_table is array(0 to 3) of std_ulogic_vector(17 downto 0); + + constant inverse_table : lookup_table := ( + 18x"3fc01", 18x"3f411", 18x"3ec31", 18x"3e460" + ); +begin + lut_access: process(clk) + begin + if rising_edge(clk) then + inverse_est <= inverse_table(to_integer(unsigned(addr))); + end if; + end process; + +end architecture behaviour; diff --git a/testsuite/issues/issue160/testsuite.sh b/testsuite/issues/issue160/testsuite.sh new file mode 100755 index 0000000..0219689 --- /dev/null +++ b/testsuite/issues/issue160/testsuite.sh @@ -0,0 +1,10 @@ +#!/bin/sh + +topdir=../.. +. $topdir/testenv.sh + +for f in fpu fpu2; do + synth_import "--std=08 ${f}.vhdl -e" +done + +echo OK