From 70d07b47de95525c4854cdede07264a89e3914e8 Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Wed, 27 Sep 2023 14:01:43 +0100 Subject: [PATCH 1/6] Add Architecture::Sharc --- src/common.rs | 2 ++ src/read/elf/file.rs | 1 + src/write/elf/object.rs | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/common.rs b/src/common.rs index 0e6af091..158ff8a8 100644 --- a/src/common.rs +++ b/src/common.rs @@ -26,6 +26,7 @@ pub enum Architecture { Riscv64, S390x, Sbf, + Sharc, Sparc64, Wasm32, Wasm64, @@ -59,6 +60,7 @@ impl Architecture { Architecture::Riscv64 => Some(AddressSize::U64), Architecture::S390x => Some(AddressSize::U64), Architecture::Sbf => Some(AddressSize::U64), + Architecture::Sharc => Some(AddressSize::U32), Architecture::Sparc64 => Some(AddressSize::U64), Architecture::Wasm32 => Some(AddressSize::U32), Architecture::Wasm64 => Some(AddressSize::U64), diff --git a/src/read/elf/file.rs b/src/read/elf/file.rs index 67be37e2..39c8ef38 100644 --- a/src/read/elf/file.rs +++ b/src/read/elf/file.rs @@ -178,6 +178,7 @@ where // We only support the 64-bit variant s390x here. (elf::EM_S390, true) => Architecture::S390x, (elf::EM_SBF, _) => Architecture::Sbf, + (elf::EM_SHARC, false) => Architecture::Sharc, (elf::EM_SPARCV9, true) => Architecture::Sparc64, (elf::EM_XTENSA, false) => Architecture::Xtensa, _ => Architecture::Unknown, diff --git a/src/write/elf/object.rs b/src/write/elf/object.rs index 421d23a8..d62df560 100644 --- a/src/write/elf/object.rs +++ b/src/write/elf/object.rs @@ -141,6 +141,7 @@ impl<'a> Object<'a> { Architecture::Riscv32 => true, Architecture::S390x => true, Architecture::Sbf => false, + Architecture::Sharc => true, Architecture::Sparc64 => true, Architecture::Xtensa => true, _ => { @@ -345,6 +346,7 @@ impl<'a> Object<'a> { Architecture::Riscv64 => elf::EM_RISCV, Architecture::S390x => elf::EM_S390, Architecture::Sbf => elf::EM_SBF, + Architecture::Sharc => elf::EM_SHARC, Architecture::Sparc64 => elf::EM_SPARCV9, Architecture::Xtensa => elf::EM_XTENSA, _ => { From 0b492edfb31f4014d7bafc80025c11b490fc899b Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Fri, 6 Oct 2023 22:06:38 +0100 Subject: [PATCH 2/6] elf: Add support for SHARC+ relocations --- src/common.rs | 48 ++++++++++++++++++ src/elf.rs | 100 +++++++++++++++++++++++++++++++++++++ src/read/elf/relocation.rs | 51 +++++++++++++++++++ src/write/elf/object.rs | 47 +++++++++++++++++ 4 files changed, 246 insertions(+) diff --git a/src/common.rs b/src/common.rs index 158ff8a8..b1eddd61 100644 --- a/src/common.rs +++ b/src/common.rs @@ -369,6 +369,54 @@ pub enum RelocationEncoding { /// /// The `RelocationKind` must be PC relative. LoongArchBranch, + + /// SHARC+ 24-bit absolute address in a Type A instruction + /// + /// Used with `RelocationKind::Absolute`. + /// See [elf::R_SHARC_ADDR24_v3] + SharcAbs24TypeA, + + /// SHARC+ 32-bit absolute address in a Type A instruction + /// + /// Used with `RelocationKind::Absolute`. + /// See [elf::R_SHARC_ADDR32_v3] + SharcAbs32TypeA, + + /// SHARC+ 32-bit absolute address in a 32-bit STT_OBJECT location + /// + /// See [elf::R_SHARC_ADDRVAR_V3] + SharcAbs32Data, + + /// SHARC+ 6-bit relative address in a Type A instruction + /// + /// The `RelocationKind` must be PC relative. + SharcPcr6TypeA, + + /// SHARC+ 24-bit relative address in a Type A instruction + /// + /// The `RelocationKind` must be PC relative. + SharcPcr24TypeA, + + /// SHARC+ 6-bit absolute address in the immediate value field of a Type A instruction + SharcAbs6TypeA, + + /// SHARC+ 16-bit absolute address in the immediate value field of a Type A instruction + SharcAbs16TypeA, + + /// SHARC+ 6-bit absolute address in the immediate value field of a Type B instruction + SharcAbs6TypeB, + + /// SHARC+ 7-bit absolute address in the immediate value field of a Type B instruction + SharcAbs7TypeB, + + /// SHARC+ 16-bit absolute address in a Type B instruction + SharcAbs16TypeB, + + /// SHARC+ 6-bit relative address in a Type B instruction + SharcPcr6TypeB, + + /// SHARC+ 16-bit absolute address in a 16-bit STT_OBJECT location + SharcAbs16Data, } /// File flags that are specific to each file format. diff --git a/src/elf.rs b/src/elf.rs index f202c598..14f4b67b 100644 --- a/src/elf.rs +++ b/src/elf.rs @@ -2207,6 +2207,106 @@ pub const R_386_IRELATIVE: u32 = 42; /// Load from 32 bit GOT entry, relaxable. pub const R_386_GOT32X: u32 = 43; +// ADI SHARC specific definitions + +// SHARC values for `Rel*::r_type` + +/// 24-bit absolute address in bits 23:0 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 25a (PC_DIRECT) +pub const R_SHARC_ADDR24_V3: u32 = 0x0b; + +/// 32-bit absolute address in bits 31:0 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 14a +/// * Type 14d +/// * Type 15a +/// * Type 16a +/// * Type 17a +/// * Type 18a +/// * Type 19a +pub const R_SHARC_ADDR32_V3: u32 = 0x0c; + +/// 32-bit absolute address in bits 31:0 of a 32-bit data location +pub const R_SHARC_ADDR_VAR_V3: u32 = 0x0d; + +/// 6-bit PC-relative address in bits 32:27 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 9a +/// * Type 10a +pub const R_SHARC_PCRSHORT_V3: u32 = 0x0e; + +/// 24-bit PC-relative address in bits 23:0 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 8a +/// * Type 12a (truncated to 23 bits after relocation) +/// * Type 13a (truncated to 23 bits after relocation) +/// * Type 25a (PC Relative) +pub const R_SHARC_PCRLONG_V3: u32 = 0x0f; + +/// 6-bit absolute address in bits 32:27 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 4a +/// * Type 4b +/// * Type 4d +pub const R_SHARC_DATA6_V3: u32 = 0x10; + +/// 16-bit absolute address in bits 39:24 of a 48-bit instr +/// +/// Targets: +/// +/// * Type 12a +pub const R_SHARC_DATA16_V3: u32 = 0x11; + +/// 6-bit absolute address into bits 16:11 of a 32-bit instr +/// +/// Targets: +/// +/// * Type 4b +pub const R_SHARC_DATA6_VISA_V3: u32 = 0x12; + +/// 7-bit absolute address into bits 6:0 of a 32-bit instr +pub const R_SHARC_DATA7_VISA_V3: u32 = 0x13; + +/// 16-bit absolute address into bits 15:0 of a 32-bit instr +pub const R_SHARC_DATA16_VISA_V3: u32 = 0x14; + +/// 6-bit PC-relative address into bits 16:11 of a Type B +/// +/// Targets: +/// +/// * Type 9b +pub const R_SHARC_PCR6_VISA_V3: u32 = 0x17; + +/// 16-bit absolute address into bits 15:0 of a 16-bit location. +pub const R_SHARC_ADDR_VAR16_V3: u32 = 0x19; + +pub const R_SHARC_CALC_PUSH_ADDR: u32 = 0xe0; +pub const R_SHARC_CALC_PUSH_ADDEND: u32 = 0xe1; +pub const R_SHARC_CALC_ADD: u32 = 0xe2; +pub const R_SHARC_CALC_SUB: u32 = 0xe3; +pub const R_SHARC_CALC_MUL: u32 = 0xe4; +pub const R_SHARC_CALC_DIV: u32 = 0xe5; +pub const R_SHARC_CALC_MOD: u32 = 0xe6; +pub const R_SHARC_CALC_LSHIFT: u32 = 0xe7; +pub const R_SHARC_CALC_RSHIFT: u32 = 0xe8; +pub const R_SHARC_CALC_AND: u32 = 0xe9; +pub const R_SHARC_CALC_OR: u32 = 0xea; +pub const R_SHARC_CALC_XOR: u32 = 0xeb; +pub const R_SHARC_CALC_PUSH_LEN: u32 = 0xec; +pub const R_SHARC_CALC_NOT: u32 = 0xf6; + + // SUN SPARC specific definitions. // SPARC values for `st_type` component of `Sym*::st_info`. diff --git a/src/read/elf/relocation.rs b/src/read/elf/relocation.rs index 78032dfd..cdf66266 100644 --- a/src/read/elf/relocation.rs +++ b/src/read/elf/relocation.rs @@ -404,6 +404,57 @@ fn parse_relocation( elf::R_SBF_64_32 => (RelocationKind::Absolute, 32), r_type => (RelocationKind::Elf(r_type), 0), }, + elf::EM_SHARC => match reloc.r_type(endian, false) { + elf::R_SHARC_ADDR24_V3 => { + encoding = RelocationEncoding::SharcAbs24TypeA; + (RelocationKind::Absolute, 48) + } + elf::R_SHARC_ADDR32_V3 => { + encoding = RelocationEncoding::SharcAbs32TypeA; + (RelocationKind::Absolute, 48) + } + elf::R_SHARC_ADDR_VAR_V3 => { + encoding = RelocationEncoding::SharcAbs32Data; + (RelocationKind::Absolute, 32) + } + elf::R_SHARC_PCRSHORT_V3 => { + encoding = RelocationEncoding::SharcPcr6TypeA; + (RelocationKind::Relative, 48) + } + elf::R_SHARC_PCRLONG_V3 => { + encoding = RelocationEncoding::SharcPcr24TypeA; + (RelocationKind::Relative, 48) + } + elf::R_SHARC_DATA6_V3 => { + encoding = RelocationEncoding::SharcAbs6TypeA; + (RelocationKind::Absolute, 48) + } + elf::R_SHARC_DATA16_V3 => { + encoding = RelocationEncoding::SharcAbs16TypeA; + (RelocationKind::Absolute, 48) + } + elf::R_SHARC_DATA6_VISA_V3 => { + encoding = RelocationEncoding::SharcAbs6TypeB; + (RelocationKind::Absolute, 32) + } + elf::R_SHARC_DATA7_VISA_V3 => { + encoding = RelocationEncoding::SharcAbs7TypeB; + (RelocationKind::Absolute, 32) + } + elf::R_SHARC_DATA16_VISA_V3 => { + encoding = RelocationEncoding::SharcAbs16TypeB; + (RelocationKind::Absolute, 32) + } + elf::R_SHARC_PCR6_VISA_V3 => { + encoding = RelocationEncoding::SharcPcr6TypeB; + (RelocationKind::Relative, 32) + } + elf::R_SHARC_ADDR_VAR16_V3 => { + encoding = RelocationEncoding::SharcAbs16Data; + (RelocationKind::Absolute, 16) + } + r_type => (RelocationKind::Elf(r_type), 0), + }, elf::EM_SPARC | elf::EM_SPARC32PLUS | elf::EM_SPARCV9 => { match reloc.r_type(endian, false) { elf::R_SPARC_32 | elf::R_SPARC_UA32 => (RelocationKind::Absolute, 32), diff --git a/src/write/elf/object.rs b/src/write/elf/object.rs index d62df560..1a6df7e5 100644 --- a/src/write/elf/object.rs +++ b/src/write/elf/object.rs @@ -768,6 +768,53 @@ impl<'a> Object<'a> { return Err(Error(format!("unimplemented relocation {:?}", reloc))); } }, + Architecture::Sharc => match (reloc.kind, reloc.encoding, reloc.size) { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs32TypeA, 48) => { + elf::R_SHARC_ADDR32_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs32Data, 32) => { + elf::R_SHARC_ADDR_VAR_V3 + } + (RelocationKind::Relative, RelocationEncoding::SharcPcr24TypeA, 48) => { + elf::R_SHARC_PCRLONG_V3 + } + (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeA, 48) => { + elf::R_SHARC_PCRSHORT_V3 + } + (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeB, 32) => { + elf::R_SHARC_PCRSHORT_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs16Data, 16) => { + elf::R_SHARC_ADDR_VAR16_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeA, 48) => { + elf::R_SHARC_DATA16_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeB, 32) => { + elf::R_SHARC_DATA16_VISA_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs24TypeA, 48) => { + elf::R_SHARC_ADDR24_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeA, 48) => { + elf::R_SHARC_DATA6_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeB, 32) => { + elf::R_SHARC_DATA6_VISA_V3 + } + (RelocationKind::Absolute, RelocationEncoding::SharcAbs7TypeB, 32) => { + elf::R_SHARC_DATA7_VISA_V3 + } + (_, RelocationEncoding::Generic, _) => { + return Err(Error(format!( + "SHARC+ ISA does not have a generic relocation encoding" + ))); + } + (RelocationKind::Elf(x), _, _) => x, + _ => { + return Err(Error(format!("unimplemented relocation {:?}", reloc))); + } + }, Architecture::Sparc64 => match (reloc.kind, reloc.encoding, reloc.size) { // TODO: use R_SPARC_32/R_SPARC_64 if aligned. (RelocationKind::Absolute, _, 32) => elf::R_SPARC_UA32, From 460f5ae1f154c8ca5c19cc9049310aa8ca4b6199 Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Mon, 13 Nov 2023 11:24:38 +0000 Subject: [PATCH 3/6] elf: sharc: add SHT_SHARC_ADI_ATTRIBUTES Encoded as normal ELF attributes, with proprietary tags. I have an implementation of the full encode/decode in a private repo, which I can share for porting into `object` if needed, but it seems a bit out of scope. --- src/elf.rs | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/elf.rs b/src/elf.rs index 14f4b67b..16408fd4 100644 --- a/src/elf.rs +++ b/src/elf.rs @@ -2306,6 +2306,10 @@ pub const R_SHARC_CALC_XOR: u32 = 0xeb; pub const R_SHARC_CALC_PUSH_LEN: u32 = 0xec; pub const R_SHARC_CALC_NOT: u32 = 0xf6; +// SHARC values for `SectionHeader*::sh_type`. + +/// .adi.attributes +pub const SHT_SHARC_ADI_ATTRIBUTES: u32 = SHT_LOPROC + 0x2; // SUN SPARC specific definitions. From b1d76dac821c156e26916c2bc494b44b5fcbc3a3 Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Mon, 13 Nov 2023 18:12:44 +0000 Subject: [PATCH 4/6] elf: sharc: Use reloc field length as `size` E.g. a 6-bit PC-relative relocation into a 48-bit instruction has `size == 6`, not `size == 48`. --- src/read/elf/relocation.rs | 20 ++++++++++---------- src/write/elf/object.rs | 20 ++++++++++---------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/read/elf/relocation.rs b/src/read/elf/relocation.rs index cdf66266..4ef2e88d 100644 --- a/src/read/elf/relocation.rs +++ b/src/read/elf/relocation.rs @@ -407,11 +407,11 @@ fn parse_relocation( elf::EM_SHARC => match reloc.r_type(endian, false) { elf::R_SHARC_ADDR24_V3 => { encoding = RelocationEncoding::SharcAbs24TypeA; - (RelocationKind::Absolute, 48) + (RelocationKind::Absolute, 24) } elf::R_SHARC_ADDR32_V3 => { encoding = RelocationEncoding::SharcAbs32TypeA; - (RelocationKind::Absolute, 48) + (RelocationKind::Absolute, 32) } elf::R_SHARC_ADDR_VAR_V3 => { encoding = RelocationEncoding::SharcAbs32Data; @@ -419,35 +419,35 @@ fn parse_relocation( } elf::R_SHARC_PCRSHORT_V3 => { encoding = RelocationEncoding::SharcPcr6TypeA; - (RelocationKind::Relative, 48) + (RelocationKind::Relative, 6) } elf::R_SHARC_PCRLONG_V3 => { encoding = RelocationEncoding::SharcPcr24TypeA; - (RelocationKind::Relative, 48) + (RelocationKind::Relative, 24) } elf::R_SHARC_DATA6_V3 => { encoding = RelocationEncoding::SharcAbs6TypeA; - (RelocationKind::Absolute, 48) + (RelocationKind::Absolute, 6) } elf::R_SHARC_DATA16_V3 => { encoding = RelocationEncoding::SharcAbs16TypeA; - (RelocationKind::Absolute, 48) + (RelocationKind::Absolute, 16) } elf::R_SHARC_DATA6_VISA_V3 => { encoding = RelocationEncoding::SharcAbs6TypeB; - (RelocationKind::Absolute, 32) + (RelocationKind::Absolute, 6) } elf::R_SHARC_DATA7_VISA_V3 => { encoding = RelocationEncoding::SharcAbs7TypeB; - (RelocationKind::Absolute, 32) + (RelocationKind::Absolute, 7) } elf::R_SHARC_DATA16_VISA_V3 => { encoding = RelocationEncoding::SharcAbs16TypeB; - (RelocationKind::Absolute, 32) + (RelocationKind::Absolute, 16) } elf::R_SHARC_PCR6_VISA_V3 => { encoding = RelocationEncoding::SharcPcr6TypeB; - (RelocationKind::Relative, 32) + (RelocationKind::Relative, 16) } elf::R_SHARC_ADDR_VAR16_V3 => { encoding = RelocationEncoding::SharcAbs16Data; diff --git a/src/write/elf/object.rs b/src/write/elf/object.rs index 1a6df7e5..d9102847 100644 --- a/src/write/elf/object.rs +++ b/src/write/elf/object.rs @@ -769,40 +769,40 @@ impl<'a> Object<'a> { } }, Architecture::Sharc => match (reloc.kind, reloc.encoding, reloc.size) { - (RelocationKind::Absolute, RelocationEncoding::SharcAbs32TypeA, 48) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs32TypeA, 32) => { elf::R_SHARC_ADDR32_V3 } (RelocationKind::Absolute, RelocationEncoding::SharcAbs32Data, 32) => { elf::R_SHARC_ADDR_VAR_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr24TypeA, 48) => { + (RelocationKind::Relative, RelocationEncoding::SharcPcr24TypeA, 24) => { elf::R_SHARC_PCRLONG_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeA, 48) => { + (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeA, 6) => { elf::R_SHARC_PCRSHORT_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeB, 32) => { + (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeB, 6) => { elf::R_SHARC_PCRSHORT_V3 } (RelocationKind::Absolute, RelocationEncoding::SharcAbs16Data, 16) => { elf::R_SHARC_ADDR_VAR16_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeA, 48) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeA, 16) => { elf::R_SHARC_DATA16_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeB, 32) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeB, 16) => { elf::R_SHARC_DATA16_VISA_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs24TypeA, 48) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs24TypeA, 24) => { elf::R_SHARC_ADDR24_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeA, 48) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeA, 6) => { elf::R_SHARC_DATA6_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeB, 32) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeB, 6) => { elf::R_SHARC_DATA6_VISA_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs7TypeB, 32) => { + (RelocationKind::Absolute, RelocationEncoding::SharcAbs7TypeB, 7) => { elf::R_SHARC_DATA7_VISA_V3 } (_, RelocationEncoding::Generic, _) => { From 45c7463e0e63238bf311b3736810b68bea135af6 Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Mon, 13 Nov 2023 18:23:20 +0000 Subject: [PATCH 5/6] elf: sharc: condense new RelocationEncoding variants As suggested by @philipc. Combined with the previous commit's change to the meaning of `size` for these relocations, there is no longer any ambiguity when converting between the 3-tuple and Rel::r_type constants. --- src/common.rs | 72 +++++++++++++------------------------- src/elf.rs | 4 +++ src/read/elf/relocation.rs | 24 ++++++------- src/write/elf/object.rs | 24 ++++++------- 4 files changed, 52 insertions(+), 72 deletions(-) diff --git a/src/common.rs b/src/common.rs index b1eddd61..37ccb4b9 100644 --- a/src/common.rs +++ b/src/common.rs @@ -369,54 +369,30 @@ pub enum RelocationEncoding { /// /// The `RelocationKind` must be PC relative. LoongArchBranch, - - /// SHARC+ 24-bit absolute address in a Type A instruction - /// - /// Used with `RelocationKind::Absolute`. - /// See [elf::R_SHARC_ADDR24_v3] - SharcAbs24TypeA, - - /// SHARC+ 32-bit absolute address in a Type A instruction - /// - /// Used with `RelocationKind::Absolute`. - /// See [elf::R_SHARC_ADDR32_v3] - SharcAbs32TypeA, - - /// SHARC+ 32-bit absolute address in a 32-bit STT_OBJECT location - /// - /// See [elf::R_SHARC_ADDRVAR_V3] - SharcAbs32Data, - - /// SHARC+ 6-bit relative address in a Type A instruction - /// - /// The `RelocationKind` must be PC relative. - SharcPcr6TypeA, - - /// SHARC+ 24-bit relative address in a Type A instruction - /// - /// The `RelocationKind` must be PC relative. - SharcPcr24TypeA, - - /// SHARC+ 6-bit absolute address in the immediate value field of a Type A instruction - SharcAbs6TypeA, - - /// SHARC+ 16-bit absolute address in the immediate value field of a Type A instruction - SharcAbs16TypeA, - - /// SHARC+ 6-bit absolute address in the immediate value field of a Type B instruction - SharcAbs6TypeB, - - /// SHARC+ 7-bit absolute address in the immediate value field of a Type B instruction - SharcAbs7TypeB, - - /// SHARC+ 16-bit absolute address in a Type B instruction - SharcAbs16TypeB, - - /// SHARC+ 6-bit relative address in a Type B instruction - SharcPcr6TypeB, - - /// SHARC+ 16-bit absolute address in a 16-bit STT_OBJECT location - SharcAbs16Data, + + /// SHARC+ 48-bit Type A instruction + /// + /// Represents these possible variants, each with a corresponding + /// `R_SHARC_*` constant: + /// + /// * 24-bit absolute address + /// * 32-bit absolute address + /// * 6-bit relative address + /// * 24-bit relative address + /// * 6-bit absolute address in the immediate value field + /// * 16-bit absolute address in the immediate value field + SharcTypeA, + + /// SHARC+ 32-bit Type B instruction + /// + /// Represents these possible variants, each with a corresponding + /// `R_SHARC_*` constant: + /// + /// * 6-bit absolute address in the immediate value field + /// * 7-bit absolute address in the immediate value field + /// * 16-bit absolute address + /// * 6-bit relative address + SharcTypeB, } /// File flags that are specific to each file format. diff --git a/src/elf.rs b/src/elf.rs index 16408fd4..87cc499d 100644 --- a/src/elf.rs +++ b/src/elf.rs @@ -2232,6 +2232,8 @@ pub const R_SHARC_ADDR24_V3: u32 = 0x0b; pub const R_SHARC_ADDR32_V3: u32 = 0x0c; /// 32-bit absolute address in bits 31:0 of a 32-bit data location +/// +/// Represented with `RelocationEncoding::Generic` pub const R_SHARC_ADDR_VAR_V3: u32 = 0x0d; /// 6-bit PC-relative address in bits 32:27 of a 48-bit instr @@ -2289,6 +2291,8 @@ pub const R_SHARC_DATA16_VISA_V3: u32 = 0x14; pub const R_SHARC_PCR6_VISA_V3: u32 = 0x17; /// 16-bit absolute address into bits 15:0 of a 16-bit location. +/// +/// Represented with `RelocationEncoding::Generic` pub const R_SHARC_ADDR_VAR16_V3: u32 = 0x19; pub const R_SHARC_CALC_PUSH_ADDR: u32 = 0xe0; diff --git a/src/read/elf/relocation.rs b/src/read/elf/relocation.rs index 4ef2e88d..a337218d 100644 --- a/src/read/elf/relocation.rs +++ b/src/read/elf/relocation.rs @@ -406,51 +406,51 @@ fn parse_relocation( }, elf::EM_SHARC => match reloc.r_type(endian, false) { elf::R_SHARC_ADDR24_V3 => { - encoding = RelocationEncoding::SharcAbs24TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Absolute, 24) } elf::R_SHARC_ADDR32_V3 => { - encoding = RelocationEncoding::SharcAbs32TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Absolute, 32) } elf::R_SHARC_ADDR_VAR_V3 => { - encoding = RelocationEncoding::SharcAbs32Data; + encoding = RelocationEncoding::Generic; (RelocationKind::Absolute, 32) } elf::R_SHARC_PCRSHORT_V3 => { - encoding = RelocationEncoding::SharcPcr6TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Relative, 6) } elf::R_SHARC_PCRLONG_V3 => { - encoding = RelocationEncoding::SharcPcr24TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Relative, 24) } elf::R_SHARC_DATA6_V3 => { - encoding = RelocationEncoding::SharcAbs6TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Absolute, 6) } elf::R_SHARC_DATA16_V3 => { - encoding = RelocationEncoding::SharcAbs16TypeA; + encoding = RelocationEncoding::SharcTypeA; (RelocationKind::Absolute, 16) } elf::R_SHARC_DATA6_VISA_V3 => { - encoding = RelocationEncoding::SharcAbs6TypeB; + encoding = RelocationEncoding::SharcTypeB; (RelocationKind::Absolute, 6) } elf::R_SHARC_DATA7_VISA_V3 => { - encoding = RelocationEncoding::SharcAbs7TypeB; + encoding = RelocationEncoding::SharcTypeB; (RelocationKind::Absolute, 7) } elf::R_SHARC_DATA16_VISA_V3 => { - encoding = RelocationEncoding::SharcAbs16TypeB; + encoding = RelocationEncoding::SharcTypeB; (RelocationKind::Absolute, 16) } elf::R_SHARC_PCR6_VISA_V3 => { - encoding = RelocationEncoding::SharcPcr6TypeB; + encoding = RelocationEncoding::SharcTypeB; (RelocationKind::Relative, 16) } elf::R_SHARC_ADDR_VAR16_V3 => { - encoding = RelocationEncoding::SharcAbs16Data; + encoding = RelocationEncoding::Generic; (RelocationKind::Absolute, 16) } r_type => (RelocationKind::Elf(r_type), 0), diff --git a/src/write/elf/object.rs b/src/write/elf/object.rs index d9102847..ceefd91e 100644 --- a/src/write/elf/object.rs +++ b/src/write/elf/object.rs @@ -769,40 +769,40 @@ impl<'a> Object<'a> { } }, Architecture::Sharc => match (reloc.kind, reloc.encoding, reloc.size) { - (RelocationKind::Absolute, RelocationEncoding::SharcAbs32TypeA, 32) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeA, 32) => { elf::R_SHARC_ADDR32_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs32Data, 32) => { + (RelocationKind::Absolute, RelocationEncoding::Generic, 32) => { elf::R_SHARC_ADDR_VAR_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr24TypeA, 24) => { + (RelocationKind::Relative, RelocationEncoding::SharcTypeA, 24) => { elf::R_SHARC_PCRLONG_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeA, 6) => { + (RelocationKind::Relative, RelocationEncoding::SharcTypeA, 6) => { elf::R_SHARC_PCRSHORT_V3 } - (RelocationKind::Relative, RelocationEncoding::SharcPcr6TypeB, 6) => { + (RelocationKind::Relative, RelocationEncoding::SharcTypeB, 6) => { elf::R_SHARC_PCRSHORT_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs16Data, 16) => { + (RelocationKind::Absolute, RelocationEncoding::Generic, 16) => { elf::R_SHARC_ADDR_VAR16_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeA, 16) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeA, 16) => { elf::R_SHARC_DATA16_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs16TypeB, 16) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeB, 16) => { elf::R_SHARC_DATA16_VISA_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs24TypeA, 24) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeA, 24) => { elf::R_SHARC_ADDR24_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeA, 6) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeA, 6) => { elf::R_SHARC_DATA6_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs6TypeB, 6) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeB, 6) => { elf::R_SHARC_DATA6_VISA_V3 } - (RelocationKind::Absolute, RelocationEncoding::SharcAbs7TypeB, 7) => { + (RelocationKind::Absolute, RelocationEncoding::SharcTypeB, 7) => { elf::R_SHARC_DATA7_VISA_V3 } (_, RelocationEncoding::Generic, _) => { From 75d90347363a4ca0ddc6b73e64168578db410be2 Mon Sep 17 00:00:00 2001 From: Josh Channings Date: Wed, 29 Nov 2023 12:44:22 +0000 Subject: [PATCH 6/6] elf: sharc: Remove specific generic encoding error As discussed in PR #593 The `_` pattern will take these matches now, so the result is still an Error, just with a (probably) more truthful message. --- src/write/elf/object.rs | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/write/elf/object.rs b/src/write/elf/object.rs index ceefd91e..c0ad3252 100644 --- a/src/write/elf/object.rs +++ b/src/write/elf/object.rs @@ -805,11 +805,6 @@ impl<'a> Object<'a> { (RelocationKind::Absolute, RelocationEncoding::SharcTypeB, 7) => { elf::R_SHARC_DATA7_VISA_V3 } - (_, RelocationEncoding::Generic, _) => { - return Err(Error(format!( - "SHARC+ ISA does not have a generic relocation encoding" - ))); - } (RelocationKind::Elf(x), _, _) => x, _ => { return Err(Error(format!("unimplemented relocation {:?}", reloc)));