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Enable Verilog lexer

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1 parent e04df8d commit c6896d633849240ae9f4fef3fa111379419c2988 @josh josh committed Sep 26, 2011
Showing with 1 addition and 1 deletion.
  1. +1 −1 lib/linguist/languages.yml
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2 lib/linguist/languages.yml
@@ -969,7 +969,7 @@ Vala:
Verilog:
type: programming
- lexer: Text only
+ lexer: verilog
extensions:
- .v

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