Permalink
Browse files

ukern: move cpu to machine independent part

  • Loading branch information...
glguida committed Dec 4, 2017
1 parent c19be2e commit 8b05be65116bf5c69d20494f18e40b7e9d0ecae5
@@ -5,9 +5,9 @@ include $(SRCROOT)/mk/mk.conf
INCS= ukparam.h
INCDIR= machine/uk
UKINCS= ansi.h asm.h cdefs.h cpu.h i386.h int_types.h apic.h \
machdep.h pae.h param.h platform.h pmap.h types.h ukparam.h \
vmparam.h tlb.h
UKINCS= ansi.h asm.h cdefs.h pcpu.h i386.h int_types.h ioapic.h \
lapic.h machdep.h pae.h param.h platform.h pmap.h types.h \
ukparam.h vmparam.h tlb.h
UKINCDIR= machine/uk
include $(MAKEDIR)/inc.mk
@@ -2,7 +2,7 @@
TMP= boot.S $(SRCS)
SRCS:= $(TMP)
SRCS+= biosops.S idt.S text.S locks.S pae.S
SRCS+= cpu.c apic.c sysboot.c tlb.c pci.c hpet.c
SRCS+= ioapic.c lapic.c sysboot.c tlb.c pci.c hpet.c
# Used by MI part.
SRCS+= pmap.c machdep.c
@@ -219,8 +219,8 @@ ENTRY(_fixup_gdt)
ret
END(_fixup_gdt)
.globl _C_LABEL(_load_segs)
_C_LABEL(_load_segs):
.globl _C_LABEL(_set_tss)
_C_LABEL(_set_tss):
push %ebp
mov %esp, %ebp
/* TSS (5 + 2*n) */
@@ -241,6 +241,13 @@ _C_LABEL(_load_segs):
add $5, %eax
shl $3, %eax
ltr %ax
pop %ebp
ret
.globl _C_LABEL(_set_fs)
_C_LABEL(_set_fs):
push %ebp
mov %esp, %ebp
/* FS (5 + 2*n + 1)*/
mov 8(%ebp), %ecx
mov %ecx, %eax
@@ -249,7 +256,7 @@ _C_LABEL(_load_segs):
movl $0, (%eax)
movl $0, 4(%eax)
movw $4, (%eax)
movl 0x10(%ebp), %ecx
movl 0xc(%ebp), %ecx
movw %cx, 2(%eax)
shr $16, %ecx
movb %cl, 4(%eax)
@@ -34,7 +34,7 @@
#include <uk/kern.h>
#include <machine/uk/machdep.h>
#include "apic.h"
#include "ioapic.h"
#include "i386.h"
/* ACPICA includes */
@@ -29,7 +29,6 @@
#include <machine/uk/asm.h>
#include <machine/uk/param.h>
#include <machine/uk/cpu.h>
.altmacro
.macro _do_entry vct
@@ -45,7 +44,7 @@
mov $KDS, %ax
mov %ax, %ds
mov %ax, %es
call _C_LABEL(cpu_number_from_lapic)
call _C_LABEL(lapic_getcurrent)
shl $4, %ax
add $(6 << 3), %ax
mov %ax, %fs
@@ -31,117 +31,35 @@
#include <uk/logio.h>
#include <uk/heap.h>
#include <uk/vmap.h>
#include <uk/assert.h>
#include "i386.h"
#include "apic.h"
#include <machine/uk/cpu.h>
#include <machine/uk/apic.h>
#include <machine/uk/param.h>
void *lapic_base = NULL;
unsigned lapics_no;
struct lapic_desc {
unsigned physid;
unsigned platformid;
uint32_t lint[2];
} *lapics;
#include "ioapic.h"
#include "param.h"
unsigned ioapics_no;
struct ioapic_desc {
void *base;
unsigned irq;
unsigned pins;
unsigned irq;
unsigned pins;
} *ioapics;
unsigned gsis_no;
struct gsi_desc {
unsigned irq;
enum gsimode mode;
unsigned ioapic;
unsigned pin;
unsigned irq;
enum gsimode mode;
unsigned ioapic;
unsigned pin;
} *gsis;
/* Memory Registers */
#define IO_REGSEL 0x00
#define IO_WIN 0x10
/* I/O Registers */
#define IO_ID 0x00
#define IO_VER 0x01
#define IO_ARB 0x02
#define IO_RED_LO(x) (0x10 + 2*(x))
#define IO_RED_HI(x) (0x11 + 2*(x))
void lapic_init(paddr_t base, unsigned no)
{
lapic_base = kvmap(base, LAPIC_SIZE);
lapics = heap_alloc(sizeof(struct lapic_desc) * no);
lapics_no = no;
dprintf("LAPIC PA: %08llx VA: %p\n", base, lapic_base);
}
void lapic_add(uint16_t physid, uint16_t plid)
{
static unsigned i = 0;
lapics[i].physid = physid;
lapics[i].platformid = plid;
lapics[i].lint[0] = 0x10000;
lapics[i].lint[1] = 0x10000;
i++;
}
void lapic_add_nmi(uint8_t pid, int l)
{
int i;
if (pid == 0xff) {
for (i = 0; i < lapics_no; i++)
lapics[i].lint[l] =
(1L << 16) | (APIC_DLVR_NMI << 8);
return;
}
for (i = 0; i < lapics_no; i++) {
if (lapics[i].platformid == pid) {
if (l)
l = 1;
lapics[i].lint[l] = (APIC_DLVR_NMI << 8);
return;
}
}
printf("Warning: LAPIC NMI for non-existing platform ID %d\n",
pid);
}
void lapic_configure(void)
{
unsigned i, physid = lapic_getcurrent();
struct lapic_desc *d = NULL;
for (i = 0; i < lapics_no; i++) {
if (lapics[i].physid == physid)
d = lapics + i;
}
if (d == NULL) {
printf("Warning: Current CPU not in Platform Tables!\n");
/* Try to continue, ignore the NMI configuration */
} else {
lapic_write(L_LVT_LINT(0), d->lint[0]);
lapic_write(L_LVT_LINT(1), d->lint[1]);
}
/* Enable LAPIC */
lapic_write(L_MISC, lapic_read(L_MISC) | 0x100);
}
void lapic_platform_done(void)
{
int i;
for (i = 0; i < lapics_no; i++)
cpu_add(lapics[i].physid, lapics[i].platformid);
/* Since we're here, configure LAPIC of BSP */
lapic_configure();
}
#define IO_ID 0x00
#define IO_VER 0x01
#define IO_ARB 0x02
#define IO_RED_LO(x) (0x10 + 2*(x))
#define IO_RED_HI(x) (0x11 + 2*(x))
void ioapic_init(unsigned no)
{
@@ -30,87 +30,6 @@
#ifndef _i386_apic_h
#define _i386_apic_h
#define APIC_DLVR_FIX 0
#define APIC_DLVR_PRIO 1
#define APIC_DLVR_SMI 2
#define APIC_DLVR_NMI 4
#define APIC_DLVR_INIT 5
#define APIC_DLVR_START 6
#define APIC_DLVR_EINT 7
/*
* Local APIC.
*/
/* LAPIC registers. */
#define L_IDREG 0x20
#define L_VER 0x30
#define L_TSKPRIO 0x80
#define L_ARBPRIO 0x90
#define L_PROCPRIO 0xa0
#define L_EOI 0xb0
#define L_LOGDEST 0xd0
#define L_DESTFMT 0xe0
#define L_MISC 0xf0 /* Spurious vector */
#define L_ISR 0x100 /* 256 bit */
#define L_TMR 0x180 /* 256 bit */
#define L_IRR 0x200 /* 256 bit */
#define L_ERR 0x280
#define L_ICR_LO 0x300
#define L_ICR_HI 0x310
#define L_LVT_TIMER 0x320
#define L_LVT_THERM 0x330
#define L_LVT_PFMCNT 0x340
#define L_LVT_LINT(x) (0x350 + (x * 0x10))
#define L_LVT_ERR 0x370
#define L_TMR_IC 0x380
#define L_TMR_CC 0x390
#define L_TMR_DIV 0x3e0
#define LAPIC_SIZE (1UL << 12)
extern void *lapic_base;
void lapic_init(paddr_t base, unsigned no);
void lapic_add(uint16_t physid, uint16_t plid);
void lapic_enable(void);
void lapic_configure(void);
static inline void lapic_write(unsigned reg, uint32_t data)
{
*((volatile uint32_t *) (lapic_base + reg)) = data;
}
static inline volatile uint32_t lapic_read(unsigned reg)
{
return *((volatile uint32_t *) (lapic_base + reg));
}
static inline void lapic_ipi(unsigned physid, uint8_t dlvr, uint8_t vct)
{
uint32_t hi, lo;
lo = 0x4000 | (dlvr & 0x7) << 8 | vct;
hi = (physid & 0xff) << 24;
lapic_write(L_ICR_HI, hi);
lapic_write(L_ICR_LO, lo);
}
static inline void lapic_ipi_broadcast(uint8_t dlvr, uint8_t vct)
{
uint32_t lo;
lo = (dlvr & 0x7) << 8 | vct
| /*ALLBUTSELF*/ 0xc0000 | /*ASSERT*/ 0x4000;
lapic_write(L_ICR_HI, 0);
lapic_write(L_ICR_LO, lo);
}
#define lapic_getcurrent(void) (lapic_read(L_IDREG) >> 24)
/*
* I/O APIC
*/
Oops, something went wrong.

0 comments on commit 8b05be6

Please sign in to comment.