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Adding reset glitch hack source code and explanations

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gligli committed Aug 28, 2011
1 parent d201f88 commit ecc2acaa7e83a85d18edd4da2860ef28e3db9714
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  1. +471 −0 reset_glitch_hack/build.py
  2. BIN reset_glitch_hack/cdxell/CD.tpl
  3. BIN reset_glitch_hack/cdxell/CDjasper.tpl
  4. +29 −0 reset_glitch_hack/cdxell/Makefile
  5. +182 −0 reset_glitch_hack/cdxell/cdxell.S
  6. +60 −0 reset_glitch_hack/cdxell/xenonsprs.h
  7. +18 −0 reset_glitch_hack/cpld/glitch48nofullpost/_pace.ucf
  8. +12 −0 reset_glitch_hack/cpld/glitch48nofullpost/_xmsgs/cpldfit.xmsgs
  9. +9 −0 reset_glitch_hack/cpld/glitch48nofullpost/_xmsgs/hprep6.xmsgs
  10. +9 −0 reset_glitch_hack/cpld/glitch48nofullpost/_xmsgs/taengine.xmsgs
  11. +9 −0 reset_glitch_hack/cpld/glitch48nofullpost/_xmsgs/tsim.xmsgs
  12. +2 −0 reset_glitch_hack/cpld/glitch48nofullpost/bench_beh.prj
  13. +28 −0 reset_glitch_hack/cpld/glitch48nofullpost/glitch48nofullpost.gise
  14. +202 −0 reset_glitch_hack/cpld/glitch48nofullpost/glitch48nofullpost.xise
  15. +113 −0 reset_glitch_hack/cpld/glitch48nofullpost/iseconfig/glitch.projectmgr
  16. +124 −0 reset_glitch_hack/cpld/glitch48nofullpost/iseconfig/glitch48.projectmgr
  17. +105 −0 reset_glitch_hack/cpld/glitch48nofullpost/iseconfig/glitch48nofullpost.projectmgr
  18. +216 −0 reset_glitch_hack/cpld/glitch48nofullpost/iseconfig/main.xreport
  19. +13 −0 reset_glitch_hack/cpld/glitch48nofullpost/isim.log
  20. +13 −0 reset_glitch_hack/cpld/glitch48nofullpost/main.ucf
  21. +94 −0 reset_glitch_hack/cpld/glitch48nofullpost/main.vhd
  22. +77 −0 reset_glitch_hack/cpld/glitch48nofullpost/main_summary.html
  23. +1 −0 reset_glitch_hack/cpld/glitch48nofullpost/pepExtractor.prj
  24. 0 reset_glitch_hack/cpld/glitch48nofullpost/tmperr.err
  25. +14 −0 reset_glitch_hack/cpld/glitchslimnodp/_pace.ucf
  26. +225 −0 reset_glitch_hack/cpld/glitchslimnodp/_xmsgs/cpldfit.xmsgs
  27. +9 −0 reset_glitch_hack/cpld/glitchslimnodp/_xmsgs/hprep6.xmsgs
  28. +9 −0 reset_glitch_hack/cpld/glitchslimnodp/_xmsgs/taengine.xmsgs
  29. +9 −0 reset_glitch_hack/cpld/glitchslimnodp/_xmsgs/tsim.xmsgs
  30. +28 −0 reset_glitch_hack/cpld/glitchslimnodp/glitchslim.gise
  31. +203 −0 reset_glitch_hack/cpld/glitchslimnodp/glitchslim.xise
  32. +113 −0 reset_glitch_hack/cpld/glitchslimnodp/iseconfig/glitch.projectmgr
  33. +124 −0 reset_glitch_hack/cpld/glitchslimnodp/iseconfig/glitch48.projectmgr
  34. +104 −0 reset_glitch_hack/cpld/glitchslimnodp/iseconfig/glitch48nofullpost.projectmgr
  35. +115 −0 reset_glitch_hack/cpld/glitchslimnodp/iseconfig/glitchslim.projectmgr
  36. +216 −0 reset_glitch_hack/cpld/glitchslimnodp/iseconfig/main.xreport
  37. +17 −0 reset_glitch_hack/cpld/glitchslimnodp/isim.log
  38. +15 −0 reset_glitch_hack/cpld/glitchslimnodp/main.ucf
  39. +137 −0 reset_glitch_hack/cpld/glitchslimnodp/main.vhd
  40. +77 −0 reset_glitch_hack/cpld/glitchslimnodp/main_summary.html
  41. +1 −0 reset_glitch_hack/cpld/glitchslimnodp/pepExtractor.prj
  42. 0 reset_glitch_hack/cpld/glitchslimnodp/tmperr.err
  43. +121 −0 reset_glitch_hack/reset_glitch_hack.txt
  44. BIN reset_glitch_hack/schematics/glitch48nofullpost.DSN
  45. BIN reset_glitch_hack/schematics/glitchslimnodp.DSN
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@@ -0,0 +1,29 @@
+CROSS=xenon-
+CC=$(CROSS)gcc
+OBJCOPY=$(CROSS)objcopy
+LD=$(CROSS)ld
+AS=$(CROSS)as
+STRIP=$(CROSS)strip
+
+# Configuration
+AFLAGS = -m64
+
+# Build rules
+all: CD CDjasper
+
+clean:
+ rm -rf cdxell.o cdxell.bin CD CDjasper
+
+.S.o:
+ $(CC) $(AFLAGS) -c -o $@ $*.S
+
+%.bin: %.o
+ $(OBJCOPY) -O binary $< $@
+
+CD: cdxell.bin
+ cp CD.tpl CD
+ dd bs=624 seek=1 if=cdxell.bin of=CD conv=notrunc
+
+CDjasper: cdxell.bin
+ cp CDjasper.tpl CDjasper
+ dd bs=624 seek=1 if=cdxell.bin of=CDjasper conv=notrunc
@@ -0,0 +1,182 @@
+#include "xenonsprs.h"
+
+.macro PATCH Address
+ .set Pc, \Address
+ .quad \Address
+ .long (9f-8f)/4 //Length of patch in words
+.endm
+
+_start:
+.globl _start
+
+bl init_regs
+
+/* POST = 0x10 */
+li %r3, 0x10
+rldicr %r3, %r3, 56, 7
+std %r3, 0(%r7)
+
+bl init_pci
+
+ /* send SMC query for powerup reason */
+stw %r9, 0x1084(%r8) /* 00000004 (byteswapped) */
+stw %r10, 0x1080(%r8) /* 01000000 */
+stw %r11, 0x1080(%r8) /* 00000000 */
+stw %r11, 0x1080(%r8) /* 00000000 */
+stw %r11, 0x1080(%r8) /* 00000000 */
+stw %r11, 0x1084(%r8) /* 00000000 */
+
+ /* wait for SMC answer */
+1:
+ lwz %r12, 0x1094(%r8)
+ and. %r12, %r12, %r9 /* check for 04 (swapped) */
+ beq 1b
+ stw %r9, 0x1094(%r8) /* 00000004 (byteswapped) */
+ lwz %r12, 0x1090(%r8)
+ lwz %r3, 0x1090(%r8)
+ lwz %r3, 0x1090(%r8)
+ lwz %r3, 0x1090(%r8)
+ stw %r11, 0x1094(%r8) /* 00000000 */
+ rlwinm %r3, %r12, 8, 24, 31
+ cmpwi %r3, 0x1
+ bne 1b
+
+ /* set HRMOR=0 for main core */
+mtspr hrmor,%r11
+
+/* POST = 0x11 */
+li %r3, 0x11
+rldicr %r3, %r3, 56, 7
+std %r3, 0(%r7)
+
+ /* Copy from Flash, src = %r5, dst = %r6 */
+
+rlwinm %r3, %r12, 16, 24, 31
+cmpwi %r3, 0x5a /* poweron by pressing guide button while connected to the back USB (lowest one on slim) */
+beq backup_xell
+cmpwi %r3, 0x24 /* poweron by pressing the windows button on the IR remote */
+beq backup_xell
+
+mr %r5,%r15
+
+backup_xell:
+
+mr %r9,%r6
+lis %r4, 1 /* 256k */
+mtctr %r4
+
+1: lwz %r8, 0(%r5) //Memcopy
+ stw %r8, 0(%r6)
+ dcbst %r0, %r6 //Flush cache to ram
+ icbi %r0, %r6
+ sync 0
+ isync
+ addi %r6, %r6, 4
+ addi %r5, %r5, 4
+ bdnz 1b
+
+/* POST = 0x12 */
+li %r3, 0x12
+rldicr %r3, %r3, 56, 7
+std %r3, 0(%r7)
+
+ /* Clear IR/DR and jump to Xell*/
+li %r4, 0x30
+mfmsr %r3
+andc %r3, %r3, %r4
+mtsrr1 %r3
+mtsrr0 %r9
+rfid
+
+init_regs:
+ /* init regs */
+ li %r5,0x200
+ oris %r5,%r5,0x8000
+ rldicr %r5,%r5,32,31
+ oris %r5,%r5,0xc80c
+
+ li %r15,0x200
+ oris %r15,%r15,0x8000
+ rldicr %r15,%r15,32,31
+ oris %r15,%r15,0xc810
+
+ lis %r6,0x8000
+ rldicr %r6,%r6,32,31
+ oris %r6,%r6,0x1c00
+
+ li %r7,0x200
+ oris %r7,%r7,0x8000
+ rldicr %r7,%r7,32,31
+ ori %r7,%r7,0x1010
+ oris %r7,%r7,6
+
+ li %r8,0x200
+ oris %r8,%r8,0x8000
+ rldicr %r8,%r8,32,31
+ oris %r8,%r8,0xea00
+
+ lis %r9,0x0400
+
+ lis %r10,0x0100
+
+ li %r11,0
+
+ lis %r20,0x8000
+ ori %r20,%r20,0x17c
+ rldicr %r20,%r20,32,31
+ oris %r20,%r20,0x400
+ ori %r20,%r20,0x270 /* offset to CD code start : 0x8000.017c.0400.0270 */
+
+ blr
+
+init_pci:
+ /* init PCI devices */
+ addi %r3,%r20,pci_inits-_start-4
+
+ li %r30,0x200
+ oris %r30,%r30,0x8000
+ rldicr %r30,%r30,32,31
+ pci_start:
+ lwzu %r4,4(%r3)
+ cmpwi %r4,-1
+ beqlr
+ lwzu %r31,4(%r3)
+ stwbrx %r31,%r30,%r4
+ li %r31,0xff
+ andc %r4,%r4,%r31
+ ori %r4,%r4,4
+ lwbrx %r31,%r30,%r4
+ lwzu %r29,4(%r3)
+ or %r31,%r31,%r29
+ stwbrx %r31,%r30,%r4
+ b pci_start
+
+pci_inits:
+/* pci-pci bridge */
+.long 0xd0000010,0xea000000,0x156
+/* host bridge */
+.long 0xd0008010,0xe0000000,2
+/* GPU */
+.long 0xd0010010,0xec800000,2
+/* 1414:5801 */
+.long 0xd0100010,0xea001800,2
+/* SATA */
+.long 0xd0108010,0xea001200,6
+.long 0xd0108014,0xea001220,6
+.long 0xd0110010,0xea001300,6
+.long 0xd0110014,0xea001320,6
+/* USB */
+.long 0xd0120010,0xea002000,0x156
+.long 0xd0121010,0xea003000,0x106
+.long 0xd0128010,0xea004000,0x156
+.long 0xd0129010,0xea005000,0x106
+/* Ethernet */
+.long 0xd0138010,0xea001400,6
+/* System flash controller */
+.long 0xd0140010,0xea00c000,6
+.long 0xd0140014,0xc8000000,6
+/* Audio */
+.long 0xd0148010,0xea001600,6
+/* SMC */
+.long 0xd0150010,0xea001000,2
+.long 0xffffffff /* structure end */
@@ -0,0 +1,60 @@
+#ifndef XENONSPRS_H_
+#define XENONSPRS_H_
+
+#endif /*XENONSPRS_H_*/
+#define esr 62
+#define ivpr 63
+#define pid 48
+#define ctrlrd 136
+#define ctrlwr 152
+#define pvr 287
+#define hsprg0 304
+#define hsprg1 305
+#define hdsisr 306
+#define hdar 307
+#define dbcr0 308
+#define dbcr1 309
+#define hdec 310
+#define hior 311
+#define rmor 312
+#define hrmor 313
+#define hsrr0 314
+#define hsrr1 315
+#define dac1 316
+#define dac2 317
+#define lpcr 318
+#define lpidr 319
+#define tsr 336
+#define tcr 340
+#define tsrl 896
+#define tsrr 897
+#define tscr 921
+#define ttr 922
+#define PpeTlbIndexHint 946
+#define PpeTlbIndex 947
+#define PpeTlbVpn 948
+#define PpeTlbRpn 949
+#define PpeTlbRmt 951
+#define dsr0 952
+#define drmr0 953
+#define dcidr0 954
+#define drsr1 955
+#define drmr1 956
+#define dcidr1 957
+#define issr0 976
+#define irmr0 977
+#define icidr0 978
+#define irsr1 979
+#define irmr1 980
+#define icidr1 981
+#define hid0 1008
+#define hid1 1009
+#define hid4 1012
+#define iabr 1010
+#define dabr 1013
+#define dabrx 1015
+#define buscsr 1016
+#define hid6 1017
+#define l2sr 1018
+#define BpVr 1022
+#define pir 1023
@@ -0,0 +1,18 @@
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "CLK" LOC = "P29" | IOSTANDARD = LVCMOS33 ;
+NET "CPU_PLL_BYPASS" LOC = "P22" | IOSTANDARD = LVCMOS33 ;
+NET "CPU_RESET" LOC = "P8" | IOSTANDARD = LVCMOS15 | SCHMITT_TRIGGER ;
+NET "POSTBIT" LOC = "P40" | IOSTANDARD = LVCMOS15 | SCHMITT_TRIGGER ;
+NET "TEST<0>" LOC = "P18" | IOSTANDARD = LVCMOS33 ;
+NET "TEST<1>" LOC = "P19" | IOSTANDARD = LVCMOS33 ;
+NET "TEST<2>" LOC = "P20" | IOSTANDARD = LVCMOS33 ;
+NET "TEST<3>" LOC = "P21" | IOSTANDARD = LVCMOS33 ;
+NET "TEST<4>" LOC = "P23" | IOSTANDARD = LVCMOS33 ;
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+<msg type="warning" file="Cpld" num="0" delta="new" >Unable to retrieve the path to the iSE Project Repository. Will use the default filename of &apos;<arg fmt="%s" index="1">main.ise</arg>&apos;.
+</msg>
+
+</messages>
+
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+</messages>
+
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+</messages>
+
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+ by the Xilinx ISE software. Any direct editing or
+ changes made to this file may result in unpredictable
+ behavior or data corruption. It is strongly advised that
+ users do not edit the contents of this file. -->
+<messages>
+</messages>
+
@@ -0,0 +1,2 @@
+vhdl work "main.vhd"
+vhdl work "bench.vhd"
@@ -0,0 +1,28 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="glitch48nofullpost.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
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