diff --git a/snippets/verilog-mode/interface b/snippets/verilog-mode/interface
index 7d2e0a0..8149b46 100644
--- a/snippets/verilog-mode/interface
+++ b/snippets/verilog-mode/interface
@@ -2,7 +2,7 @@
 # key: itf
 # --
 
-interface ${1:name} ${2:# (parameter WIDTH = 0)} (${3:input logic Clk, input logick Rst_n});
+interface ${1:name} ${2:# (parameter WIDTH = 0)} (${3:input logic Clk, input logic Rst_n});
 
     // Itf signals
     // logic Request;