From d3ba43c22750afc750d2a2101e40882bd109e0c6 Mon Sep 17 00:00:00 2001 From: Gonzalo Larumbe Date: Mon, 7 Jul 2025 20:13:43 +0200 Subject: [PATCH] Replace outshine dependency with builtin outline for hierarchy --- ...tshine.sv => axi_demux.builtin.outline.sv} | 2 +- ...ine.sv => axi_demux.mm.builtin.outline.sv} | 2 +- ...outshine.sv => axi_demux.mm.ts.outline.sv} | 2 +- ...ts.outshine.sv => axi_demux.ts.outline.sv} | 2 +- ...tshine.sv => instances.builtin.outline.sv} | 10 +- ...in.outshine.sv => instances.ts.outline.sv} | 2 +- ...outshine.sv => instances.vhier.outline.sv} | 10 +- ...hine.sv => ucontroller.builtin.outline.sv} | 2 +- ....outshine.sv => ucontroller.ts.outline.sv} | 2 +- ...tshine.sv => ucontroller.vhier.outline.sv} | 2 +- test/src/verilog-ext-test-hierarchy.el | 100 +++++++++--------- test/src/verilog-ext-test-setup-package.el | 2 +- test/src/verilog-ext-test-setup-straight.el | 2 +- verilog-ext-hierarchy.el | 86 ++++++--------- verilog-ext-utils.el | 2 +- verilog-ext.el | 2 +- 16 files changed, 107 insertions(+), 123 deletions(-) rename test/ref/hierarchy/{axi_demux.builtin.outshine.sv => axi_demux.builtin.outline.sv} (89%) rename test/ref/hierarchy/{axi_demux.mm.builtin.outshine.sv => axi_demux.mm.builtin.outline.sv} (90%) rename test/ref/hierarchy/{axi_demux.mm.ts.outshine.sv => axi_demux.mm.ts.outline.sv} (90%) rename test/ref/hierarchy/{axi_demux.ts.outshine.sv => axi_demux.ts.outline.sv} (89%) rename test/ref/hierarchy/{instances.vhier.outshine.sv => instances.builtin.outline.sv} (85%) rename test/ref/hierarchy/{instances.builtin.outshine.sv => instances.ts.outline.sv} (85%) rename test/ref/hierarchy/{instances.ts.outshine.sv => instances.vhier.outline.sv} (85%) rename test/ref/hierarchy/{ucontroller.builtin.outshine.sv => ucontroller.builtin.outline.sv} (90%) rename test/ref/hierarchy/{ucontroller.ts.outshine.sv => ucontroller.ts.outline.sv} (90%) rename test/ref/hierarchy/{ucontroller.vhier.outshine.sv => ucontroller.vhier.outline.sv} (91%) diff --git a/test/ref/hierarchy/axi_demux.builtin.outshine.sv b/test/ref/hierarchy/axi_demux.builtin.outline.sv similarity index 89% rename from test/ref/hierarchy/axi_demux.builtin.outshine.sv rename to test/ref/hierarchy/axi_demux.builtin.outline.sv index 7bc759e..cdca3c7 100644 --- a/test/ref/hierarchy/axi_demux.builtin.outshine.sv +++ b/test/ref/hierarchy/axi_demux.builtin.outline.sv @@ -21,5 +21,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/axi_demux.mm.builtin.outshine.sv b/test/ref/hierarchy/axi_demux.mm.builtin.outline.sv similarity index 90% rename from test/ref/hierarchy/axi_demux.mm.builtin.outshine.sv rename to test/ref/hierarchy/axi_demux.mm.builtin.outline.sv index e30465a..2bd1488 100644 --- a/test/ref/hierarchy/axi_demux.mm.builtin.outshine.sv +++ b/test/ref/hierarchy/axi_demux.mm.builtin.outline.sv @@ -22,5 +22,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/axi_demux.mm.ts.outshine.sv b/test/ref/hierarchy/axi_demux.mm.ts.outline.sv similarity index 90% rename from test/ref/hierarchy/axi_demux.mm.ts.outshine.sv rename to test/ref/hierarchy/axi_demux.mm.ts.outline.sv index e30465a..2bd1488 100644 --- a/test/ref/hierarchy/axi_demux.mm.ts.outshine.sv +++ b/test/ref/hierarchy/axi_demux.mm.ts.outline.sv @@ -22,5 +22,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/axi_demux.ts.outshine.sv b/test/ref/hierarchy/axi_demux.ts.outline.sv similarity index 89% rename from test/ref/hierarchy/axi_demux.ts.outshine.sv rename to test/ref/hierarchy/axi_demux.ts.outline.sv index 7bc759e..cdca3c7 100644 --- a/test/ref/hierarchy/axi_demux.ts.outshine.sv +++ b/test/ref/hierarchy/axi_demux.ts.outline.sv @@ -21,5 +21,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/instances.vhier.outshine.sv b/test/ref/hierarchy/instances.builtin.outline.sv similarity index 85% rename from test/ref/hierarchy/instances.vhier.outshine.sv rename to test/ref/hierarchy/instances.builtin.outline.sv index 0398721..e3c6010 100644 --- a/test/ref/hierarchy/instances.vhier.outshine.sv +++ b/test/ref/hierarchy/instances.builtin.outline.sv @@ -1,20 +1,20 @@ // Hierarchy generated by `verilog-ext' // * instances -// ** test_if_params -// ** test_if_params_array // ** block0 // ** block1 // ** block2 // ** block3 // ** block_gen -// ** block_ws_0 -// ** block_ws_1 // ** test_if +// ** test_if_params +// ** test_if_params_array // ** test_if_params_empty +// ** block_ws_0 +// ** block_ws_1 // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/instances.builtin.outshine.sv b/test/ref/hierarchy/instances.ts.outline.sv similarity index 85% rename from test/ref/hierarchy/instances.builtin.outshine.sv rename to test/ref/hierarchy/instances.ts.outline.sv index 6c868cb..e3c6010 100644 --- a/test/ref/hierarchy/instances.builtin.outshine.sv +++ b/test/ref/hierarchy/instances.ts.outline.sv @@ -16,5 +16,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/instances.ts.outshine.sv b/test/ref/hierarchy/instances.vhier.outline.sv similarity index 85% rename from test/ref/hierarchy/instances.ts.outshine.sv rename to test/ref/hierarchy/instances.vhier.outline.sv index 6c868cb..570004f 100644 --- a/test/ref/hierarchy/instances.ts.outshine.sv +++ b/test/ref/hierarchy/instances.vhier.outline.sv @@ -1,20 +1,20 @@ // Hierarchy generated by `verilog-ext' // * instances +// ** test_if_params +// ** test_if_params_array // ** block0 // ** block1 // ** block2 // ** block3 // ** block_gen -// ** test_if -// ** test_if_params -// ** test_if_params_array -// ** test_if_params_empty // ** block_ws_0 // ** block_ws_1 +// ** test_if +// ** test_if_params_empty // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/ucontroller.builtin.outshine.sv b/test/ref/hierarchy/ucontroller.builtin.outline.sv similarity index 90% rename from test/ref/hierarchy/ucontroller.builtin.outshine.sv rename to test/ref/hierarchy/ucontroller.builtin.outline.sv index 15f8a20..9271971 100644 --- a/test/ref/hierarchy/ucontroller.builtin.outshine.sv +++ b/test/ref/hierarchy/ucontroller.builtin.outline.sv @@ -26,5 +26,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/ucontroller.ts.outshine.sv b/test/ref/hierarchy/ucontroller.ts.outline.sv similarity index 90% rename from test/ref/hierarchy/ucontroller.ts.outshine.sv rename to test/ref/hierarchy/ucontroller.ts.outline.sv index 2d8bb59..b1a4425 100644 --- a/test/ref/hierarchy/ucontroller.ts.outshine.sv +++ b/test/ref/hierarchy/ucontroller.ts.outline.sv @@ -27,5 +27,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/ref/hierarchy/ucontroller.vhier.outshine.sv b/test/ref/hierarchy/ucontroller.vhier.outline.sv similarity index 91% rename from test/ref/hierarchy/ucontroller.vhier.outshine.sv rename to test/ref/hierarchy/ucontroller.vhier.outline.sv index d58040b..d78fd93 100644 --- a/test/ref/hierarchy/ucontroller.vhier.outshine.sv +++ b/test/ref/hierarchy/ucontroller.vhier.outline.sv @@ -25,5 +25,5 @@ // * Buffer local variables // Local Variables: -// eval: (verilog-ext-hierarchy-outshine-nav-mode) +// eval: (verilog-ext-hierarchy-outline-nav-mode) // End: diff --git a/test/src/verilog-ext-test-hierarchy.el b/test/src/verilog-ext-test-hierarchy.el index 153c336..21f8ad5 100644 --- a/test/src/verilog-ext-test-hierarchy.el +++ b/test/src/verilog-ext-test-hierarchy.el @@ -57,7 +57,7 @@ (hierarchy-print hier (lambda (node) node)) (buffer-substring-no-properties (point-min) (point-max))))) -(defun verilog-ext-test-hierarchy--outshine-fn () +(defun verilog-ext-test-hierarchy--outline-fn () (verilog-ext-hierarchy-current-buffer) (buffer-substring-no-properties (point-min) (point-max))) @@ -86,11 +86,11 @@ ;; INFO: This one seems important to have a clear state on each file parsed. (verilog-ext-hierarchy-clear-cache) (funcall mode) - (cond (;; vhier-outshine + (cond (;; vhier-outline ;; - vhier cannot use temp-buffer since executes a command that requires a filename as an argument (and (eq backend 'vhier) - (eq frontend 'outshine)) - (verilog-ext-test-hierarchy--outshine-fn)) + (eq frontend 'outline)) + (verilog-ext-test-hierarchy--outline-fn)) ;; vhier-hierarchy ;; - vhier cannot use temp-buffer since executes a command that requires a filename as an argument ((and (eq backend 'vhier) @@ -101,21 +101,21 @@ (eq frontend 'hierarchy)) (verilog-ext-hierarchy-parse) (verilog-ext-test-hierarchy--hierarchy-fn)) - ;; builtin-outshine + ;; builtin-outline ((and (eq backend 'builtin) - (eq frontend 'outshine)) + (eq frontend 'outline)) (verilog-ext-hierarchy-parse) - (verilog-ext-test-hierarchy--outshine-fn)) + (verilog-ext-test-hierarchy--outline-fn)) ;; tree-sitter-hierarchy ((and (eq backend 'tree-sitter) (eq frontend 'hierarchy)) (verilog-ext-hierarchy-parse) (verilog-ext-test-hierarchy--hierarchy-fn)) - ;; tree-sitter-outshine + ;; tree-sitter-outline ((and (eq backend 'tree-sitter) - (eq frontend 'outshine)) + (eq frontend 'outline)) (verilog-ext-hierarchy-parse) - (verilog-ext-test-hierarchy--outshine-fn)) + (verilog-ext-test-hierarchy--outline-fn)) ;; Fallback (t (error "Not a proper backend-frontend combination!"))))))) @@ -150,16 +150,16 @@ :files (,(file-name-concat verilog-ext-test-ucontroller-rtl-dir "global_pkg.sv") ,@verilog-ext-test-hierarchy-ucontroller-file-list) :lib-search-path ,verilog-ext-test-hierarchy-vhier-lib-search-path))) - ;; vhier-outshine + ;; vhier-outline (let ((file (file-name-concat verilog-ext-test-files-common-dir "instances.sv"))) (test-hdl-gen-expected-files :file-list `(,file) :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "vhier.outshine.sv" + :out-file-ext "vhier.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend vhier - :frontend outshine + :frontend outline :root ,verilog-ext-test-files-common-dir :files (,file) :lib-search-path ,verilog-ext-test-hierarchy-vhier-lib-search-path))) @@ -168,12 +168,12 @@ (let ((file (file-name-concat verilog-ext-test-ucontroller-rtl-dir "ucontroller.sv"))) (test-hdl-gen-expected-files :file-list `(,file) :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "vhier.outshine.sv" + :out-file-ext "vhier.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend vhier - :frontend outshine + :frontend outline :root ,verilog-ext-test-ucontroller-rtl-dir :files (,(file-name-concat verilog-ext-test-ucontroller-rtl-dir "global_pkg.sv") ,@verilog-ext-test-hierarchy-ucontroller-file-list) @@ -188,15 +188,15 @@ :backend builtin :frontend hierarchy :files ,verilog-ext-test-hierarchy-sources-list)) - ;; builtin-outshine + ;; builtin-outline (test-hdl-gen-expected-files :file-list verilog-ext-test-hierarchy-file-list :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "builtin.outshine.sv" + :out-file-ext "builtin.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend builtin - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list)) ;; tree-sitter-hierarchy (test-hdl-gen-expected-files :file-list verilog-ext-test-hierarchy-file-list @@ -208,15 +208,15 @@ :backend tree-sitter :frontend hierarchy :files ,verilog-ext-test-hierarchy-sources-list)) - ;; tree-sitter-outshine + ;; tree-sitter-outline (test-hdl-gen-expected-files :file-list verilog-ext-test-hierarchy-file-list :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "ts.outshine.sv" + :out-file-ext "ts.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-ts-mode :backend tree-sitter - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list)) ;; More custom ones (e.g. need to explicit module to be parsed from a file with multiple modules declared) ;; - axi_demux / builtin-hierarchy @@ -230,15 +230,15 @@ :frontend hierarchy :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf")) - ;; - axi_demux / builtin-outshine + ;; - axi_demux / builtin-outline (test-hdl-gen-expected-files :file-list `(,(file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv")) :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "mm.builtin.outshine.sv" + :out-file-ext "mm.builtin.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend builtin - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf")) ;; - axi_demux / tree-sitter-hierarchy @@ -252,15 +252,15 @@ :frontend hierarchy :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf")) - ;; - axi_demux / tree-sitter-outshine + ;; - axi_demux / tree-sitter-outline (test-hdl-gen-expected-files :file-list `(,(file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv")) :dest-dir verilog-ext-test-ref-dir-hierarchy - :out-file-ext "mm.ts.outshine.sv" + :out-file-ext "mm.ts.outline.sv" :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-ts-mode :backend tree-sitter - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf"))) @@ -297,38 +297,38 @@ )) (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "vhier.hier.el")))))) -(ert-deftest hierarchy::vhier-outshine () +(ert-deftest hierarchy::vhier-outline () ;; instances.sv (let ((file (file-name-concat verilog-ext-test-files-common-dir "instances.sv"))) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "vhier.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "vhier.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend vhier - :frontend outshine + :frontend outline :root ,verilog-ext-test-files-common-dir :files (,file) :lib-search-path ,verilog-ext-test-hierarchy-vhier-lib-search-path )) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "vhier.outshine.sv"))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "vhier.outline.sv"))))) ;; ucontroller.sv ;; INFO: For some reason, the one ucontroller.sv in `verilog-ext-test-files-common-dir ;; had the package line removed and didn't work as expected (let ((file (file-name-concat verilog-ext-test-ucontroller-rtl-dir "ucontroller.sv"))) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "vhier.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "vhier.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend vhier - :frontend outshine + :frontend outline :root ,verilog-ext-test-ucontroller-rtl-dir :files (,(file-name-concat verilog-ext-test-ucontroller-rtl-dir "global_pkg.sv") ,@verilog-ext-test-hierarchy-ucontroller-file-list) :lib-search-path ,verilog-ext-test-hierarchy-vhier-lib-search-path )) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "vhier.outshine.sv")))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "vhier.outline.sv")))))) (ert-deftest hierarchy::builtin-hierarchy () (dolist (file verilog-ext-test-hierarchy-file-list) @@ -342,17 +342,17 @@ :files ,verilog-ext-test-hierarchy-sources-list)) (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "builtin.hier.el")))))) -(ert-deftest hierarchy::builtin-outshine () +(ert-deftest hierarchy::builtin-outline () (dolist (file verilog-ext-test-hierarchy-file-list) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "builtin.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "builtin.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend builtin - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list)) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "builtin.outshine.sv")))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "builtin.outline.sv")))))) (ert-deftest hierarchy::tree-sitter-hierarchy () (dolist (file verilog-ext-test-hierarchy-file-list) @@ -366,17 +366,17 @@ :files ,verilog-ext-test-hierarchy-sources-list)) (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "ts.hier.el")))))) -(ert-deftest hierarchy::tree-sitter-outshine () +(ert-deftest hierarchy::tree-sitter-outline () (dolist (file verilog-ext-test-hierarchy-file-list) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "ts.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "ts.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-ts-mode :backend tree-sitter - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list)) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "ts.outshine.sv")))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "ts.outline.sv")))))) (ert-deftest hierarchy::builtin-hierarchy::multiple-modules () (let ((file (file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv"))) @@ -391,18 +391,18 @@ :module "axi_demux_intf")) (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.builtin.hier.el")))))) -(ert-deftest hierarchy::builtin-outshine::multiple-modules () +(ert-deftest hierarchy::builtin-outline::multiple-modules () (let ((file (file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv"))) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "mm.builtin.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "mm.builtin.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-mode :backend builtin - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf")) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.builtin.outshine.sv")))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.builtin.outline.sv")))))) (ert-deftest hierarchy::tree-sitter-hierarchy::multiple-modules () (let ((file (file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv"))) @@ -417,18 +417,18 @@ :module "axi_demux_intf")) (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.ts.hier.el")))))) -(ert-deftest hierarchy::tree-sitter-outshine::multiple-modules () +(ert-deftest hierarchy::tree-sitter-outline::multiple-modules () (let ((file (file-name-concat verilog-ext-test-files-common-dir "axi_demux.sv"))) (should (test-hdl-files-equal (test-hdl-process-file :test-file file - :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "mm.ts.outshine.sv")) + :dump-file (file-name-concat verilog-ext-test-dump-dir-hierarchy (test-hdl-basename file "mm.ts.outline.sv")) :process-fn 'eval-ff :fn #'verilog-ext-test-hierarchy-buffer :args `(:mode verilog-ts-mode :backend tree-sitter - :frontend outshine + :frontend outline :files ,verilog-ext-test-hierarchy-sources-list :module "axi_demux_intf")) - (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.ts.outshine.sv")))))) + (file-name-concat verilog-ext-test-ref-dir-hierarchy (test-hdl-basename file "mm.ts.outline.sv")))))) (provide 'verilog-ext-test-hierarchy) diff --git a/test/src/verilog-ext-test-setup-package.el b/test/src/verilog-ext-test-setup-package.el index 4e62e70..533776f 100644 --- a/test/src/verilog-ext-test-setup-package.el +++ b/test/src/verilog-ext-test-setup-package.el @@ -73,7 +73,7 @@ (setq verilog-date-scientific-format t) (setq verilog-case-fold nil) ; Regexps should NOT ignore case (setq verilog-align-ifelse nil) -(setq verilog-indent-ignore-regexp "// \\*") ; Ignore outshine headings +(setq verilog-indent-ignore-regexp "// \\*") ; Ignore outline/outshine headings ;; Verilog AUTO (setq verilog-auto-delete-trailing-whitespace t) ; ‘delete-trailing-whitespace’ in ‘verilog-auto’. (setq verilog-auto-indent-on-newline t) ; Self-explaining diff --git a/test/src/verilog-ext-test-setup-straight.el b/test/src/verilog-ext-test-setup-straight.el index a66351a..b0b736d 100644 --- a/test/src/verilog-ext-test-setup-straight.el +++ b/test/src/verilog-ext-test-setup-straight.el @@ -54,7 +54,7 @@ (setq verilog-date-scientific-format t) (setq verilog-case-fold nil) ; Regexps should NOT ignore case (setq verilog-align-ifelse nil) - (setq verilog-indent-ignore-regexp "// \\*") ; Ignore outshine headings + (setq verilog-indent-ignore-regexp "// \\*") ; Ignore outline/outshine headings ;; Verilog AUTO (setq verilog-auto-delete-trailing-whitespace t) ; ‘delete-trailing-whitespace’ in ‘verilog-auto’. (setq verilog-auto-indent-on-newline t) ; Self-explaining diff --git a/verilog-ext-hierarchy.el b/verilog-ext-hierarchy.el index 8647ff1..41f1cc5 100644 --- a/verilog-ext-hierarchy.el +++ b/verilog-ext-hierarchy.el @@ -24,7 +24,7 @@ ;;; Code: -(require 'outshine) +(require 'outline) (require 'hierarchy) (require 'tree-widget) (require 'async) @@ -45,7 +45,7 @@ (defcustom verilog-ext-hierarchy-frontend 'hierarchy "Verilog-ext hierarchy display and navigation frontend." - :type '(choice (const :tag "Outshine" outshine) + :type '(choice (const :tag "Outline" outline) (const :tag "Hierarchy" hierarchy)) :group 'verilog-ext-hierarchy) @@ -164,7 +164,7 @@ Return populated `hierarchy' struct." (defun verilog-ext-hierarchy--convert-struct-to-string (hierarchy-struct) "Convert HIERARCHY-STRUCT to a string. Used to convert hierarchy formats for displaying on different frontends." - (let ((offset-blank-spaces 2) ; Intended to be used by outshine, which assumes that... + (let ((offset-blank-spaces 2) ; Intended to be used by outline, which assumes that... (unicode-spc 32) ; ... vhier output adds two offset indent spaces (debug nil)) (unless (hierarchy-p hierarchy-struct) @@ -184,7 +184,7 @@ Used to convert hierarchy formats for displaying on different frontends." "Convert HIERARCHY-STRING to an alist. Used to convert hierarchy formats for displaying on different frontends. Alist will be of the form (module instance1:NAME1 instance2:NAME2 ...)." - (let ((offset-blank-spaces 2) ; Intended to be used by outshine, which assumes that... + (let ((offset-blank-spaces 2) ; Intended to be used by outline, which assumes that... (debug nil) ; ... vhier output adds two offset indent spaces flat-hierarchy current-line parent current-indent cell hierarchy-alist) (unless (stringp hierarchy-string) @@ -518,26 +518,8 @@ Show only module name, discard instance name after colon (mod:INST)." (when verilog-ext-hierarchy-twidget-init-expand (verilog-ext-hierarchy-twidget-nav-init-expand))) -;;;;; outshine -(defmacro verilog-ext-hierarchy-outshine-nav (verilog-ext-func outshine-func) - "Define function VERILOG-EXT-FUNC to call OUTSHINE-FUNC. -Called in a buffer with `verilog-ext-hierarchy-outshine-nav-mode' enabled. -Move through headings and point at the beginning of the tag." - (declare (indent 0) (debug t)) - `(defun ,verilog-ext-func () - (interactive) - (beginning-of-line) ; Required for `outline-hide-sublevels' - (call-interactively ,outshine-func) - (skip-chars-forward (car (car outshine-promotion-headings))))) - -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-previous-visible-heading #'outline-previous-visible-heading) -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-next-visible-heading #'outline-next-visible-heading) -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-up-heading #'outline-up-heading) -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-forward-same-level #'outline-forward-same-level) -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-backward-same-level #'outline-backward-same-level) -(verilog-ext-hierarchy-outshine-nav verilog-ext-hierarchy-outshine-nav-hide-sublevels #'outline-hide-sublevels) - -(defun verilog-ext-hierarchy-outshine-jump-to-file (&optional other-window) +;;;;; outline +(defun verilog-ext-hierarchy-outline-jump-to-file (&optional other-window) "Jump to module definition at point on navigation hierarchy file. If OTHER-WINDOW is non-nil, open definition in other window." (interactive) @@ -545,46 +527,48 @@ If OTHER-WINDOW is non-nil, open definition in other window." (xref-find-definitions-other-window (thing-at-point 'symbol t)) (xref-find-definitions (thing-at-point 'symbol t)))) -(defun verilog-ext-hierarchy-outshine-jump-to-file-other-window () +(defun verilog-ext-hierarchy-outline-jump-to-file-other-window () "Jump to module definition at point on navigation hierarchy file." (interactive) - (verilog-ext-hierarchy-outshine-jump-to-file :other-window)) + (verilog-ext-hierarchy-outline-jump-to-file :other-window)) -(define-minor-mode verilog-ext-hierarchy-outshine-nav-mode - "Instance navigation frontend with `outshine'. -Makes use of processed output under `outline-minor-mode' and `outshine'." +(define-minor-mode verilog-ext-hierarchy-outline-nav-mode + "Instance navigation frontend with `outline'. +Makes use of processed output under `outline-minor-mode'." :lighter " vH" :keymap '(;; Hide/Show ("a" . outline-show-all) ("i" . outline-show-children) ("h" . outline-show-children) - ("l" . verilog-ext-hierarchy-outshine-nav-hide-sublevels) + ("l" . outline-hide-sublevels) ("I" . outline-show-branches) (";" . outline-hide-other) ;; Movement - ("u" . verilog-ext-hierarchy-outshine-nav-up-heading) - ("C-c C-u" . verilog-ext-hierarchy-outshine-nav-up-heading) - ("n" . verilog-ext-hierarchy-outshine-nav-next-visible-heading) - ("j" . verilog-ext-hierarchy-outshine-nav-next-visible-heading) - ("p" . verilog-ext-hierarchy-outshine-nav-previous-visible-heading) - ("k" . verilog-ext-hierarchy-outshine-nav-previous-visible-heading) - ("C-c C-n" . verilog-ext-hierarchy-outshine-nav-forward-same-level) - ("C-c C-p" . verilog-ext-hierarchy-outshine-nav-backward-same-level) + ("u" . outline-up-heading) + ("C-c C-u" . outline-up-heading) + ("n" . outline-next-visible-heading) + ("j" . outline-next-visible-heading) + ("p" . outline-previous-visible-heading) + ("k" . outline-previous-visible-heading) + ("C-c C-n" . outline-forward-same-level) + ("C-c C-p" . outline-backward-same-level) ;; Jump - ("o" . verilog-ext-hierarchy-outshine-jump-to-file-other-window) - ("C-o" . verilog-ext-hierarchy-outshine-jump-to-file-other-window) - ("RET" . verilog-ext-hierarchy-outshine-jump-to-file) - ("C-j" . verilog-ext-hierarchy-outshine-jump-to-file)) + ("o" . verilog-ext-hierarchy-outline-jump-to-file-other-window) + ("C-o" . verilog-ext-hierarchy-outline-jump-to-file-other-window) + ("RET" . verilog-ext-hierarchy-outline-jump-to-file) + ("C-j" . verilog-ext-hierarchy-outline-jump-to-file)) ;; Minor-mode code - (outshine-mode 1) + (setq outline-regexp "// [\\*]+ ") + (setq outline-minor-mode-highlight 'override) + (outline-minor-mode 1) (setq buffer-read-only t) (view-mode -1)) -(defun verilog-ext-hierarchy-outshine-display (hierarchy) - "Display HIERARCHY using `outshine'. +(defun verilog-ext-hierarchy-outline-display (hierarchy) + "Display HIERARCHY using `outline'. Expects HIERARCHY to be a indented string." - (let ((buf "*Verilog-outshine*")) + (let ((buf "*Verilog-outline*")) (with-current-buffer (get-buffer-create buf) (setq buffer-read-only nil) (erase-buffer) @@ -606,14 +590,14 @@ Expects HIERARCHY to be a indented string." ;; Insert local variables at the end of the file (goto-char (point-max)) (newline 1) - (insert "\n// * Buffer local variables\n// Local Variables:\n// eval: (verilog-ext-hierarchy-outshine-nav-mode)\n// End:\n") + (insert "\n// * Buffer local variables\n// Local Variables:\n// eval: (verilog-ext-hierarchy-outline-nav-mode)\n// End:\n") ;; Insert header to get some info of the file (goto-char (point-min)) (open-line 1) (insert "// Hierarchy generated by `verilog-ext'\n") (verilog-ext-with-no-hooks (verilog-mode)) - (verilog-ext-hierarchy-outshine-nav-mode)) + (verilog-ext-hierarchy-outline-nav-mode)) (pop-to-buffer buf))) ;;;; Core @@ -678,11 +662,11 @@ frontend. E.g.: If extracted with vhier and displayed with hierarchy it is needed to convert between an indented string and a populated hierarchy struct." (let ((display-hierarchy hierarchy)) - (cond (;; Outshine - (eq verilog-ext-hierarchy-frontend 'outshine) + (cond (;; Outline + (eq verilog-ext-hierarchy-frontend 'outline) (when (hierarchy-p hierarchy) (setq display-hierarchy (verilog-ext-hierarchy--convert-struct-to-string hierarchy))) - (verilog-ext-hierarchy-outshine-display display-hierarchy)) + (verilog-ext-hierarchy-outline-display display-hierarchy)) ;; Hierarchy ((eq verilog-ext-hierarchy-frontend 'hierarchy) (setq display-hierarchy hierarchy) diff --git a/verilog-ext-utils.el b/verilog-ext-utils.el index eedb5a9..1ed2d35 100644 --- a/verilog-ext-utils.el +++ b/verilog-ext-utils.el @@ -857,7 +857,7 @@ Pass the args START, END and optional COLUMN to `indent-region'." (defun verilog-ext-tab (&optional arg) "Run corresponding TAB function depending on `major-mode'. -If on an outline header, fold/unfold current section (`outshine' compatibility). +If on an outline header, fold/unfold current section (`outline' compatibility). If on a `verilog-mode' buffer, run `electric-verilog-tab' with original `verilog-mode' syntax table. Prevents indentation issues with compiler diff --git a/verilog-ext.el b/verilog-ext.el index 946a0de..d7b552e 100644 --- a/verilog-ext.el +++ b/verilog-ext.el @@ -6,7 +6,7 @@ ;; URL: https://github.com/gmlarumbe/verilog-ext ;; Version: 0.6.2 ;; Keywords: Verilog, IDE, Tools -;; Package-Requires: ((emacs "29.1") (verilog-mode "2024.3.1.121933719") (verilog-ts-mode "0.3.0") (lsp-mode "8.0.0") (ag "0.48") (ripgrep "0.4.0") (hydra "0.15.0") (apheleia "3.1") (yasnippet "0.14.0") (flycheck "32") (outshine "3.0.1") (async "1.9.7")) +;; Package-Requires: ((emacs "29.1") (verilog-mode "2024.3.1.121933719") (verilog-ts-mode "0.3.0") (lsp-mode "8.0.0") (ag "0.48") (ripgrep "0.4.0") (hydra "0.15.0") (apheleia "3.1") (yasnippet "0.14.0") (flycheck "32") (async "1.9.7")) ;; This program is free software; you can redistribute it and/or modify ;; it under the terms of the GNU General Public License as published by