Merge pull request riscv-collab#134 from kito-cheng/riscv-gcc-8.1.0

Back port patches to riscv-gcc-8.1.0 branch from trunk

gcc/ChangeLog

@@ -1,3 +1,140 @@
+2018-07-02  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv.c (riscv_expand_epilogue): Use emit_jump_insn
+	instead of emit_insn for interrupt returns.
+	* config/riscv/riscv.md (riscv_met): Add (return) to rtl.
+	(riscv_sret, riscv_uret): Likewise.
+
+2018-06-30  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/predicates.md (p2m1_shift_operand): New.
+	(high_mask_shift_operand): New.
+	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): New combiner
+	pattern using p2m1_shift_operand.
+	(lshsi3_zero_extend_3+2): New combiner pattern using
+	high_mask_shift_operand.
+
+2018-06-15  Sebastian Huber  <sebastian.huber@embedded-brains.de>
+
+	* config.gcc (riscv*-*-elf* | riscv*-*-rtems*): Use custom
+	multilibs for *-*-rtems*.
+	* config/riscv/t-rtems: New file.
+
+2018-06-06  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv.c (enum riscv_privilege_levels): New.
+	(struct machine_function): New field interrupt_mode.
+	(riscv_handle_type_attribute): New function.  Add forward declaration.
+	(riscv_attribute_table) <interrupt>: Use riscv_handle_type_attribute.
+	(riscv_expand_epilogue): Check interrupt_mode field.
+	(riscv_set_current_function): Check interrupt attribute args and
+	set interrupt_mode field.
+	* config/riscv/riscv.md (UNSPECV_SRET, UNSPECV_URET): New.
+	(riscv_sret, riscv_uret): New.
+	* doc/extend.texi (RISC-V Function Attributes) <interrupt>: Document
+	new arguments to interrupt attribute.
+
+2018-06-04  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv-protos.h (riscv_expand_epilogue): Change bool arg
+	to int.
+	* config/riscv/riscv.c (riscv_for_each_saved_reg): New args epilogue
+	and maybe_eh_return.  Change regno to unsigned int.  Use new args to
+	handle EH_RETURN_DATA_REGNO registers properly.
+	(riscv_expand_prologue): Pass new args to riscv_for_each_saved_reg.
+	(riscv_expand_epilogue): Update comment.  Change argument name and
+	type.  Update code to use new name and type.  Pass new args to
+	riscv_for_each_saved_reg.  Only use EH_RETURN_STACKADJ_RTX when
+	EXCEPTION_RETURN.
+	* config/riscv/riscv.md (NORMAL_RETURN): New.
+	(SIBCALL_RETURN, EXCEPTION_RETURN): New.
+	(epilogue, sibcall_epilogue): Update riscv_expand_epilogue arg.
+	(eh_return): Call gen_eh_return_internal and emit barrier.
+	(eh_return_internal): Call riscv_expand_epilogue.
+
+2018-05-29  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv.c (riscv_interrupt_type): Fix comment typo.
+
+2018-05-25  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv-protos.h (riscv_epilogue_uses): New.
+	* config/riscv/riscv.c (struct machine_function): Add
+	interrupt_handler_p and attribute_checked_p fields.
+	(riscv_attribute_table): Add interrupt.
+	(riscv_interrupt_type_p): New.
+	(riscv_save_reg_p): Save extra regs for interrupt handler.
+	(riscv_use_save_libcall): Return false  for interrupt handler.
+	(riscv_first_stack_step): Add forward declaration.
+	(riscv_compute_frame_info): New local interrupt_save_t1.  Set it
+	for interrupt handler with large frame.  Use it for saved reg list.
+	(riscv_expand_prologue): Move flag_stack_usage_info support to
+	eliminate duplication.
+	(riscv_expand_epilogue): Generate mret for interrupt handler.
+	(riscv_epilogue_uses): New.
+	(riscv_can_use_return_insn): Return false for interrupt handler.
+	(riscv_function_ok_for_sibcall): Likewise.
+	(riscv_set_current_function): Add interrupt handler support.
+	* config/riscv/riscv.h (EPILOGUE_USES): Call riscv_epilogue_uses.
+	* config/riscv/riscv.md (UNSPECV_MRET): New.
+	(GP_REGNUM): New.
+	(riscv_frflags, riscv_fsflags): Use tab after opcode.
+	(riscv_mret): New.
+	* doc/extend.texi (RISC-V Function Attributes) <interrupt>: New.
+
+2018-05-18  Kito Cheng  <kito.cheng@gmail.com>
+	    Monk Chiang  <sh.chiang04@gmail.com>
+	    Jim Wilson <jimw@sifive.com>
+
+	* common/config/riscv/riscv-common.c (riscv_parse_arch_string):
+	Add support to parse rv32e*.  Clear MASK_RVE for rv32i and rv64i.
+	* config.gcc (riscv*-*-*): Add support for rv32e* and ilp32e.
+	* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): Define
+	__riscv_32e when TARGET_RVE.  Handle ABI_ILP32E as soft-float ABI.
+	* config/riscv/riscv-opts.h (riscv_abi_type): Add ABI_ILP32E.
+	* config/riscv/riscv.c (riscv_compute_frame_info): When TARGET_RVE,
+	compute save_libcall_adjustment properly.
+	(riscv_option_override): Call error if TARGET_RVE and not ABI_ILP32E.
+	(riscv_conditional_register_usage): Handle TARGET_RVE and ABI_ILP32E.
+	* config/riscv/riscv.h (UNITS_PER_FP_ARG): Handle ABI_ILP32E.
+	(STACK_BOUNDARY, ABI_STACK_BOUNDARY): Handle TARGET_RVE.
+	(GP_REG_LAST, MAX_ARGS_IN_REGISTERS): Likewise.
+	(ABI_SPEC): Handle mabi=ilp32e.
+	* config/riscv/riscv.opt (abi_type): Add ABI_ILP32E.
+	(RVE): Add RVE mask.
+	* doc/invoke.texi (RISC-V options) <-mabi>: Add ilp32e info.
+	<-march>: Add rv32e as an example.
+
+2018-05-17  Jim Wilson  <jimw@sifive.com>
+
+	* expr.c (do_tablejump): When converting index to Pmode, if we have a
+	sign extended promoted subreg, and the range does not have the sign bit
+	set, then do a sign extend.
+
+	* config/riscv/riscv.c (riscv_extend_comparands): In unsigned QImode
+	test, check for sign extended subreg and/or constant operands, and
+	do a sign extend in that case.
+
+2018-05-16  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv.md (<optab>si3_mask, <optab>si3_mask_1): Prepend
+	asterisk to name.
+	(<optab>di3_mask, <optab>di3_mask_1): Likewise.
+
+2018-05-09  Jim Wilson  <jimw@sifive.com>
+
+	PR target/84797
+	* config.gcc (riscv*-*-*): Handle --with-multilib-list.
+	* config/riscv/t-withmultilib: New.
+	* config/riscv/withmultilib.h: New.
+	* doc/install.texi: Document RISC-V --with-multilib-list support.
+
+2018-05-08  Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/linux.h (MUSL_ABI_SUFFIX): Delete unnecessary backslash.
+	(LD_EMUL_SUFFIX): New.
+	(LINK_SPEC): Use it.
+
 2018-05-02  Release Manager
 
 	* GCC 8.1.0 released.

gcc/common/config/riscv/riscv-common.c

@@ -27,7 +27,8 @@ along with GCC; see the file COPYING3.  If not see
 #include "flags.h"
 #include "diagnostic-core.h"
 
-/* Parse a RISC-V ISA string into an option mask.  */
+/* Parse a RISC-V ISA string into an option mask.  Must clear or set all arch
+   dependent mask bits, in case more than one -march string is passed.  */
 
 static void
 riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
@@ -48,6 +49,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
     {
       p++;
 
+      *flags &= ~MASK_RVE;
+
       *flags |= MASK_MUL;
       *flags |= MASK_ATOMIC;
       *flags |= MASK_HARD_FLOAT;
@@ -57,6 +60,8 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
     {
       p++;
 
+      *flags &= ~MASK_RVE;
+
       *flags &= ~MASK_MUL;
       if (*p == 'm')
 	*flags |= MASK_MUL, p++;
@@ -77,6 +82,28 @@ riscv_parse_arch_string (const char *isa, int *flags, location_t loc)
 	    }
 	}
     }
+  else if (*p == 'e')
+    {
+      p++;
+
+      *flags |= MASK_RVE;
+
+      if (*flags & MASK_64BIT)
+	{
+	  error ("RV64E is not a valid base ISA");
+	  return;
+	}
+
+      *flags &= ~MASK_MUL;
+      if (*p == 'm')
+	*flags |= MASK_MUL, p++;
+
+      *flags &= ~MASK_ATOMIC;
+      if (*p == 'a')
+	*flags |= MASK_ATOMIC, p++;
+
+      *flags &= ~(MASK_HARD_FLOAT | MASK_DOUBLE_FLOAT);
+    }
   else
     {
       error_at (loc, "-march=%s: invalid ISA string", isa);

gcc/config.gcc

@@ -2073,22 +2073,24 @@ riscv*-*-linux*)
 	;;
 riscv*-*-elf* | riscv*-*-rtems*)
 	tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
-	case "x${enable_multilib}" in
-	xno) ;;
-	xyes) tmake_file="${tmake_file} riscv/t-elf-multilib" ;;
-	*) echo "Unknown value for enable_multilib"; exit 1
+	case ${target} in
+	*-*-rtems*)
+	  tm_file="${tm_file} rtems.h riscv/rtems.h"
+	  tmake_file="${tmake_file} riscv/t-rtems"
+	  ;;
+	*)
+	  case "x${enable_multilib}" in
+	  xno) ;;
+	  xyes) tmake_file="${tmake_file} riscv/t-elf-multilib" ;;
+	  *) echo "Unknown value for enable_multilib"; exit 1
+	  esac
 	esac
 	tmake_file="${tmake_file} riscv/t-riscv"
 	gnu_ld=yes
 	gas=yes
 	# Force .init_array support.  The configure script cannot always
 	# automatically detect that GAS supports it, yet we require it.
 	gcc_cv_initfini_array=yes
-	case ${target} in
-	riscv*-*-rtems*)
-	  tm_file="${tm_file} rtems.h riscv/rtems.h"
-	  ;;
-	esac
 	;;
 riscv*-*-freebsd*)
 	tm_file="${tm_file} elfos.h ${fbsd_tm_file} riscv/freebsd.h"
@@ -4078,19 +4080,20 @@ case "${target}" in
 
 		# Infer arch from --with-arch, --target, and --with-abi.
 		case "${with_arch}" in
-		rv32i* | rv32g* | rv64i* | rv64g*)
+		rv32e* | rv32i* | rv32g* | rv64i* | rv64g*)
 			# OK.
 			;;
 		"")
 			# Infer XLEN, but otherwise assume GC.
 			case "${with_abi}" in
+			ilp32e) with_arch="rv32e" ;;
 			ilp32 | ilp32f | ilp32d) with_arch="rv32gc" ;;
 			lp64 | lp64f | lp64d) with_arch="rv64gc" ;;
 			*) with_arch="rv${xlen}gc" ;;
 			esac
 			;;
 		*)
-			echo "--with-arch=${with_arch} is not supported.  The argument must begin with rv32i, rv32g, rv64i, or rv64g." 1>&2
+			echo "--with-arch=${with_arch} is not supported.  The argument must begin with rv32e, rv32i, rv32g, rv64i, or rv64g." 1>&2
 			exit 1
 			;;
 		esac
@@ -4099,11 +4102,12 @@ case "${target}" in
 		# pick a default based on the ISA, preferring soft-float
 		# unless the D extension is present.
 		case "${with_abi}" in
-		ilp32 | ilp32f | ilp32d | lp64 | lp64f | lp64d)
+		ilp32 | ilp32e | ilp32f | ilp32d | lp64 | lp64f | lp64d)
 			;;
 		"")
 			case "${with_arch}" in
 			rv32*d* | rv32g*) with_abi=ilp32d ;;
+			rv32e*) with_abi=ilp32e ;;
 			rv32*) with_abi=ilp32 ;;
 			rv64*d* | rv64g*) with_abi=lp64d ;;
 			rv64*) with_abi=lp64 ;;
@@ -4117,7 +4121,7 @@ case "${target}" in
 
 		# Make sure ABI and ISA are compatible.
 		case "${with_abi},${with_arch}" in
-		ilp32,rv32* \
+		ilp32,rv32* | ilp32e,rv32e* \
 		| ilp32f,rv32*f* | ilp32f,rv32g* \
 		| ilp32d,rv32*d* | ilp32d,rv32g* \
 		| lp64,rv64* \
@@ -4129,6 +4133,58 @@ case "${target}" in
 			exit 1
 			;;
 		esac
+
+		# Handle --with-multilib-list.
+		if test "x${with_multilib_list}" != xdefault; then
+			tm_file="${tm_file} riscv/withmultilib.h"
+			tmake_file="${tmake_file} riscv/t-withmultilib"
+
+			case ${with_multilib_list} in
+			ilp32 | ilp32f | ilp32d \
+			| lp64 | lp64f | lp64d )
+				TM_MULTILIB_CONFIG="${with_arch},${with_multilib_list}"
+				;;
+			*)
+				echo "--with-multilib-list=${with_multilib_list} not supported."
+				exit 1
+			esac
+
+			# Define macros to select the default multilib.
+			case ${with_arch} in
+			rv32gc)
+				tm_defines="${tm_defines} TARGET_MLIB_ARCH=1"
+				;;
+			rv64gc)
+				tm_defines="${tm_defines} TARGET_MLIB_ARCH=2"
+				;;
+			*)
+				echo "unsupported --with-arch for --with-multilib-list"
+				exit 1
+			esac
+			case ${with_abi} in
+			ilp32)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=1"
+				;;
+			ilp32f)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=2"
+				;;
+			ilp32d)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=3"
+				;;
+			lp64)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=4"
+				;;
+			lp64f)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=5"
+				;;
+			lp64d)
+				tm_defines="${tm_defines} TARGET_MLIB_ABI=6"
+				;;
+			*)
+				echo "unsupported --with-abi for --with-multilib"
+				exit 1
+			esac
+		fi
 		;;
 
 	mips*-*-*)

gcc/config/riscv/linux.h

@@ -30,7 +30,7 @@ along with GCC; see the file COPYING3.  If not see
   "%{mabi=ilp32d:}" \
   "%{mabi=lp64:-sf}" \
   "%{mabi=lp64f:-sp}" \
-  "%{mabi=lp64d:}" \
+  "%{mabi=lp64d:}"
 
 #undef MUSL_DYNAMIC_LINKER
 #define MUSL_DYNAMIC_LINKER "/lib/ld-musl-riscv" XLEN_SPEC MUSL_ABI_SUFFIX ".so.1"
@@ -49,8 +49,16 @@ along with GCC; see the file COPYING3.  If not see
 
 #define CPP_SPEC "%{pthread:-D_REENTRANT}"
 
+#define LD_EMUL_SUFFIX \
+  "%{mabi=lp64d:}" \
+  "%{mabi=lp64f:_lp64f}" \
+  "%{mabi=lp64:_lp64}" \
+  "%{mabi=ilp32d:}" \
+  "%{mabi=ilp32f:_ilp32f}" \
+  "%{mabi=ilp32:_ilp32}"
+
 #define LINK_SPEC "\
--melf" XLEN_SPEC "lriscv \
+-melf" XLEN_SPEC "lriscv" LD_EMUL_SUFFIX " \
 %{mno-relax:--no-relax} \
 %{shared} \
   %{!shared: \

gcc/config/riscv/predicates.md

@@ -71,6 +71,26 @@
   return !LUI_OPERAND (INTVAL (op)) && !SMALL_OPERAND (INTVAL (op));
 })
 
+(define_predicate "p2m1_shift_operand"
+  (match_code "const_int")
+{
+  int val = exact_log2 (INTVAL (op) + 1);
+  if (val < 12)
+    return false;
+  return true;
+ })
+
+(define_predicate "high_mask_shift_operand"
+  (match_code "const_int")
+{
+  int val1 = clz_hwi (~ INTVAL (op));
+  int val0 = ctz_hwi (INTVAL (op));
+  if ((val0 + val1 == BITS_PER_WORD)
+      && val0 > 31 && val0 < 64)
+    return true;
+  return false;
+})
+
 (define_predicate "move_operand"
   (match_operand 0 "general_operand")
 {