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renamed verylog to iodine

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gokhankici committed May 10, 2019
1 parent 719e04c commit 218f4cc047ae25870b99ae99060ee0d655b48ca2
Showing with 150 additions and 150 deletions.
  1. +1 −1 .gitignore
  2. +1 −1 app/Main.hs
  3. +6 −6 package.yaml
  4. +5 −5 src/{Verylog → Iodine}/Abduction/Graph.hs
  5. +6 −6 src/{Verylog → Iodine}/Abduction/Parser.hs
  6. +10 −10 src/{Verylog → Iodine}/Abduction/RandomSearch.hs
  7. +8 −8 src/{Verylog → Iodine}/Abduction/Runner.hs
  8. +5 −5 src/{Verylog → Iodine}/Abduction/Sample.hs
  9. +5 −5 src/{Verylog → Iodine}/Abduction/Testing.hs
  10. +3 −3 src/{Verylog → Iodine}/Abduction/Transform.hs
  11. +3 −3 src/{Verylog → Iodine}/Abduction/Types.hs
  12. +2 −2 src/{Verylog → Iodine}/Abduction/Utils.hs
  13. +5 −5 src/{Verylog → Iodine}/Language/Parser.hs
  14. +1 −1 src/{Verylog → Iodine}/Language/Types.hs
  15. +8 −8 src/{Verylog → Iodine}/Pipeline.hs
  16. +23 −23 src/{Verylog → Iodine}/Runner.hs
  17. +2 −2 src/{Verylog → Iodine}/Solver/Common.hs
  18. +5 −5 src/{Verylog → Iodine}/Solver/FP/FQ.hs
  19. +6 −6 src/{Verylog → Iodine}/Solver/FP/Solve.hs
  20. +3 −3 src/{Verylog → Iodine}/Solver/FP/Types.hs
  21. +3 −3 src/{Verylog → Iodine}/Transform/DFG.hs
  22. +6 −6 src/{Verylog → Iodine}/Transform/FP/VCGen.hs
  23. +4 −4 src/{Verylog → Iodine}/Transform/Merge.hs
  24. +2 −2 src/{Verylog → Iodine}/Transform/Modularize.hs
  25. +3 −3 src/{Verylog → Iodine}/Transform/SanityCheck.hs
  26. +4 −4 src/{Verylog → Iodine}/Transform/TransitionRelation.hs
  27. +3 −3 src/{Verylog → Iodine}/Transform/Utils.hs
  28. +5 −5 src/{Verylog → Iodine}/Transform/VCGen.hs
  29. +4 −4 src/{Verylog → Iodine}/Transform/Visualize.hs
  30. +3 −3 src/{Verylog → Iodine}/Types.hs
  31. +1 −1 src/{Verylog → Iodine}/Utils.hs
  32. +1 −1 t
  33. +3 −3 test/Test.hs
@@ -1,6 +1,6 @@
.stack-work/
.stack-work-profile/
/verylog-hs.cabal
/iodine.cabal
configuration.sh
.*.pl
.*.preproc.v
@@ -1,6 +1,6 @@
module Main where

import qualified Verylog.Runner as R (main)
import qualified Iodine.Runner as R (main)

main :: IO ()
main = R.main
@@ -1,6 +1,6 @@
name: verylog-hs
name: iodine
version: 0.1.0.0
github: "gokhankici/verylog-hs"
github: "gokhankici/iodine"
license: MIT
author: "Rami Gokhan Kici"
maintainer: "gokhankici@gmail.com"
@@ -13,7 +13,7 @@ extra-source-files:
synopsis: Generates the transition relation & verification conditions from a Verilog IR
category: Hardware Verification

description: Please see the README on Github at <https://github.com/gokhankici/verylog-hs#readme>
description: Please see the README on Github at <https://github.com/gokhankici/iodine#readme>

dependencies:
- base >= 4.7 && < 5
@@ -45,7 +45,7 @@ dependencies:
library:
source-dirs: src
exposed-modules:
- Verylog.Runner
- Iodine.Runner
ghc-options:
- -Werror
- -O2
@@ -75,7 +75,7 @@ executables:
- -Werror
- -O2
dependencies:
- verylog-hs
- iodine

tests:
iodine-test:
@@ -89,6 +89,6 @@ tests:
- -Werror
- -O2
dependencies:
- verylog-hs
- iodine
- hspec
- hspec-core
@@ -5,14 +5,14 @@
{-# LANGUAGE DeriveGeneric #-}
{-# LANGUAGE OverloadedStrings #-}

module Verylog.Abduction.Graph ( updateAnnotations
module Iodine.Abduction.Graph ( updateAnnotations
, toAbductionGraph
, G, E
) where

import Verylog.Types
import Verylog.Language.Types
import Verylog.Abduction.Types
import Iodine.Types
import Iodine.Language.Types
import Iodine.Abduction.Types

import Control.Lens
import Control.Monad.State.Lazy
@@ -107,7 +107,7 @@ goAsgn prts (implicits, g) (lName, lIndex) r = g''
regLookup name ps =
case SQ.viewl ps of
p SQ.:< rest ->
if fst (Verylog.Language.Types.varName p) == name
if fst (Iodine.Language.Types.varName p) == name
then case p of
Register {} -> True
Wire {} -> False
@@ -3,17 +3,17 @@
{-# LANGUAGE StrictData #-}
{-# LANGUAGE MultiWayIf #-}

module Verylog.Abduction.Parser ( toR
module Iodine.Abduction.Parser ( toR
, readAnnots
, writeAnnots
) where

import Verylog.Abduction.Types
import Iodine.Abduction.Types

import Verylog.Transform.Utils
import Verylog.Language.Types
import Verylog.Solver.FP.Types
import Verylog.Utils
import Iodine.Transform.Utils
import Iodine.Language.Types
import Iodine.Solver.FP.Types
import Iodine.Utils

import qualified Language.Fixpoint.Types as FT

@@ -4,20 +4,20 @@
{-# LANGUAGE StrictData #-}
{-# LANGUAGE MultiWayIf #-}

module Verylog.Abduction.RandomSearch (abduction) where
module Iodine.Abduction.RandomSearch (abduction) where

import Prelude hiding (break)

import Verylog.Abduction.Types
import Verylog.Abduction.Parser
import Verylog.Abduction.Utils
import Verylog.Abduction.Sample
import Iodine.Abduction.Types
import Iodine.Abduction.Parser
import Iodine.Abduction.Utils
import Iodine.Abduction.Sample

import Verylog.Language.Types
import Verylog.Solver.FP.Solve
import Verylog.Solver.FP.Types
import Verylog.Transform.FP.VCGen
import Verylog.Utils
import Iodine.Language.Types
import Iodine.Solver.FP.Solve
import Iodine.Solver.FP.Types
import Iodine.Transform.FP.VCGen
import Iodine.Utils

import qualified Language.Fixpoint.Types.Config as FC

@@ -2,18 +2,18 @@
{-# LANGUAGE StrictData #-}
{-# LANGUAGE MultiWayIf #-}

module Verylog.Abduction.Runner ( runner
module Iodine.Abduction.Runner ( runner
, runner'
, runner3, toCplexInput, cplexToMark, runner3'
) where

import Verylog.Abduction.Graph
import Verylog.Abduction.RandomSearch
import Verylog.Abduction.Transform
import Verylog.Abduction.Types
import Verylog.Language.Types
import Verylog.Solver.FP.Types
import Verylog.Types
import Iodine.Abduction.Graph
import Iodine.Abduction.RandomSearch
import Iodine.Abduction.Transform
import Iodine.Abduction.Types
import Iodine.Language.Types
import Iodine.Solver.FP.Types
import Iodine.Types

import qualified Language.Fixpoint.Types.Config as FC

@@ -3,18 +3,18 @@
{-# LANGUAGE StrictData #-}
{-# LANGUAGE MultiWayIf #-}

module Verylog.Abduction.Sample ( sample
module Iodine.Abduction.Sample ( sample
, calculateCost
, acceptanceProb
) where

import Prelude hiding (break)

import Verylog.Abduction.Types
import Verylog.Abduction.Utils
import Iodine.Abduction.Types
import Iodine.Abduction.Utils

import Verylog.Solver.FP.Types
import Verylog.Language.Types
import Iodine.Solver.FP.Types
import Iodine.Language.Types

import Control.Lens
import qualified Data.HashSet as HS
@@ -6,12 +6,12 @@
-- | This is a module used for debugging/testing stuff
-- | Not needed by the rest of the modules

module Verylog.Abduction.Testing where
module Iodine.Abduction.Testing where

-- import Verylog.Abduction.Graph
-- import Verylog.Abduction.Runner
-- import Verylog.Abduction.Types hiding (t)
-- import Verylog.Language.Types
-- import Iodine.Abduction.Graph
-- import Iodine.Abduction.Runner
-- import Iodine.Abduction.Types hiding (t)
-- import Iodine.Language.Types

-- import Control.Monad
-- import Data.Maybe (fromJust)
@@ -6,12 +6,12 @@
{-# LANGUAGE TemplateHaskell #-}
{-# LANGUAGE DeriveGeneric #-}

module Verylog.Abduction.Transform ( giveUniqueId
module Iodine.Abduction.Transform ( giveUniqueId
, giveUniqueId'
, undoUniqueId
) where
import Verylog.Language.Types
import Verylog.Solver.FP.Types (FPStA(..), FPQualifierA(..))
import Iodine.Language.Types
import Iodine.Solver.FP.Types (FPStA(..), FPQualifierA(..))

import Control.Lens hiding (Index)
import Control.Monad.State.Lazy
@@ -4,10 +4,10 @@
{-# LANGUAGE MultiWayIf #-}
{-# LANGUAGE OverloadedStrings #-}

module Verylog.Abduction.Types where
module Iodine.Abduction.Types where

import Verylog.Language.Types
import Verylog.Solver.FP.Types
import Iodine.Language.Types
import Iodine.Solver.FP.Types

import qualified Language.Fixpoint.Types as FT
import qualified Language.Fixpoint.Types.Config as FC
@@ -1,6 +1,6 @@
module Verylog.Abduction.Utils where
module Iodine.Abduction.Utils where

import Verylog.Utils
import Iodine.Utils

import Control.Monad.State.Lazy
import qualified Data.Sequence as SQ
@@ -6,7 +6,7 @@
{-# LANGUAGE StrictData #-}
{-# LANGUAGE OverloadedStrings #-}

module Verylog.Language.Parser ( parse
module Iodine.Language.Parser ( parse
, renderError
, IRParseError (..)
) where
@@ -28,12 +28,12 @@ import qualified Text.Megaparsec.Char.Lexer as L
import Text.Printf
import qualified Data.Sequence as SQ

import Verylog.Utils
import Verylog.Language.Types
import Verylog.Solver.FP.Types
import Iodine.Utils
import Iodine.Language.Types
import Iodine.Solver.FP.Types

-----------------------------------------------------------------------------------
-- | Verylog IR
-- | Iodine IR
-----------------------------------------------------------------------------------

data ParsePort = PInput Id
@@ -6,7 +6,7 @@
{-# LANGUAGE OverloadedStrings #-}
{-# LANGUAGE GADTs #-}

module Verylog.Language.Types where
module Iodine.Language.Types where

import Control.Exception
import Control.Lens
@@ -1,17 +1,17 @@
module Verylog.Pipeline ( pipeline
module Iodine.Pipeline ( pipeline
, pipeline'
) where

import Control.Arrow

import Verylog.Types
import Iodine.Types

import Verylog.Language.Parser
import Verylog.Solver.FP.Types
import Verylog.Transform.FP.VCGen
import Verylog.Transform.Merge
import Verylog.Transform.Modularize
import Verylog.Transform.SanityCheck
import Iodine.Language.Parser
import Iodine.Solver.FP.Types
import Iodine.Transform.FP.VCGen
import Iodine.Transform.Merge
import Iodine.Transform.Modularize
import Iodine.Transform.SanityCheck

-- parse :: (FilePath, String) -> (States, Qualifiers)
-- modularize :: States -> ABS

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