Skip to content
Permalink
c170b14c2c
Switch branches/tags

Name already in use

A tag already exists with the provided branch name. Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. Are you sure you want to create this branch?

go/src/cmd/compile/internal/ssa/rewrite386.go

Go to file
 
 
Cannot retrieve contributors at this time
23093 lines (23090 sloc) 514 KB
Raw Blame
// Code generated from gen/386.rules; DO NOT EDIT.
// generated with: cd gen; go run *.go
package ssa
import "math"
import "cmd/compile/internal/types"
func rewriteValue386(v *Value) bool {
switch v.Op {
case Op386ADCL:
return rewriteValue386_Op386ADCL_0(v)
case Op386ADDL:
return rewriteValue386_Op386ADDL_0(v) || rewriteValue386_Op386ADDL_10(v) || rewriteValue386_Op386ADDL_20(v)
case Op386ADDLcarry:
return rewriteValue386_Op386ADDLcarry_0(v)
case Op386ADDLconst:
return rewriteValue386_Op386ADDLconst_0(v)
case Op386ADDLconstmodify:
return rewriteValue386_Op386ADDLconstmodify_0(v)
case Op386ADDLconstmodifyidx4:
return rewriteValue386_Op386ADDLconstmodifyidx4_0(v)
case Op386ADDLload:
return rewriteValue386_Op386ADDLload_0(v)
case Op386ADDLloadidx4:
return rewriteValue386_Op386ADDLloadidx4_0(v)
case Op386ADDLmodify:
return rewriteValue386_Op386ADDLmodify_0(v)
case Op386ADDLmodifyidx4:
return rewriteValue386_Op386ADDLmodifyidx4_0(v)
case Op386ADDSD:
return rewriteValue386_Op386ADDSD_0(v)
case Op386ADDSDload:
return rewriteValue386_Op386ADDSDload_0(v)
case Op386ADDSS:
return rewriteValue386_Op386ADDSS_0(v)
case Op386ADDSSload:
return rewriteValue386_Op386ADDSSload_0(v)
case Op386ANDL:
return rewriteValue386_Op386ANDL_0(v)
case Op386ANDLconst:
return rewriteValue386_Op386ANDLconst_0(v)
case Op386ANDLconstmodify:
return rewriteValue386_Op386ANDLconstmodify_0(v)
case Op386ANDLconstmodifyidx4:
return rewriteValue386_Op386ANDLconstmodifyidx4_0(v)
case Op386ANDLload:
return rewriteValue386_Op386ANDLload_0(v)
case Op386ANDLloadidx4:
return rewriteValue386_Op386ANDLloadidx4_0(v)
case Op386ANDLmodify:
return rewriteValue386_Op386ANDLmodify_0(v)
case Op386ANDLmodifyidx4:
return rewriteValue386_Op386ANDLmodifyidx4_0(v)
case Op386CMPB:
return rewriteValue386_Op386CMPB_0(v)
case Op386CMPBconst:
return rewriteValue386_Op386CMPBconst_0(v)
case Op386CMPBload:
return rewriteValue386_Op386CMPBload_0(v)
case Op386CMPL:
return rewriteValue386_Op386CMPL_0(v)
case Op386CMPLconst:
return rewriteValue386_Op386CMPLconst_0(v) || rewriteValue386_Op386CMPLconst_10(v)
case Op386CMPLload:
return rewriteValue386_Op386CMPLload_0(v)
case Op386CMPW:
return rewriteValue386_Op386CMPW_0(v)
case Op386CMPWconst:
return rewriteValue386_Op386CMPWconst_0(v)
case Op386CMPWload:
return rewriteValue386_Op386CMPWload_0(v)
case Op386DIVSD:
return rewriteValue386_Op386DIVSD_0(v)
case Op386DIVSDload:
return rewriteValue386_Op386DIVSDload_0(v)
case Op386DIVSS:
return rewriteValue386_Op386DIVSS_0(v)
case Op386DIVSSload:
return rewriteValue386_Op386DIVSSload_0(v)
case Op386LEAL:
return rewriteValue386_Op386LEAL_0(v)
case Op386LEAL1:
return rewriteValue386_Op386LEAL1_0(v)
case Op386LEAL2:
return rewriteValue386_Op386LEAL2_0(v)
case Op386LEAL4:
return rewriteValue386_Op386LEAL4_0(v)
case Op386LEAL8:
return rewriteValue386_Op386LEAL8_0(v)
case Op386MOVBLSX:
return rewriteValue386_Op386MOVBLSX_0(v)
case Op386MOVBLSXload:
return rewriteValue386_Op386MOVBLSXload_0(v)
case Op386MOVBLZX:
return rewriteValue386_Op386MOVBLZX_0(v)
case Op386MOVBload:
return rewriteValue386_Op386MOVBload_0(v)
case Op386MOVBloadidx1:
return rewriteValue386_Op386MOVBloadidx1_0(v)
case Op386MOVBstore:
return rewriteValue386_Op386MOVBstore_0(v) || rewriteValue386_Op386MOVBstore_10(v)
case Op386MOVBstoreconst:
return rewriteValue386_Op386MOVBstoreconst_0(v)
case Op386MOVBstoreconstidx1:
return rewriteValue386_Op386MOVBstoreconstidx1_0(v)
case Op386MOVBstoreidx1:
return rewriteValue386_Op386MOVBstoreidx1_0(v) || rewriteValue386_Op386MOVBstoreidx1_10(v) || rewriteValue386_Op386MOVBstoreidx1_20(v)
case Op386MOVLload:
return rewriteValue386_Op386MOVLload_0(v)
case Op386MOVLloadidx1:
return rewriteValue386_Op386MOVLloadidx1_0(v)
case Op386MOVLloadidx4:
return rewriteValue386_Op386MOVLloadidx4_0(v)
case Op386MOVLstore:
return rewriteValue386_Op386MOVLstore_0(v) || rewriteValue386_Op386MOVLstore_10(v) || rewriteValue386_Op386MOVLstore_20(v)
case Op386MOVLstoreconst:
return rewriteValue386_Op386MOVLstoreconst_0(v)
case Op386MOVLstoreconstidx1:
return rewriteValue386_Op386MOVLstoreconstidx1_0(v)
case Op386MOVLstoreconstidx4:
return rewriteValue386_Op386MOVLstoreconstidx4_0(v)
case Op386MOVLstoreidx1:
return rewriteValue386_Op386MOVLstoreidx1_0(v)
case Op386MOVLstoreidx4:
return rewriteValue386_Op386MOVLstoreidx4_0(v) || rewriteValue386_Op386MOVLstoreidx4_10(v)
case Op386MOVSDconst:
return rewriteValue386_Op386MOVSDconst_0(v)
case Op386MOVSDload:
return rewriteValue386_Op386MOVSDload_0(v)
case Op386MOVSDloadidx1:
return rewriteValue386_Op386MOVSDloadidx1_0(v)
case Op386MOVSDloadidx8:
return rewriteValue386_Op386MOVSDloadidx8_0(v)
case Op386MOVSDstore:
return rewriteValue386_Op386MOVSDstore_0(v)
case Op386MOVSDstoreidx1:
return rewriteValue386_Op386MOVSDstoreidx1_0(v)
case Op386MOVSDstoreidx8:
return rewriteValue386_Op386MOVSDstoreidx8_0(v)
case Op386MOVSSconst:
return rewriteValue386_Op386MOVSSconst_0(v)
case Op386MOVSSload:
return rewriteValue386_Op386MOVSSload_0(v)
case Op386MOVSSloadidx1:
return rewriteValue386_Op386MOVSSloadidx1_0(v)
case Op386MOVSSloadidx4:
return rewriteValue386_Op386MOVSSloadidx4_0(v)
case Op386MOVSSstore:
return rewriteValue386_Op386MOVSSstore_0(v)
case Op386MOVSSstoreidx1:
return rewriteValue386_Op386MOVSSstoreidx1_0(v)
case Op386MOVSSstoreidx4:
return rewriteValue386_Op386MOVSSstoreidx4_0(v)
case Op386MOVWLSX:
return rewriteValue386_Op386MOVWLSX_0(v)
case Op386MOVWLSXload:
return rewriteValue386_Op386MOVWLSXload_0(v)
case Op386MOVWLZX:
return rewriteValue386_Op386MOVWLZX_0(v)
case Op386MOVWload:
return rewriteValue386_Op386MOVWload_0(v)
case Op386MOVWloadidx1:
return rewriteValue386_Op386MOVWloadidx1_0(v)
case Op386MOVWloadidx2:
return rewriteValue386_Op386MOVWloadidx2_0(v)
case Op386MOVWstore:
return rewriteValue386_Op386MOVWstore_0(v)
case Op386MOVWstoreconst:
return rewriteValue386_Op386MOVWstoreconst_0(v)
case Op386MOVWstoreconstidx1:
return rewriteValue386_Op386MOVWstoreconstidx1_0(v)
case Op386MOVWstoreconstidx2:
return rewriteValue386_Op386MOVWstoreconstidx2_0(v)
case Op386MOVWstoreidx1:
return rewriteValue386_Op386MOVWstoreidx1_0(v) || rewriteValue386_Op386MOVWstoreidx1_10(v)
case Op386MOVWstoreidx2:
return rewriteValue386_Op386MOVWstoreidx2_0(v)
case Op386MULL:
return rewriteValue386_Op386MULL_0(v)
case Op386MULLconst:
return rewriteValue386_Op386MULLconst_0(v) || rewriteValue386_Op386MULLconst_10(v) || rewriteValue386_Op386MULLconst_20(v) || rewriteValue386_Op386MULLconst_30(v)
case Op386MULLload:
return rewriteValue386_Op386MULLload_0(v)
case Op386MULLloadidx4:
return rewriteValue386_Op386MULLloadidx4_0(v)
case Op386MULSD:
return rewriteValue386_Op386MULSD_0(v)
case Op386MULSDload:
return rewriteValue386_Op386MULSDload_0(v)
case Op386MULSS:
return rewriteValue386_Op386MULSS_0(v)
case Op386MULSSload:
return rewriteValue386_Op386MULSSload_0(v)
case Op386NEGL:
return rewriteValue386_Op386NEGL_0(v)
case Op386NOTL:
return rewriteValue386_Op386NOTL_0(v)
case Op386ORL:
return rewriteValue386_Op386ORL_0(v) || rewriteValue386_Op386ORL_10(v) || rewriteValue386_Op386ORL_20(v) || rewriteValue386_Op386ORL_30(v) || rewriteValue386_Op386ORL_40(v) || rewriteValue386_Op386ORL_50(v)
case Op386ORLconst:
return rewriteValue386_Op386ORLconst_0(v)
case Op386ORLconstmodify:
return rewriteValue386_Op386ORLconstmodify_0(v)
case Op386ORLconstmodifyidx4:
return rewriteValue386_Op386ORLconstmodifyidx4_0(v)
case Op386ORLload:
return rewriteValue386_Op386ORLload_0(v)
case Op386ORLloadidx4:
return rewriteValue386_Op386ORLloadidx4_0(v)
case Op386ORLmodify:
return rewriteValue386_Op386ORLmodify_0(v)
case Op386ORLmodifyidx4:
return rewriteValue386_Op386ORLmodifyidx4_0(v)
case Op386ROLBconst:
return rewriteValue386_Op386ROLBconst_0(v)
case Op386ROLLconst:
return rewriteValue386_Op386ROLLconst_0(v)
case Op386ROLWconst:
return rewriteValue386_Op386ROLWconst_0(v)
case Op386SARB:
return rewriteValue386_Op386SARB_0(v)
case Op386SARBconst:
return rewriteValue386_Op386SARBconst_0(v)
case Op386SARL:
return rewriteValue386_Op386SARL_0(v)
case Op386SARLconst:
return rewriteValue386_Op386SARLconst_0(v)
case Op386SARW:
return rewriteValue386_Op386SARW_0(v)
case Op386SARWconst:
return rewriteValue386_Op386SARWconst_0(v)
case Op386SBBL:
return rewriteValue386_Op386SBBL_0(v)
case Op386SBBLcarrymask:
return rewriteValue386_Op386SBBLcarrymask_0(v)
case Op386SETA:
return rewriteValue386_Op386SETA_0(v)
case Op386SETAE:
return rewriteValue386_Op386SETAE_0(v)
case Op386SETB:
return rewriteValue386_Op386SETB_0(v)
case Op386SETBE:
return rewriteValue386_Op386SETBE_0(v)
case Op386SETEQ:
return rewriteValue386_Op386SETEQ_0(v)
case Op386SETG:
return rewriteValue386_Op386SETG_0(v)
case Op386SETGE:
return rewriteValue386_Op386SETGE_0(v)
case Op386SETL:
return rewriteValue386_Op386SETL_0(v)
case Op386SETLE:
return rewriteValue386_Op386SETLE_0(v)
case Op386SETNE:
return rewriteValue386_Op386SETNE_0(v)
case Op386SHLL:
return rewriteValue386_Op386SHLL_0(v)
case Op386SHLLconst:
return rewriteValue386_Op386SHLLconst_0(v)
case Op386SHRB:
return rewriteValue386_Op386SHRB_0(v)
case Op386SHRBconst:
return rewriteValue386_Op386SHRBconst_0(v)
case Op386SHRL:
return rewriteValue386_Op386SHRL_0(v)
case Op386SHRLconst:
return rewriteValue386_Op386SHRLconst_0(v)
case Op386SHRW:
return rewriteValue386_Op386SHRW_0(v)
case Op386SHRWconst:
return rewriteValue386_Op386SHRWconst_0(v)
case Op386SUBL:
return rewriteValue386_Op386SUBL_0(v)
case Op386SUBLcarry:
return rewriteValue386_Op386SUBLcarry_0(v)
case Op386SUBLconst:
return rewriteValue386_Op386SUBLconst_0(v)
case Op386SUBLload:
return rewriteValue386_Op386SUBLload_0(v)
case Op386SUBLloadidx4:
return rewriteValue386_Op386SUBLloadidx4_0(v)
case Op386SUBLmodify:
return rewriteValue386_Op386SUBLmodify_0(v)
case Op386SUBLmodifyidx4:
return rewriteValue386_Op386SUBLmodifyidx4_0(v)
case Op386SUBSD:
return rewriteValue386_Op386SUBSD_0(v)
case Op386SUBSDload:
return rewriteValue386_Op386SUBSDload_0(v)
case Op386SUBSS:
return rewriteValue386_Op386SUBSS_0(v)
case Op386SUBSSload:
return rewriteValue386_Op386SUBSSload_0(v)
case Op386XORL:
return rewriteValue386_Op386XORL_0(v) || rewriteValue386_Op386XORL_10(v)
case Op386XORLconst:
return rewriteValue386_Op386XORLconst_0(v)
case Op386XORLconstmodify:
return rewriteValue386_Op386XORLconstmodify_0(v)
case Op386XORLconstmodifyidx4:
return rewriteValue386_Op386XORLconstmodifyidx4_0(v)
case Op386XORLload:
return rewriteValue386_Op386XORLload_0(v)
case Op386XORLloadidx4:
return rewriteValue386_Op386XORLloadidx4_0(v)
case Op386XORLmodify:
return rewriteValue386_Op386XORLmodify_0(v)
case Op386XORLmodifyidx4:
return rewriteValue386_Op386XORLmodifyidx4_0(v)
case OpAdd16:
return rewriteValue386_OpAdd16_0(v)
case OpAdd32:
return rewriteValue386_OpAdd32_0(v)
case OpAdd32F:
return rewriteValue386_OpAdd32F_0(v)
case OpAdd32carry:
return rewriteValue386_OpAdd32carry_0(v)
case OpAdd32withcarry:
return rewriteValue386_OpAdd32withcarry_0(v)
case OpAdd64F:
return rewriteValue386_OpAdd64F_0(v)
case OpAdd8:
return rewriteValue386_OpAdd8_0(v)
case OpAddPtr:
return rewriteValue386_OpAddPtr_0(v)
case OpAddr:
return rewriteValue386_OpAddr_0(v)
case OpAnd16:
return rewriteValue386_OpAnd16_0(v)
case OpAnd32:
return rewriteValue386_OpAnd32_0(v)
case OpAnd8:
return rewriteValue386_OpAnd8_0(v)
case OpAndB:
return rewriteValue386_OpAndB_0(v)
case OpAvg32u:
return rewriteValue386_OpAvg32u_0(v)
case OpBswap32:
return rewriteValue386_OpBswap32_0(v)
case OpClosureCall:
return rewriteValue386_OpClosureCall_0(v)
case OpCom16:
return rewriteValue386_OpCom16_0(v)
case OpCom32:
return rewriteValue386_OpCom32_0(v)
case OpCom8:
return rewriteValue386_OpCom8_0(v)
case OpConst16:
return rewriteValue386_OpConst16_0(v)
case OpConst32:
return rewriteValue386_OpConst32_0(v)
case OpConst32F:
return rewriteValue386_OpConst32F_0(v)
case OpConst64F:
return rewriteValue386_OpConst64F_0(v)
case OpConst8:
return rewriteValue386_OpConst8_0(v)
case OpConstBool:
return rewriteValue386_OpConstBool_0(v)
case OpConstNil:
return rewriteValue386_OpConstNil_0(v)
case OpCtz16:
return rewriteValue386_OpCtz16_0(v)
case OpCtz16NonZero:
return rewriteValue386_OpCtz16NonZero_0(v)
case OpCvt32Fto32:
return rewriteValue386_OpCvt32Fto32_0(v)
case OpCvt32Fto64F:
return rewriteValue386_OpCvt32Fto64F_0(v)
case OpCvt32to32F:
return rewriteValue386_OpCvt32to32F_0(v)
case OpCvt32to64F:
return rewriteValue386_OpCvt32to64F_0(v)
case OpCvt64Fto32:
return rewriteValue386_OpCvt64Fto32_0(v)
case OpCvt64Fto32F:
return rewriteValue386_OpCvt64Fto32F_0(v)
case OpDiv16:
return rewriteValue386_OpDiv16_0(v)
case OpDiv16u:
return rewriteValue386_OpDiv16u_0(v)
case OpDiv32:
return rewriteValue386_OpDiv32_0(v)
case OpDiv32F:
return rewriteValue386_OpDiv32F_0(v)
case OpDiv32u:
return rewriteValue386_OpDiv32u_0(v)
case OpDiv64F:
return rewriteValue386_OpDiv64F_0(v)
case OpDiv8:
return rewriteValue386_OpDiv8_0(v)
case OpDiv8u:
return rewriteValue386_OpDiv8u_0(v)
case OpEq16:
return rewriteValue386_OpEq16_0(v)
case OpEq32:
return rewriteValue386_OpEq32_0(v)
case OpEq32F:
return rewriteValue386_OpEq32F_0(v)
case OpEq64F:
return rewriteValue386_OpEq64F_0(v)
case OpEq8:
return rewriteValue386_OpEq8_0(v)
case OpEqB:
return rewriteValue386_OpEqB_0(v)
case OpEqPtr:
return rewriteValue386_OpEqPtr_0(v)
case OpGeq16:
return rewriteValue386_OpGeq16_0(v)
case OpGeq16U:
return rewriteValue386_OpGeq16U_0(v)
case OpGeq32:
return rewriteValue386_OpGeq32_0(v)
case OpGeq32F:
return rewriteValue386_OpGeq32F_0(v)
case OpGeq32U:
return rewriteValue386_OpGeq32U_0(v)
case OpGeq64F:
return rewriteValue386_OpGeq64F_0(v)
case OpGeq8:
return rewriteValue386_OpGeq8_0(v)
case OpGeq8U:
return rewriteValue386_OpGeq8U_0(v)
case OpGetCallerPC:
return rewriteValue386_OpGetCallerPC_0(v)
case OpGetCallerSP:
return rewriteValue386_OpGetCallerSP_0(v)
case OpGetClosurePtr:
return rewriteValue386_OpGetClosurePtr_0(v)
case OpGetG:
return rewriteValue386_OpGetG_0(v)
case OpGreater16:
return rewriteValue386_OpGreater16_0(v)
case OpGreater16U:
return rewriteValue386_OpGreater16U_0(v)
case OpGreater32:
return rewriteValue386_OpGreater32_0(v)
case OpGreater32F:
return rewriteValue386_OpGreater32F_0(v)
case OpGreater32U:
return rewriteValue386_OpGreater32U_0(v)
case OpGreater64F:
return rewriteValue386_OpGreater64F_0(v)
case OpGreater8:
return rewriteValue386_OpGreater8_0(v)
case OpGreater8U:
return rewriteValue386_OpGreater8U_0(v)
case OpHmul32:
return rewriteValue386_OpHmul32_0(v)
case OpHmul32u:
return rewriteValue386_OpHmul32u_0(v)
case OpInterCall:
return rewriteValue386_OpInterCall_0(v)
case OpIsInBounds:
return rewriteValue386_OpIsInBounds_0(v)
case OpIsNonNil:
return rewriteValue386_OpIsNonNil_0(v)
case OpIsSliceInBounds:
return rewriteValue386_OpIsSliceInBounds_0(v)
case OpLeq16:
return rewriteValue386_OpLeq16_0(v)
case OpLeq16U:
return rewriteValue386_OpLeq16U_0(v)
case OpLeq32:
return rewriteValue386_OpLeq32_0(v)
case OpLeq32F:
return rewriteValue386_OpLeq32F_0(v)
case OpLeq32U:
return rewriteValue386_OpLeq32U_0(v)
case OpLeq64F:
return rewriteValue386_OpLeq64F_0(v)
case OpLeq8:
return rewriteValue386_OpLeq8_0(v)
case OpLeq8U:
return rewriteValue386_OpLeq8U_0(v)
case OpLess16:
return rewriteValue386_OpLess16_0(v)
case OpLess16U:
return rewriteValue386_OpLess16U_0(v)
case OpLess32:
return rewriteValue386_OpLess32_0(v)
case OpLess32F:
return rewriteValue386_OpLess32F_0(v)
case OpLess32U:
return rewriteValue386_OpLess32U_0(v)
case OpLess64F:
return rewriteValue386_OpLess64F_0(v)
case OpLess8:
return rewriteValue386_OpLess8_0(v)
case OpLess8U:
return rewriteValue386_OpLess8U_0(v)
case OpLoad:
return rewriteValue386_OpLoad_0(v)
case OpLocalAddr:
return rewriteValue386_OpLocalAddr_0(v)
case OpLsh16x16:
return rewriteValue386_OpLsh16x16_0(v)
case OpLsh16x32:
return rewriteValue386_OpLsh16x32_0(v)
case OpLsh16x64:
return rewriteValue386_OpLsh16x64_0(v)
case OpLsh16x8:
return rewriteValue386_OpLsh16x8_0(v)
case OpLsh32x16:
return rewriteValue386_OpLsh32x16_0(v)
case OpLsh32x32:
return rewriteValue386_OpLsh32x32_0(v)
case OpLsh32x64:
return rewriteValue386_OpLsh32x64_0(v)
case OpLsh32x8:
return rewriteValue386_OpLsh32x8_0(v)
case OpLsh8x16:
return rewriteValue386_OpLsh8x16_0(v)
case OpLsh8x32:
return rewriteValue386_OpLsh8x32_0(v)
case OpLsh8x64:
return rewriteValue386_OpLsh8x64_0(v)
case OpLsh8x8:
return rewriteValue386_OpLsh8x8_0(v)
case OpMod16:
return rewriteValue386_OpMod16_0(v)
case OpMod16u:
return rewriteValue386_OpMod16u_0(v)
case OpMod32:
return rewriteValue386_OpMod32_0(v)
case OpMod32u:
return rewriteValue386_OpMod32u_0(v)
case OpMod8:
return rewriteValue386_OpMod8_0(v)
case OpMod8u:
return rewriteValue386_OpMod8u_0(v)
case OpMove:
return rewriteValue386_OpMove_0(v) || rewriteValue386_OpMove_10(v)
case OpMul16:
return rewriteValue386_OpMul16_0(v)
case OpMul32:
return rewriteValue386_OpMul32_0(v)
case OpMul32F:
return rewriteValue386_OpMul32F_0(v)
case OpMul32uhilo:
return rewriteValue386_OpMul32uhilo_0(v)
case OpMul64F:
return rewriteValue386_OpMul64F_0(v)
case OpMul8:
return rewriteValue386_OpMul8_0(v)
case OpNeg16:
return rewriteValue386_OpNeg16_0(v)
case OpNeg32:
return rewriteValue386_OpNeg32_0(v)
case OpNeg32F:
return rewriteValue386_OpNeg32F_0(v)
case OpNeg64F:
return rewriteValue386_OpNeg64F_0(v)
case OpNeg8:
return rewriteValue386_OpNeg8_0(v)
case OpNeq16:
return rewriteValue386_OpNeq16_0(v)
case OpNeq32:
return rewriteValue386_OpNeq32_0(v)
case OpNeq32F:
return rewriteValue386_OpNeq32F_0(v)
case OpNeq64F:
return rewriteValue386_OpNeq64F_0(v)
case OpNeq8:
return rewriteValue386_OpNeq8_0(v)
case OpNeqB:
return rewriteValue386_OpNeqB_0(v)
case OpNeqPtr:
return rewriteValue386_OpNeqPtr_0(v)
case OpNilCheck:
return rewriteValue386_OpNilCheck_0(v)
case OpNot:
return rewriteValue386_OpNot_0(v)
case OpOffPtr:
return rewriteValue386_OpOffPtr_0(v)
case OpOr16:
return rewriteValue386_OpOr16_0(v)
case OpOr32:
return rewriteValue386_OpOr32_0(v)
case OpOr8:
return rewriteValue386_OpOr8_0(v)
case OpOrB:
return rewriteValue386_OpOrB_0(v)
case OpPanicBounds:
return rewriteValue386_OpPanicBounds_0(v)
case OpPanicExtend:
return rewriteValue386_OpPanicExtend_0(v)
case OpRotateLeft16:
return rewriteValue386_OpRotateLeft16_0(v)
case OpRotateLeft32:
return rewriteValue386_OpRotateLeft32_0(v)
case OpRotateLeft8:
return rewriteValue386_OpRotateLeft8_0(v)
case OpRound32F:
return rewriteValue386_OpRound32F_0(v)
case OpRound64F:
return rewriteValue386_OpRound64F_0(v)
case OpRsh16Ux16:
return rewriteValue386_OpRsh16Ux16_0(v)
case OpRsh16Ux32:
return rewriteValue386_OpRsh16Ux32_0(v)
case OpRsh16Ux64:
return rewriteValue386_OpRsh16Ux64_0(v)
case OpRsh16Ux8:
return rewriteValue386_OpRsh16Ux8_0(v)
case OpRsh16x16:
return rewriteValue386_OpRsh16x16_0(v)
case OpRsh16x32:
return rewriteValue386_OpRsh16x32_0(v)
case OpRsh16x64:
return rewriteValue386_OpRsh16x64_0(v)
case OpRsh16x8:
return rewriteValue386_OpRsh16x8_0(v)
case OpRsh32Ux16:
return rewriteValue386_OpRsh32Ux16_0(v)
case OpRsh32Ux32:
return rewriteValue386_OpRsh32Ux32_0(v)
case OpRsh32Ux64:
return rewriteValue386_OpRsh32Ux64_0(v)
case OpRsh32Ux8:
return rewriteValue386_OpRsh32Ux8_0(v)
case OpRsh32x16:
return rewriteValue386_OpRsh32x16_0(v)
case OpRsh32x32:
return rewriteValue386_OpRsh32x32_0(v)
case OpRsh32x64:
return rewriteValue386_OpRsh32x64_0(v)
case OpRsh32x8:
return rewriteValue386_OpRsh32x8_0(v)
case OpRsh8Ux16:
return rewriteValue386_OpRsh8Ux16_0(v)
case OpRsh8Ux32:
return rewriteValue386_OpRsh8Ux32_0(v)
case OpRsh8Ux64:
return rewriteValue386_OpRsh8Ux64_0(v)
case OpRsh8Ux8:
return rewriteValue386_OpRsh8Ux8_0(v)
case OpRsh8x16:
return rewriteValue386_OpRsh8x16_0(v)
case OpRsh8x32:
return rewriteValue386_OpRsh8x32_0(v)
case OpRsh8x64:
return rewriteValue386_OpRsh8x64_0(v)
case OpRsh8x8:
return rewriteValue386_OpRsh8x8_0(v)
case OpSelect0:
return rewriteValue386_OpSelect0_0(v)
case OpSelect1:
return rewriteValue386_OpSelect1_0(v)
case OpSignExt16to32:
return rewriteValue386_OpSignExt16to32_0(v)
case OpSignExt8to16:
return rewriteValue386_OpSignExt8to16_0(v)
case OpSignExt8to32:
return rewriteValue386_OpSignExt8to32_0(v)
case OpSignmask:
return rewriteValue386_OpSignmask_0(v)
case OpSlicemask:
return rewriteValue386_OpSlicemask_0(v)
case OpSqrt:
return rewriteValue386_OpSqrt_0(v)
case OpStaticCall:
return rewriteValue386_OpStaticCall_0(v)
case OpStore:
return rewriteValue386_OpStore_0(v)
case OpSub16:
return rewriteValue386_OpSub16_0(v)
case OpSub32:
return rewriteValue386_OpSub32_0(v)
case OpSub32F:
return rewriteValue386_OpSub32F_0(v)
case OpSub32carry:
return rewriteValue386_OpSub32carry_0(v)
case OpSub32withcarry:
return rewriteValue386_OpSub32withcarry_0(v)
case OpSub64F:
return rewriteValue386_OpSub64F_0(v)
case OpSub8:
return rewriteValue386_OpSub8_0(v)
case OpSubPtr:
return rewriteValue386_OpSubPtr_0(v)
case OpTrunc16to8:
return rewriteValue386_OpTrunc16to8_0(v)
case OpTrunc32to16:
return rewriteValue386_OpTrunc32to16_0(v)
case OpTrunc32to8:
return rewriteValue386_OpTrunc32to8_0(v)
case OpWB:
return rewriteValue386_OpWB_0(v)
case OpXor16:
return rewriteValue386_OpXor16_0(v)
case OpXor32:
return rewriteValue386_OpXor32_0(v)
case OpXor8:
return rewriteValue386_OpXor8_0(v)
case OpZero:
return rewriteValue386_OpZero_0(v) || rewriteValue386_OpZero_10(v)
case OpZeroExt16to32:
return rewriteValue386_OpZeroExt16to32_0(v)
case OpZeroExt8to16:
return rewriteValue386_OpZeroExt8to16_0(v)
case OpZeroExt8to32:
return rewriteValue386_OpZeroExt8to32_0(v)
case OpZeromask:
return rewriteValue386_OpZeromask_0(v)
}
return false
}
func rewriteValue386_Op386ADCL_0(v *Value) bool {
// match: (ADCL x (MOVLconst [c]) f)
// result: (ADCLconst [c] x f)
for {
f := v.Args[2]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386ADCLconst)
v.AuxInt = c
v.AddArg(x)
v.AddArg(f)
return true
}
// match: (ADCL (MOVLconst [c]) x f)
// result: (ADCLconst [c] x f)
for {
f := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
x := v.Args[1]
v.reset(Op386ADCLconst)
v.AuxInt = c
v.AddArg(x)
v.AddArg(f)
return true
}
// match: (ADCL (MOVLconst [c]) x f)
// result: (ADCLconst [c] x f)
for {
f := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
x := v.Args[1]
v.reset(Op386ADCLconst)
v.AuxInt = c
v.AddArg(x)
v.AddArg(f)
return true
}
// match: (ADCL x (MOVLconst [c]) f)
// result: (ADCLconst [c] x f)
for {
f := v.Args[2]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386ADCLconst)
v.AuxInt = c
v.AddArg(x)
v.AddArg(f)
return true
}
return false
}
func rewriteValue386_Op386ADDL_0(v *Value) bool {
// match: (ADDL x (MOVLconst [c]))
// result: (ADDLconst [c] x)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386ADDLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL (MOVLconst [c]) x)
// result: (ADDLconst [c] x)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386ADDLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL (SHLLconst [c] x) (SHRLconst [d] x))
// cond: d == 32-c
// result: (ROLLconst [c] x)
for {
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst {
break
}
c := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHRLconst {
break
}
d := v_1.AuxInt
if x != v_1.Args[0] || !(d == 32-c) {
break
}
v.reset(Op386ROLLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL (SHRLconst [d] x) (SHLLconst [c] x))
// cond: d == 32-c
// result: (ROLLconst [c] x)
for {
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHRLconst {
break
}
d := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst {
break
}
c := v_1.AuxInt
if x != v_1.Args[0] || !(d == 32-c) {
break
}
v.reset(Op386ROLLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL <t> (SHLLconst x [c]) (SHRWconst x [d]))
// cond: c < 16 && d == 16-c && t.Size() == 2
// result: (ROLWconst x [c])
for {
t := v.Type
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst {
break
}
c := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHRWconst {
break
}
d := v_1.AuxInt
if x != v_1.Args[0] || !(c < 16 && d == 16-c && t.Size() == 2) {
break
}
v.reset(Op386ROLWconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL <t> (SHRWconst x [d]) (SHLLconst x [c]))
// cond: c < 16 && d == 16-c && t.Size() == 2
// result: (ROLWconst x [c])
for {
t := v.Type
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHRWconst {
break
}
d := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst {
break
}
c := v_1.AuxInt
if x != v_1.Args[0] || !(c < 16 && d == 16-c && t.Size() == 2) {
break
}
v.reset(Op386ROLWconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL <t> (SHLLconst x [c]) (SHRBconst x [d]))
// cond: c < 8 && d == 8-c && t.Size() == 1
// result: (ROLBconst x [c])
for {
t := v.Type
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst {
break
}
c := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHRBconst {
break
}
d := v_1.AuxInt
if x != v_1.Args[0] || !(c < 8 && d == 8-c && t.Size() == 1) {
break
}
v.reset(Op386ROLBconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL <t> (SHRBconst x [d]) (SHLLconst x [c]))
// cond: c < 8 && d == 8-c && t.Size() == 1
// result: (ROLBconst x [c])
for {
t := v.Type
_ = v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHRBconst {
break
}
d := v_0.AuxInt
x := v_0.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst {
break
}
c := v_1.AuxInt
if x != v_1.Args[0] || !(c < 8 && d == 8-c && t.Size() == 1) {
break
}
v.reset(Op386ROLBconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDL x (SHLLconst [3] y))
// result: (LEAL8 x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst || v_1.AuxInt != 3 {
break
}
y := v_1.Args[0]
v.reset(Op386LEAL8)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (SHLLconst [3] y) x)
// result: (LEAL8 x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst || v_0.AuxInt != 3 {
break
}
y := v_0.Args[0]
v.reset(Op386LEAL8)
v.AddArg(x)
v.AddArg(y)
return true
}
return false
}
func rewriteValue386_Op386ADDL_10(v *Value) bool {
// match: (ADDL x (SHLLconst [2] y))
// result: (LEAL4 x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst || v_1.AuxInt != 2 {
break
}
y := v_1.Args[0]
v.reset(Op386LEAL4)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (SHLLconst [2] y) x)
// result: (LEAL4 x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst || v_0.AuxInt != 2 {
break
}
y := v_0.Args[0]
v.reset(Op386LEAL4)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL x (SHLLconst [1] y))
// result: (LEAL2 x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386SHLLconst || v_1.AuxInt != 1 {
break
}
y := v_1.Args[0]
v.reset(Op386LEAL2)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (SHLLconst [1] y) x)
// result: (LEAL2 x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386SHLLconst || v_0.AuxInt != 1 {
break
}
y := v_0.Args[0]
v.reset(Op386LEAL2)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL x (ADDL y y))
// result: (LEAL2 x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDL {
break
}
y := v_1.Args[1]
if y != v_1.Args[0] {
break
}
v.reset(Op386LEAL2)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (ADDL y y) x)
// result: (LEAL2 x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDL {
break
}
y := v_0.Args[1]
if y != v_0.Args[0] {
break
}
v.reset(Op386LEAL2)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL x (ADDL x y))
// result: (LEAL2 y x)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDL {
break
}
y := v_1.Args[1]
if x != v_1.Args[0] {
break
}
v.reset(Op386LEAL2)
v.AddArg(y)
v.AddArg(x)
return true
}
// match: (ADDL x (ADDL y x))
// result: (LEAL2 y x)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDL {
break
}
_ = v_1.Args[1]
y := v_1.Args[0]
if x != v_1.Args[1] {
break
}
v.reset(Op386LEAL2)
v.AddArg(y)
v.AddArg(x)
return true
}
// match: (ADDL (ADDL x y) x)
// result: (LEAL2 y x)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDL {
break
}
y := v_0.Args[1]
if x != v_0.Args[0] {
break
}
v.reset(Op386LEAL2)
v.AddArg(y)
v.AddArg(x)
return true
}
// match: (ADDL (ADDL y x) x)
// result: (LEAL2 y x)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDL {
break
}
_ = v_0.Args[1]
y := v_0.Args[0]
if x != v_0.Args[1] {
break
}
v.reset(Op386LEAL2)
v.AddArg(y)
v.AddArg(x)
return true
}
return false
}
func rewriteValue386_Op386ADDL_20(v *Value) bool {
// match: (ADDL (ADDLconst [c] x) y)
// result: (LEAL1 [c] x y)
for {
y := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
c := v_0.AuxInt
x := v_0.Args[0]
v.reset(Op386LEAL1)
v.AuxInt = c
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL y (ADDLconst [c] x))
// result: (LEAL1 [c] x y)
for {
_ = v.Args[1]
y := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
c := v_1.AuxInt
x := v_1.Args[0]
v.reset(Op386LEAL1)
v.AuxInt = c
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL x (LEAL [c] {s} y))
// cond: x.Op != OpSB && y.Op != OpSB
// result: (LEAL1 [c] {s} x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
c := v_1.AuxInt
s := v_1.Aux
y := v_1.Args[0]
if !(x.Op != OpSB && y.Op != OpSB) {
break
}
v.reset(Op386LEAL1)
v.AuxInt = c
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (LEAL [c] {s} y) x)
// cond: x.Op != OpSB && y.Op != OpSB
// result: (LEAL1 [c] {s} x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
c := v_0.AuxInt
s := v_0.Aux
y := v_0.Args[0]
if !(x.Op != OpSB && y.Op != OpSB) {
break
}
v.reset(Op386LEAL1)
v.AuxInt = c
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ADDLload x [off] {sym} ptr mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ADDLload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ADDL l:(MOVLload [off] {sym} ptr mem) x)
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ADDLload x [off] {sym} ptr mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ADDLload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ADDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVLloadidx4 {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[2]
ptr := l.Args[0]
idx := l.Args[1]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ADDLloadidx4 x [off] {sym} ptr idx mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVLloadidx4 {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[2]
ptr := l.Args[0]
idx := l.Args[1]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDL x (NEGL y))
// result: (SUBL x y)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386NEGL {
break
}
y := v_1.Args[0]
v.reset(Op386SUBL)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDL (NEGL y) x)
// result: (SUBL x y)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386NEGL {
break
}
y := v_0.Args[0]
v.reset(Op386SUBL)
v.AddArg(x)
v.AddArg(y)
return true
}
return false
}
func rewriteValue386_Op386ADDLcarry_0(v *Value) bool {
// match: (ADDLcarry x (MOVLconst [c]))
// result: (ADDLconstcarry [c] x)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386ADDLconstcarry)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ADDLcarry (MOVLconst [c]) x)
// result: (ADDLconstcarry [c] x)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386ADDLconstcarry)
v.AuxInt = c
v.AddArg(x)
return true
}
return false
}
func rewriteValue386_Op386ADDLconst_0(v *Value) bool {
// match: (ADDLconst [c] (ADDL x y))
// result: (LEAL1 [c] x y)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386ADDL {
break
}
y := v_0.Args[1]
x := v_0.Args[0]
v.reset(Op386LEAL1)
v.AuxInt = c
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDLconst [c] (LEAL [d] {s} x))
// cond: is32Bit(c+d)
// result: (LEAL [c+d] {s} x)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
d := v_0.AuxInt
s := v_0.Aux
x := v_0.Args[0]
if !(is32Bit(c + d)) {
break
}
v.reset(Op386LEAL)
v.AuxInt = c + d
v.Aux = s
v.AddArg(x)
return true
}
// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
// cond: is32Bit(c+d)
// result: (LEAL1 [c+d] {s} x y)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386LEAL1 {
break
}
d := v_0.AuxInt
s := v_0.Aux
y := v_0.Args[1]
x := v_0.Args[0]
if !(is32Bit(c + d)) {
break
}
v.reset(Op386LEAL1)
v.AuxInt = c + d
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
// cond: is32Bit(c+d)
// result: (LEAL2 [c+d] {s} x y)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386LEAL2 {
break
}
d := v_0.AuxInt
s := v_0.Aux
y := v_0.Args[1]
x := v_0.Args[0]
if !(is32Bit(c + d)) {
break
}
v.reset(Op386LEAL2)
v.AuxInt = c + d
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
// cond: is32Bit(c+d)
// result: (LEAL4 [c+d] {s} x y)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386LEAL4 {
break
}
d := v_0.AuxInt
s := v_0.Aux
y := v_0.Args[1]
x := v_0.Args[0]
if !(is32Bit(c + d)) {
break
}
v.reset(Op386LEAL4)
v.AuxInt = c + d
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
// cond: is32Bit(c+d)
// result: (LEAL8 [c+d] {s} x y)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386LEAL8 {
break
}
d := v_0.AuxInt
s := v_0.Aux
y := v_0.Args[1]
x := v_0.Args[0]
if !(is32Bit(c + d)) {
break
}
v.reset(Op386LEAL8)
v.AuxInt = c + d
v.Aux = s
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (ADDLconst [c] x)
// cond: int32(c)==0
// result: x
for {
c := v.AuxInt
x := v.Args[0]
if !(int32(c) == 0) {
break
}
v.reset(OpCopy)
v.Type = x.Type
v.AddArg(x)
return true
}
// match: (ADDLconst [c] (MOVLconst [d]))
// result: (MOVLconst [int64(int32(c+d))])
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
d := v_0.AuxInt
v.reset(Op386MOVLconst)
v.AuxInt = int64(int32(c + d))
return true
}
// match: (ADDLconst [c] (ADDLconst [d] x))
// result: (ADDLconst [int64(int32(c+d))] x)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
d := v_0.AuxInt
x := v_0.Args[0]
v.reset(Op386ADDLconst)
v.AuxInt = int64(int32(c + d))
v.AddArg(x)
return true
}
return false
}
func rewriteValue386_Op386ADDLconstmodify_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
// cond: ValAndOff(valoff1).canAdd(off2)
// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
if !(ValAndOff(valoff1).canAdd(off2)) {
break
}
v.reset(Op386ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ADDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
for {
valoff1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDLconstmodifyidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
// cond: ValAndOff(valoff1).canAdd(off2)
// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
idx := v.Args[1]
if !(ValAndOff(valoff1).canAdd(off2)) {
break
}
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
// cond: ValAndOff(valoff1).canAdd(off2*4)
// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
base := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
idx := v_1.Args[0]
if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
break
}
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
for {
valoff1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
idx := v.Args[1]
if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDLload_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLload [off1] {sym} val (ADDLconst [off2] base) mem)
// cond: is32Bit(off1+off2)
// result: (ADDLload [off1+off2] {sym} val base mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDLload)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ADDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ADDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL4 {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
idx := v_1.Args[1]
ptr := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDLloadidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
// cond: is32Bit(off1+off2)
// result: (ADDLloadidx4 [off1+off2] {sym} val base idx mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
idx := v.Args[2]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
// cond: is32Bit(off1+off2*4)
// result: (ADDLloadidx4 [off1+off2*4] {sym} val base idx mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
val := v.Args[0]
base := v.Args[1]
v_2 := v.Args[2]
if v_2.Op != Op386ADDLconst {
break
}
off2 := v_2.AuxInt
idx := v_2.Args[0]
if !(is32Bit(off1 + off2*4)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ADDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[3]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
idx := v.Args[2]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDLmodify_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
// cond: is32Bit(off1+off2)
// result: (ADDLmodify [off1+off2] {sym} base val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
val := v.Args[1]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(base)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ADDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
val := v.Args[1]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(val)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDLmodifyidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
// cond: is32Bit(off1+off2)
// result: (ADDLmodifyidx4 [off1+off2] {sym} base idx val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
idx := v.Args[1]
val := v.Args[2]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ADDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
// cond: is32Bit(off1+off2*4)
// result: (ADDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
base := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
idx := v_1.Args[0]
val := v.Args[2]
if !(is32Bit(off1 + off2*4)) {
break
}
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ADDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[3]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
idx := v.Args[1]
val := v.Args[2]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ADDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
// cond: validValAndOff(c,off)
// result: (ADDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
for {
off := v.AuxInt
sym := v.Aux
mem := v.Args[3]
ptr := v.Args[0]
idx := v.Args[1]
v_2 := v.Args[2]
if v_2.Op != Op386MOVLconst {
break
}
c := v_2.AuxInt
if !(validValAndOff(c, off)) {
break
}
v.reset(Op386ADDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDSD_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
// result: (ADDSDload x [off] {sym} ptr mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVSDload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
break
}
v.reset(Op386ADDSDload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ADDSD l:(MOVSDload [off] {sym} ptr mem) x)
// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
// result: (ADDSDload x [off] {sym} ptr mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVSDload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
break
}
v.reset(Op386ADDSDload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDSDload_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDSDload [off1] {sym} val (ADDLconst [off2] base) mem)
// cond: is32Bit(off1+off2)
// result: (ADDSDload [off1+off2] {sym} val base mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDSDload)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ADDSDload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDSDload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDSDload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDSS_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
// result: (ADDSSload x [off] {sym} ptr mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVSSload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
break
}
v.reset(Op386ADDSSload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ADDSS l:(MOVSSload [off] {sym} ptr mem) x)
// cond: canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)
// result: (ADDSSload x [off] {sym} ptr mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVSSload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && !config.use387 && clobber(l)) {
break
}
v.reset(Op386ADDSSload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ADDSSload_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ADDSSload [off1] {sym} val (ADDLconst [off2] base) mem)
// cond: is32Bit(off1+off2)
// result: (ADDSSload [off1+off2] {sym} val base mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ADDSSload)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ADDSSload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ADDSSload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ADDSSload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDL_0(v *Value) bool {
// match: (ANDL x (MOVLconst [c]))
// result: (ANDLconst [c] x)
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386ANDLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ANDL (MOVLconst [c]) x)
// result: (ANDLconst [c] x)
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386ANDLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ANDLload x [off] {sym} ptr mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ANDLload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ANDL l:(MOVLload [off] {sym} ptr mem) x)
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ANDLload x [off] {sym} ptr mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ANDLload)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(mem)
return true
}
// match: (ANDL x l:(MOVLloadidx4 [off] {sym} ptr idx mem))
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVLloadidx4 {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[2]
ptr := l.Args[0]
idx := l.Args[1]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDL l:(MOVLloadidx4 [off] {sym} ptr idx mem) x)
// cond: canMergeLoadClobber(v, l, x) && clobber(l)
// result: (ANDLloadidx4 x [off] {sym} ptr idx mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVLloadidx4 {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[2]
ptr := l.Args[0]
idx := l.Args[1]
if !(canMergeLoadClobber(v, l, x) && clobber(l)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off
v.Aux = sym
v.AddArg(x)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDL x x)
// result: x
for {
x := v.Args[1]
if x != v.Args[0] {
break
}
v.reset(OpCopy)
v.Type = x.Type
v.AddArg(x)
return true
}
return false
}
func rewriteValue386_Op386ANDLconst_0(v *Value) bool {
// match: (ANDLconst [c] (ANDLconst [d] x))
// result: (ANDLconst [c & d] x)
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386ANDLconst {
break
}
d := v_0.AuxInt
x := v_0.Args[0]
v.reset(Op386ANDLconst)
v.AuxInt = c & d
v.AddArg(x)
return true
}
// match: (ANDLconst [c] _)
// cond: int32(c)==0
// result: (MOVLconst [0])
for {
c := v.AuxInt
if !(int32(c) == 0) {
break
}
v.reset(Op386MOVLconst)
v.AuxInt = 0
return true
}
// match: (ANDLconst [c] x)
// cond: int32(c)==-1
// result: x
for {
c := v.AuxInt
x := v.Args[0]
if !(int32(c) == -1) {
break
}
v.reset(OpCopy)
v.Type = x.Type
v.AddArg(x)
return true
}
// match: (ANDLconst [c] (MOVLconst [d]))
// result: (MOVLconst [c&d])
for {
c := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
d := v_0.AuxInt
v.reset(Op386MOVLconst)
v.AuxInt = c & d
return true
}
return false
}
func rewriteValue386_Op386ANDLconstmodify_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLconstmodify [valoff1] {sym} (ADDLconst [off2] base) mem)
// cond: ValAndOff(valoff1).canAdd(off2)
// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {sym} base mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
if !(ValAndOff(valoff1).canAdd(off2)) {
break
}
v.reset(Op386ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ANDLconstmodify [valoff1] {sym1} (LEAL [off2] {sym2} base) mem)
// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLconstmodify [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base mem)
for {
valoff1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLconstmodify)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDLconstmodifyidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLconstmodifyidx4 [valoff1] {sym} (ADDLconst [off2] base) idx mem)
// cond: ValAndOff(valoff1).canAdd(off2)
// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {sym} base idx mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
idx := v.Args[1]
if !(ValAndOff(valoff1).canAdd(off2)) {
break
}
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDLconstmodifyidx4 [valoff1] {sym} base (ADDLconst [off2] idx) mem)
// cond: ValAndOff(valoff1).canAdd(off2*4)
// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2*4)] {sym} base idx mem)
for {
valoff1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
base := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
idx := v_1.Args[0]
if !(ValAndOff(valoff1).canAdd(off2 * 4)) {
break
}
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2 * 4)
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDLconstmodifyidx4 [valoff1] {sym1} (LEAL [off2] {sym2} base) idx mem)
// cond: ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLconstmodifyidx4 [ValAndOff(valoff1).add(off2)] {mergeSym(sym1,sym2)} base idx mem)
for {
valoff1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
idx := v.Args[1]
if !(ValAndOff(valoff1).canAdd(off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = ValAndOff(valoff1).add(off2)
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDLload_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLload [off1] {sym} val (ADDLconst [off2] base) mem)
// cond: is32Bit(off1+off2)
// result: (ANDLload [off1+off2] {sym} val base mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ANDLload)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ANDLload [off1] {sym1} val (LEAL [off2] {sym2} base) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLload [off1+off2] {mergeSym(sym1,sym2)} val base mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLload)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(mem)
return true
}
// match: (ANDLload [off1] {sym1} val (LEAL4 [off2] {sym2} ptr idx) mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2)
// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val ptr idx mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL4 {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
idx := v_1.Args[1]
ptr := v_1.Args[0]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDLloadidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLloadidx4 [off1] {sym} val (ADDLconst [off2] base) idx mem)
// cond: is32Bit(off1+off2)
// result: (ANDLloadidx4 [off1+off2] {sym} val base idx mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
base := v_1.Args[0]
idx := v.Args[2]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDLloadidx4 [off1] {sym} val base (ADDLconst [off2] idx) mem)
// cond: is32Bit(off1+off2*4)
// result: (ANDLloadidx4 [off1+off2*4] {sym} val base idx mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
val := v.Args[0]
base := v.Args[1]
v_2 := v.Args[2]
if v_2.Op != Op386ADDLconst {
break
}
off2 := v_2.AuxInt
idx := v_2.Args[0]
if !(is32Bit(off1 + off2*4)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
// match: (ANDLloadidx4 [off1] {sym1} val (LEAL [off2] {sym2} base) idx mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLloadidx4 [off1+off2] {mergeSym(sym1,sym2)} val base idx mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[3]
val := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386LEAL {
break
}
off2 := v_1.AuxInt
sym2 := v_1.Aux
base := v_1.Args[0]
idx := v.Args[2]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLloadidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(val)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDLmodify_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLmodify [off1] {sym} (ADDLconst [off2] base) val mem)
// cond: is32Bit(off1+off2)
// result: (ANDLmodify [off1+off2] {sym} base val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
val := v.Args[1]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(base)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ANDLmodify [off1] {sym1} (LEAL [off2] {sym2} base) val mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLmodify [off1+off2] {mergeSym(sym1,sym2)} base val mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[2]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
val := v.Args[1]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLmodify)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(val)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386ANDLmodifyidx4_0(v *Value) bool {
b := v.Block
config := b.Func.Config
// match: (ANDLmodifyidx4 [off1] {sym} (ADDLconst [off2] base) idx val mem)
// cond: is32Bit(off1+off2)
// result: (ANDLmodifyidx4 [off1+off2] {sym} base idx val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
v_0 := v.Args[0]
if v_0.Op != Op386ADDLconst {
break
}
off2 := v_0.AuxInt
base := v_0.Args[0]
idx := v.Args[1]
val := v.Args[2]
if !(is32Bit(off1 + off2)) {
break
}
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ANDLmodifyidx4 [off1] {sym} base (ADDLconst [off2] idx) val mem)
// cond: is32Bit(off1+off2*4)
// result: (ANDLmodifyidx4 [off1+off2*4] {sym} base idx val mem)
for {
off1 := v.AuxInt
sym := v.Aux
mem := v.Args[3]
base := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386ADDLconst {
break
}
off2 := v_1.AuxInt
idx := v_1.Args[0]
val := v.Args[2]
if !(is32Bit(off1 + off2*4)) {
break
}
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2*4
v.Aux = sym
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ANDLmodifyidx4 [off1] {sym1} (LEAL [off2] {sym2} base) idx val mem)
// cond: is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)
// result: (ANDLmodifyidx4 [off1+off2] {mergeSym(sym1,sym2)} base idx val mem)
for {
off1 := v.AuxInt
sym1 := v.Aux
mem := v.Args[3]
v_0 := v.Args[0]
if v_0.Op != Op386LEAL {
break
}
off2 := v_0.AuxInt
sym2 := v_0.Aux
base := v_0.Args[0]
idx := v.Args[1]
val := v.Args[2]
if !(is32Bit(off1+off2) && canMergeSym(sym1, sym2) && (base.Op != OpSB || !config.ctxt.Flag_shared)) {
break
}
v.reset(Op386ANDLmodifyidx4)
v.AuxInt = off1 + off2
v.Aux = mergeSym(sym1, sym2)
v.AddArg(base)
v.AddArg(idx)
v.AddArg(val)
v.AddArg(mem)
return true
}
// match: (ANDLmodifyidx4 [off] {sym} ptr idx (MOVLconst [c]) mem)
// cond: validValAndOff(c,off)
// result: (ANDLconstmodifyidx4 [makeValAndOff(c,off)] {sym} ptr idx mem)
for {
off := v.AuxInt
sym := v.Aux
mem := v.Args[3]
ptr := v.Args[0]
idx := v.Args[1]
v_2 := v.Args[2]
if v_2.Op != Op386MOVLconst {
break
}
c := v_2.AuxInt
if !(validValAndOff(c, off)) {
break
}
v.reset(Op386ANDLconstmodifyidx4)
v.AuxInt = makeValAndOff(c, off)
v.Aux = sym
v.AddArg(ptr)
v.AddArg(idx)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386CMPB_0(v *Value) bool {
b := v.Block
// match: (CMPB x (MOVLconst [c]))
// result: (CMPBconst x [int64(int8(c))])
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386CMPBconst)
v.AuxInt = int64(int8(c))
v.AddArg(x)
return true
}
// match: (CMPB (MOVLconst [c]) x)
// result: (InvertFlags (CMPBconst x [int64(int8(c))]))
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPBconst, types.TypeFlags)
v0.AuxInt = int64(int8(c))
v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
// cond: canMergeLoad(v, l) && clobber(l)
// result: (CMPBload {sym} [off] ptr x mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVBload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoad(v, l) && clobber(l)) {
break
}
v.reset(Op386CMPBload)
v.AuxInt = off
v.Aux = sym
v.AddArg(ptr)
v.AddArg(x)
v.AddArg(mem)
return true
}
// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
// cond: canMergeLoad(v, l) && clobber(l)
// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVBload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoad(v, l) && clobber(l)) {
break
}
v.reset(Op386InvertFlags)
v0 := b.NewValue0(l.Pos, Op386CMPBload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
v0.AddArg(ptr)
v0.AddArg(x)
v0.AddArg(mem)
v.AddArg(v0)
return true
}
return false
}
func rewriteValue386_Op386CMPBconst_0(v *Value) bool {
b := v.Block
// match: (CMPBconst (MOVLconst [x]) [y])
// cond: int8(x)==int8(y)
// result: (FlagEQ)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int8(x) == int8(y)) {
break
}
v.reset(Op386FlagEQ)
return true
}
// match: (CMPBconst (MOVLconst [x]) [y])
// cond: int8(x)<int8(y) && uint8(x)<uint8(y)
// result: (FlagLT_ULT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int8(x) < int8(y) && uint8(x) < uint8(y)) {
break
}
v.reset(Op386FlagLT_ULT)
return true
}
// match: (CMPBconst (MOVLconst [x]) [y])
// cond: int8(x)<int8(y) && uint8(x)>uint8(y)
// result: (FlagLT_UGT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int8(x) < int8(y) && uint8(x) > uint8(y)) {
break
}
v.reset(Op386FlagLT_UGT)
return true
}
// match: (CMPBconst (MOVLconst [x]) [y])
// cond: int8(x)>int8(y) && uint8(x)<uint8(y)
// result: (FlagGT_ULT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int8(x) > int8(y) && uint8(x) < uint8(y)) {
break
}
v.reset(Op386FlagGT_ULT)
return true
}
// match: (CMPBconst (MOVLconst [x]) [y])
// cond: int8(x)>int8(y) && uint8(x)>uint8(y)
// result: (FlagGT_UGT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int8(x) > int8(y) && uint8(x) > uint8(y)) {
break
}
v.reset(Op386FlagGT_UGT)
return true
}
// match: (CMPBconst (ANDLconst _ [m]) [n])
// cond: 0 <= int8(m) && int8(m) < int8(n)
// result: (FlagLT_ULT)
for {
n := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386ANDLconst {
break
}
m := v_0.AuxInt
if !(0 <= int8(m) && int8(m) < int8(n)) {
break
}
v.reset(Op386FlagLT_ULT)
return true
}
// match: (CMPBconst l:(ANDL x y) [0])
// cond: l.Uses==1
// result: (TESTB x y)
for {
if v.AuxInt != 0 {
break
}
l := v.Args[0]
if l.Op != Op386ANDL {
break
}
y := l.Args[1]
x := l.Args[0]
if !(l.Uses == 1) {
break
}
v.reset(Op386TESTB)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (CMPBconst l:(ANDLconst [c] x) [0])
// cond: l.Uses==1
// result: (TESTBconst [int64(int8(c))] x)
for {
if v.AuxInt != 0 {
break
}
l := v.Args[0]
if l.Op != Op386ANDLconst {
break
}
c := l.AuxInt
x := l.Args[0]
if !(l.Uses == 1) {
break
}
v.reset(Op386TESTBconst)
v.AuxInt = int64(int8(c))
v.AddArg(x)
return true
}
// match: (CMPBconst x [0])
// result: (TESTB x x)
for {
if v.AuxInt != 0 {
break
}
x := v.Args[0]
v.reset(Op386TESTB)
v.AddArg(x)
v.AddArg(x)
return true
}
// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
// result: @l.Block (CMPBconstload {sym} [makeValAndOff(c,off)] ptr mem)
for {
c := v.AuxInt
l := v.Args[0]
if l.Op != Op386MOVBload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
break
}
b = l.Block
v0 := b.NewValue0(l.Pos, Op386CMPBconstload, types.TypeFlags)
v.reset(OpCopy)
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
v0.AddArg(ptr)
v0.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386CMPBload_0(v *Value) bool {
// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
// cond: validValAndOff(int64(int8(c)),off)
// result: (CMPBconstload {sym} [makeValAndOff(int64(int8(c)),off)] ptr mem)
for {
off := v.AuxInt
sym := v.Aux
mem := v.Args[2]
ptr := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
if !(validValAndOff(int64(int8(c)), off)) {
break
}
v.reset(Op386CMPBconstload)
v.AuxInt = makeValAndOff(int64(int8(c)), off)
v.Aux = sym
v.AddArg(ptr)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386CMPL_0(v *Value) bool {
b := v.Block
// match: (CMPL x (MOVLconst [c]))
// result: (CMPLconst x [c])
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386CMPLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (CMPL (MOVLconst [c]) x)
// result: (InvertFlags (CMPLconst x [c]))
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPLconst, types.TypeFlags)
v0.AuxInt = c
v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
// cond: canMergeLoad(v, l) && clobber(l)
// result: (CMPLload {sym} [off] ptr x mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoad(v, l) && clobber(l)) {
break
}
v.reset(Op386CMPLload)
v.AuxInt = off
v.Aux = sym
v.AddArg(ptr)
v.AddArg(x)
v.AddArg(mem)
return true
}
// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
// cond: canMergeLoad(v, l) && clobber(l)
// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoad(v, l) && clobber(l)) {
break
}
v.reset(Op386InvertFlags)
v0 := b.NewValue0(l.Pos, Op386CMPLload, types.TypeFlags)
v0.AuxInt = off
v0.Aux = sym
v0.AddArg(ptr)
v0.AddArg(x)
v0.AddArg(mem)
v.AddArg(v0)
return true
}
return false
}
func rewriteValue386_Op386CMPLconst_0(v *Value) bool {
// match: (CMPLconst (MOVLconst [x]) [y])
// cond: int32(x)==int32(y)
// result: (FlagEQ)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int32(x) == int32(y)) {
break
}
v.reset(Op386FlagEQ)
return true
}
// match: (CMPLconst (MOVLconst [x]) [y])
// cond: int32(x)<int32(y) && uint32(x)<uint32(y)
// result: (FlagLT_ULT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int32(x) < int32(y) && uint32(x) < uint32(y)) {
break
}
v.reset(Op386FlagLT_ULT)
return true
}
// match: (CMPLconst (MOVLconst [x]) [y])
// cond: int32(x)<int32(y) && uint32(x)>uint32(y)
// result: (FlagLT_UGT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int32(x) < int32(y) && uint32(x) > uint32(y)) {
break
}
v.reset(Op386FlagLT_UGT)
return true
}
// match: (CMPLconst (MOVLconst [x]) [y])
// cond: int32(x)>int32(y) && uint32(x)<uint32(y)
// result: (FlagGT_ULT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int32(x) > int32(y) && uint32(x) < uint32(y)) {
break
}
v.reset(Op386FlagGT_ULT)
return true
}
// match: (CMPLconst (MOVLconst [x]) [y])
// cond: int32(x)>int32(y) && uint32(x)>uint32(y)
// result: (FlagGT_UGT)
for {
y := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
x := v_0.AuxInt
if !(int32(x) > int32(y) && uint32(x) > uint32(y)) {
break
}
v.reset(Op386FlagGT_UGT)
return true
}
// match: (CMPLconst (SHRLconst _ [c]) [n])
// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
// result: (FlagLT_ULT)
for {
n := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386SHRLconst {
break
}
c := v_0.AuxInt
if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
break
}
v.reset(Op386FlagLT_ULT)
return true
}
// match: (CMPLconst (ANDLconst _ [m]) [n])
// cond: 0 <= int32(m) && int32(m) < int32(n)
// result: (FlagLT_ULT)
for {
n := v.AuxInt
v_0 := v.Args[0]
if v_0.Op != Op386ANDLconst {
break
}
m := v_0.AuxInt
if !(0 <= int32(m) && int32(m) < int32(n)) {
break
}
v.reset(Op386FlagLT_ULT)
return true
}
// match: (CMPLconst l:(ANDL x y) [0])
// cond: l.Uses==1
// result: (TESTL x y)
for {
if v.AuxInt != 0 {
break
}
l := v.Args[0]
if l.Op != Op386ANDL {
break
}
y := l.Args[1]
x := l.Args[0]
if !(l.Uses == 1) {
break
}
v.reset(Op386TESTL)
v.AddArg(x)
v.AddArg(y)
return true
}
// match: (CMPLconst l:(ANDLconst [c] x) [0])
// cond: l.Uses==1
// result: (TESTLconst [c] x)
for {
if v.AuxInt != 0 {
break
}
l := v.Args[0]
if l.Op != Op386ANDLconst {
break
}
c := l.AuxInt
x := l.Args[0]
if !(l.Uses == 1) {
break
}
v.reset(Op386TESTLconst)
v.AuxInt = c
v.AddArg(x)
return true
}
// match: (CMPLconst x [0])
// result: (TESTL x x)
for {
if v.AuxInt != 0 {
break
}
x := v.Args[0]
v.reset(Op386TESTL)
v.AddArg(x)
v.AddArg(x)
return true
}
return false
}
func rewriteValue386_Op386CMPLconst_10(v *Value) bool {
b := v.Block
// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
// cond: l.Uses == 1 && validValAndOff(c, off) && clobber(l)
// result: @l.Block (CMPLconstload {sym} [makeValAndOff(c,off)] ptr mem)
for {
c := v.AuxInt
l := v.Args[0]
if l.Op != Op386MOVLload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(l.Uses == 1 && validValAndOff(c, off) && clobber(l)) {
break
}
b = l.Block
v0 := b.NewValue0(l.Pos, Op386CMPLconstload, types.TypeFlags)
v.reset(OpCopy)
v.AddArg(v0)
v0.AuxInt = makeValAndOff(c, off)
v0.Aux = sym
v0.AddArg(ptr)
v0.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386CMPLload_0(v *Value) bool {
// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
// cond: validValAndOff(int64(int32(c)),off)
// result: (CMPLconstload {sym} [makeValAndOff(int64(int32(c)),off)] ptr mem)
for {
off := v.AuxInt
sym := v.Aux
mem := v.Args[2]
ptr := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
if !(validValAndOff(int64(int32(c)), off)) {
break
}
v.reset(Op386CMPLconstload)
v.AuxInt = makeValAndOff(int64(int32(c)), off)
v.Aux = sym
v.AddArg(ptr)
v.AddArg(mem)
return true
}
return false
}
func rewriteValue386_Op386CMPW_0(v *Value) bool {
b := v.Block
// match: (CMPW x (MOVLconst [c]))
// result: (CMPWconst x [int64(int16(c))])
for {
_ = v.Args[1]
x := v.Args[0]
v_1 := v.Args[1]
if v_1.Op != Op386MOVLconst {
break
}
c := v_1.AuxInt
v.reset(Op386CMPWconst)
v.AuxInt = int64(int16(c))
v.AddArg(x)
return true
}
// match: (CMPW (MOVLconst [c]) x)
// result: (InvertFlags (CMPWconst x [int64(int16(c))]))
for {
x := v.Args[1]
v_0 := v.Args[0]
if v_0.Op != Op386MOVLconst {
break
}
c := v_0.AuxInt
v.reset(Op386InvertFlags)
v0 := b.NewValue0(v.Pos, Op386CMPWconst, types.TypeFlags)
v0.AuxInt = int64(int16(c))
v0.AddArg(x)
v.AddArg(v0)
return true
}
// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
// cond: canMergeLoad(v, l) && clobber(l)
// result: (CMPWload {sym} [off] ptr x mem)
for {
x := v.Args[1]
l := v.Args[0]
if l.Op != Op386MOVWload {
break
}
off := l.AuxInt
sym := l.Aux
mem := l.Args[1]
ptr := l.Args[0]
if !(canMergeLoad(v, l) && clobber(l)) {
break
}
v.reset(Op386CMPWload)
v.AuxInt = off
v.Aux = sym
v.AddArg(ptr)
v.AddArg(x)
v.AddArg(mem)
return true
}
// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
// cond: canMergeLoad(v, l) && clobber(l)
// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
for {
_ = v.Args[1]
x := v.Args[0]
l := v.Args[1]
if l.Op != Op386MOVWload {
break
}
off := l.AuxInt