As far as I know, gc don't generate conditional move
(or conditonal arithmetic) instructions for any of the
supported architectures directly (in cmd/5g, there is
a predicate pass that try to convert branches to
conditionally executed instructions, but that pass is
not enabled yet [@josharian, if you want to work on
this issue, please take a look at the predicate function
in cmd/5g/peep.go; we might be able to port that
to 8g/6g to make use of cmovcc]).
I think josh has a change to make bgen use setcc on
I imagine it will be easier to use condition move
instructions in the new SSA-based backend with
graph matching based instruction selection.
I watched Aram write a bunch of peephole rules this afternoon, each
totalling 60-70kb reduction in godoc, given we're removing one 32 bit
instruction per rule, that tells you how common these patterns that the
peep optimiser is targeting are.
Do we generate conditional move instructions on i386/amd64?
No, although as @minux said, we will hopefully soon generate SETcc. I'm working on reviving that CL now.
Also, ARM can attach conditions to most instructions, not just MOVs. CMOV also has the pitfall that it unconditionally loads the source from memory; it is only the resulting store than is conditional. These are probably good reasons to make this happen after the initial codegen.
if you want to work on this issue, please take a look at the predicate function in cmd/5g/peep.go; we might be able to port that to 8g/6g to make use of cmovcc
Thanks! I'll take a look, although if this will all be eclipsed by SSA in 1.6, it might not be worth the effort and risk right now. (I'm worried about the same issue w.r.t. to the SETcc work, but I've already done a lot of the work, so I'll see it through.)
totalling 60-70kb reduction in godoc, given we're removing one 32 bit instruction per rule