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cmd/compile: arm64: emit double-register loads and stores in lowering #19715

philhofer opened this issue Mar 25, 2017 · 2 comments


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@philhofer philhofer commented Mar 25, 2017

ARMv8 has "double-register" loads and stores (ldp and stp), which the present SSA backend does not emit.

Since these instructions can accept any general-purpose register (unlike the corresponding ARMv7 instructions ldrd and strd), they shouldn't require any changes to the register allocator in order to get them working. I think things will "just work" if ldp returns a tuple of the loaded values.

In particular, I'd expect this change to make the sequence of instructions preceding and following a call op (with the existing ABI) to be reduced by up to a factor of 2. We can also use stp to zero 16 bytes at once.

The stp rule should be expressible with the existing SSA rewrite rule infrastructure. The ldp rule is more challenging, because there is no way to iterate the uses of a memory value in the rewrite rules. We may have to introduce an architecture-dependent pass just before lower to combine adjacent 4- and 8-byte loads into paired 8- and 16-byte loads.

CC: @williamweixiao I'm happy to take this on, but please let me know if you have similar work planned.


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@williamweixiao williamweixiao commented Mar 27, 2017

I don't plan similar work to optimize arm64 based on "ldp" and "stp". Please go ahead with it!
In the following 3 months, my major work focus on providing arm64 decoder, improving arm64 assembler (especially for SIMD instructions) and optimizing hash/crypto/runtime with SIMD instructions. I may try to make some optimizations based on SSA in the second half of this year.
Anyway, welcome to sync with me about golang arm64 related work!


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@andybons andybons commented Apr 11, 2018

@philhofer how's this work coming?

@andybons andybons added the NeedsFix label Apr 11, 2018
@andybons andybons added this to the Unplanned milestone Apr 11, 2018
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