x/arch/arm/armasm: MSR instruction is not supported

[benshi001]

decode_test.go:66: Decode(01f02ce1|) [plan9] = error: unknown instruction, 0, want MSR R1, CPSR
decode_test.go:66: Decode(fff02ce3|) [plan9] = error: unknown instruction, 0, want MSR $255, CPSR
decode_test.go:66: Decode(fff42ce3|) [plan9] = error: unknown instruction, 0, want MSR $4278190080, CPSR

All those are common ARM instructions, which should be correctly decoded.

[odeke-em]

@benshi001 what package is this issue for? Is it for x/arch/arm/armasm or for cmd/internal/objfile? Could we update the title to something that can easily be groked?
Thanks.

/cc @cherrymui @randall77 @josharian

[benshi001]

01f02ce1|	1	plan9	MSR R1, CPSR
fff02ce3|	1	plan9	MSR $255, CPSR
fff42ce3|	1	plan9	MSR $4278190080, CPSR

add to arm/armasm/testdata/decode.txt

[benshi001]

here is gnu objdump's result

10: e12cf001 msr CPSR_fs, r1
14: e32cfff0 msr CPSR_fs, # 240, 30 ; 0x3c0
18: e32cfff4 msr CPSR_fs, # 244, 30 ; 0x3d0

[cherrymui]

@odeke-em it is x/arch/arm/armasm.

All those are common ARM instructions

They are rarely used in Go. Given that it doesn't disassemble to some other instruction, I would say it is "unsupported" yet, instead of "incorrect".

Does it work in GNU syntax? (I mean, GNU syntax in x/arch/arm/armasm, not GNU objudump).

[benshi001]

No. it is not supported in GNU syntax x/arch/arm/armasm

[benshi001]

The register list order is wrong when decoding QADD/QDADD/QSUB.

0xe1086055 should be decoded to "QADD R6, R8, R5" in GNU syntax, but actually "QADD R6, R5, R8". So do QDADD and QSUB.

[benshi001]

Sorry, I made a mistake again. The QADD/QSUB/QDSUB/QDADD are right in register order. Theirs are indeed different from QADD16/QSUB16/QADD8/QSUB8.