x/arch/x86/x86asm: missing Control-flow Enforcement instructions; e.g. ENDBR64 #35865
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NeedsInvestigation
Someone must examine and confirm this is a valid issue and not a duplicate of an existing one.
Milestone
As a follow-up of #18665, instructions related to Control-flow Enforcement are currently not recognized by the
x/arch/x86
disassembler.Example link at play.golang.org: https://play.golang.org/p/xz6V8cSREWF
At rev golang/arch@368ea8f, the
ENDBR64
instruction is incorrectly recognized asREP Op(0)
without reporting any error from decode. TheENDBR64
instruction has the byte sequence0xF3, 0x0F, 0x1E, 0xFA
and was introduced as part of the Control-flow Enforcement Technology Specification: https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf/cc: @rsc @minux
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