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I came across some bugs in the mips rules while reviewing the typed aux conversion for those rules.
Constant shifts require 0-31 as the shift amount. Rules like this:
(SLL x (MOVWconst [c])) => (SLLconst x [c])
Might violate that invariant. Might just need
We should check all the other uses of constant shifts to make sure they obey the invariant listed in the opcode definition. Maybe even define a new aux type
To be clear, I don't think there is an actual code generation bug.
The docs for SRAconst, for example, just say "arg0 >> auxInt, signed". But I don't think that's what it actually does, at least if you interpret
That's what we do on other archs, e.g. for amd64/SHLQconst: