The RISC-V architecture has support for compressed instructions - these are effectively a subset of the standard 4 byte long instructions, which fit in 2 bytes. These compressed instructions have limited functionality, however require half the code size.
Adding support to the assembler is relatively straight forward and from a code generation perspective, things work as expected and the binary runs. However, I keep hitting problems relating to the pcdatavalue tables while building toolchain3 - this is in the form of deadlock loops while generating tracebacks for inline functions, "runtime: invalid pc-encoded table" from symtab.go while handling async pre-empt, etc.
These all seems to suggest that the various PCDATA tables are wrong/broken, however as far as I can tell p.Pc is being set correctly in cmd/internal/obj/riscv. I would also expect that we handle variable instruction sizes (and variable p.Pc steps), given CISC architectures like x86.
Overall it seems like I'm missing something obvious - should things work if p.Pc is set correctly on a per *obj.Prog basis (even with multiple machine instructions with various widths being generated)?
Any suggestions regarding what else I should check?
(will mail out the work in progress code shortly)
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