This fixes two independent problems:
We normally propagate desired registers backwards through opcodes that
are marked resultInArg0. Unfortunately for the desired register
computation, ADDQconst is not marked as resultInArg0. This is because
the amd64 backend can write it out as LEAQ instead if the input and
output registers don't match. For desired register purposes, we want
to treat ADDQconst as resultInArg0, so that we get an ADDQ instead of
a LEAQ if we can.
Desired registers don't currently work for tuple-generating opcodes.
Declare that the desired register applies to the first element of the
tuple, and propagate the desired register back through Select0.
Noticed when fixing #51964
Trust: Keith Randall <email@example.com>
Run-TryBot: Keith Randall <firstname.lastname@example.org>
Reviewed-by: David Chase <email@example.com>
TryBot-Result: Gopher Robot <firstname.lastname@example.org>