cmd/go: add GOMIPS32, GOMIPS64 ISA levels (iii, r1, r2, r5, r6) #60072
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cc @cherrymui |
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See my comment over at #59415 (comment) |
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@randall77 I think that your comment has been addressed: the proposal here is permitting setting @HeliC829 The
I added Do you have any reference to what the different ISA levels mean? I couldn't find one. |
Here is MIPS ISA level ref, at Page 24 of 148 : Golang currently support MIPS To resolve there is letter in ISA level, i think we can use the enum mips_isa level defined in gcc in rules. |
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I know that the situation is very confusing, but it doesn't seem ideal to treat |
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OK, so let us use roman numerals
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From the doc linked above: 
It sounds like GOMIPS64 is a comma-separated list of choices: hardfloat, softfloat, iii, r1, r2, r5, r6. Do I have that right? |
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This proposal has been added to the active column of the proposals project |
rsc
changed the title
Right.
Just FYI: there is no MIPS IV hardware running Linux distribution in practice and even no MIPS V hardware implementation. Besides, in user space, the difference between III, IV and V is tiny. R3 is a significant release but there are only privileged instructions added and no visible user space change compared to R2. Thus, as a minimum requirement, we consider that only defining iii, r1, r2, r5 and r6 should be enough. It is okay to define other ISA levels as reserved, of course, if there is such a demand. |
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In practice since we don't emit code that cares about the difference, GOMIPS32=iii and GOMIPS32=iv and GOMIPS32=v will all mean the same thing, but they exist(ed) and it's easy to include them, so we might as well recognize the full set. |
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Based on the discussion above, this proposal seems like a likely accept. |
Excited news! Thanks for your review.
Did you mean GOMIPS64?
Let me summarize:
Footnotes |
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Change https://go.dev/cl/493816 mentions this issue: |
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Change https://go.dev/cl/485595 mentions this issue: |
It‘s such a good summary. Besides, each newer ISA level is the superset of previous version except for R6 (R6 removed and adjusted some outdated instructions due to the changes in microarchitecture desgin). |
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No change in consensus, so accepted. 🎉 |
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Change https://go.dev/cl/508095 mentions this issue: |
HeliC829
changed the title
Add support for WSBH/DSBH/DSHD instructions, which are introduced in mips{32,64}r2.
WSBH reverse bytes within halfwords for 32-bit word, DSBH reverse bytes within halfwords for 64-bit doubleword, and DSHD reverse halfwords within doublewords. These instructions can be used to optimize byte swaps.
Ref: The MIPS64 Instruction Set, Revision 5.04: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-05.04.pdf
Updates #60072
Change-Id: I31c043150fe8ac03027f413ef4cb2f3e435775e1
Reviewed-on: https://go-review.googlesource.com/c/go/+/493816
TryBot-Result: Gopher Robot <gobot@golang.org>
Reviewed-by: Keith Randall <khr@google.com>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Joel Sing <joel@sing.id.au>
Reviewed-by: Cherry Mui <cherryyz@google.com>
Run-TryBot: Joel Sing <joel@sing.id.au>
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Change https://go.dev/cl/515475 mentions this issue: |
Add support for SEB/SEH instructions, which are introduced in mips32r2. SEB/SEH can be used to sign-extend byte/halfword in registers directly without passing through memory. Ref: The MIPS32 Instruction Set, Revision 5.04: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00086-2B-MIPS32BIS-AFP-05.04.pdf Updates #60072 Change-Id: I33175ae9d943ead5983ac004bd2a158039046d65 Reviewed-on: https://go-review.googlesource.com/c/go/+/515475 TryBot-Result: Gopher Robot <gobot@golang.org> Reviewed-by: Michael Knyszek <mknyszek@google.com> Reviewed-by: Cherry Mui <cherryyz@google.com> Run-TryBot: Joel Sing <joel@sing.id.au>
For GOARCH=mips the Go compiler will use the newer MIPS32-r1 ISA, whereas for GOARCH=mips64 it will use the MIPS-III ISA, which is the highest N64 supports. See golang#60072
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@cherrymui Hi, PTAL on CL 508095, thanks. |
Currently GOMIPS64 accepts hardfloat(as default) and softfloat.
Golang currently support MIPS III or higher. I had submitted two CLs and they take little performance improvement to MIPS64. CL 485635 CL 485595. But those instructions only available after r1 but not MIPS III.
So if we want to get more performance improvement on mips64, we should support more isa level.
We wish that GOMIPS can also accept
r2/r5.I tried introduce some instructions from MIPS R2. The following data shows the test results and performance improvement if we can support newer isa level on mips64x..
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