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cmd/compile: remove amd64's LEA splitting #80310

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@randall77

Our compiler currently splits 3-operand LEAs (base register, index register, and nonzero constant offset) into two separate LEAs. This was introduced because Intel recommended it (Intel Optimization Manual, section 3.5.1.2). The optimization manual states a single 3-operand LEA takes 3 cycles and two 2-operand LEAs take one cycle each. This was originally discussed in #21735.

It seems this recommendation is pretty obsolete. Current processors do not have performance characteristics that would make splitting helpful (all forms of LEA are either 1 or 2 cycles, depending on chip).

@vnmakarov wrote a good summary in CL 797480:

  1. Splitting is necessary only for CPUs from Sandy Bridge (2nd generation) to Coffee Lake (9th generation).
  2. Zen architectures never had a problem with slow 3-part LEA.
  3. The section about using LEA in the Intel optimization guide is stale.
  4. Agner Fog's instruction latency table stops at Ice Lake (10th generation).
  5. It seems the most accurate and complete info is given on uops.info.
  6. GCC splits LEA only for Atom micro-architectures based on AGU (address generation unit) stall analysis.
  7. Two simpler LEA instructions can still have better throughput on some micro-architectures, but I don't think there are real programs where such throughput is necessary.

The latest chip we have confirmed that splitting still helps on is a Intel Core i7-9700K, released October 2018.

I propose we rip out the splitting for 1.28. It will make an old chip 1 cycle slower and probably make more current chips 1 cycle faster.

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Performancearch-386Issues solely affecting the 32-bit x86 architecturearch-amd64compiler/runtimeIssues related to the Go compiler and/or runtime.

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